CoreSight

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[PATCH v2] coresight: etm4x: add CPU hotplug support for probing

by Tamas Zsoldos

etm4x devices cannot be successfully probed when their CPU is offline. For example, when booting with maxcpus=n, ETM probing will fail on CPUs >n, and the probing won't be reattempted once the CPUs come online. This will leave those CPUs unable to make use of ETM. This change adds a mechanism to delay the probing if the corresponding CPU is offline, and to try it again when the CPU comes online. Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> --- Changes from v1 (all suggested by Suzuki): 1. Expanded commit message. 2. The delayed probe now uses etm4_init_arg. 3. Reuses etm4_online_cpu() instead of installing own cpuhp callback. 4. Changed guard condition in etm4_remove_dev(). --- .../coresight/coresight-etm4x-core.c | 153 +++++++++++++----- 1 file changed, 113 insertions(+), 40 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..c39d9055b22c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,13 @@ static enum cpuhp_state hp_online; struct etm4_init_arg { unsigned int pid; - struct etmv4_drvdata *drvdata; + struct device *dev; struct csdev_access *csa; }; +static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); +static int etm4_probe_cpu(unsigned int cpu); + /* * Check if TRCSSPCICRn(i) is implemented for a given instance. * @@ -1071,7 +1074,7 @@ static void etm4_init_arch_data(void *info) struct csdev_access *csa; int i; - drvdata = init_arg->drvdata; + drvdata = dev_get_drvdata(init_arg->dev); csa = init_arg->csa; /* @@ -1514,7 +1517,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) static int etm4_online_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) coresight_enable(etmdrvdata[cpu]->csdev); @@ -1890,48 +1893,20 @@ static void etm4_pm_clear(void) } } -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) { int ret; struct coresight_platform_data *pdata = NULL; - struct etmv4_drvdata *drvdata; + struct device *dev = init_arg->dev; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct coresight_desc desc = { 0 }; - struct etm4_init_arg init_arg = { 0 }; u8 major, minor; char *type_name; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) - pm_save_enable = coresight_loses_context_with_cpu(dev) ? - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; - - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { - drvdata->save_state = devm_kmalloc(dev, - sizeof(struct etmv4_save_state), GFP_KERNEL); - if (!drvdata->save_state) - return -ENOMEM; - } - - drvdata->base = base; - - spin_lock_init(&drvdata->spinlock); - - drvdata->cpu = coresight_get_cpu(dev); - if (drvdata->cpu < 0) - return drvdata->cpu; - - init_arg.drvdata = drvdata; - init_arg.csa = &desc.access; - init_arg.pid = etm_pid; + return -EINVAL; - if (smp_call_function_single(drvdata->cpu, - etm4_init_arch_data, &init_arg, 1)) - dev_err(dev, "ETM arch init failed\n"); + desc.access = *init_arg->csa; if (!drvdata->arch) return -EINVAL; @@ -2002,6 +1977,68 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return 0; } +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +{ + struct etmv4_drvdata *drvdata; + struct csdev_access access = { 0 }; + struct etm4_init_arg init_arg = { 0 }; + struct etm4_init_arg *delayed; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) + pm_save_enable = coresight_loses_context_with_cpu(dev) ? + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; + + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { + drvdata->save_state = devm_kmalloc(dev, + sizeof(struct etmv4_save_state), GFP_KERNEL); + if (!drvdata->save_state) + return -ENOMEM; + } + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + + init_arg.dev = dev; + init_arg.csa = &access; + init_arg.pid = etm_pid; + + /* + * Serialize against CPUHP callbacks to avoid race condition + * between the smp call and saving the delayed probe. + */ + cpus_read_lock(); + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, &init_arg, 1)) { + /* The CPU was offline, try again once it comes online. */ + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); + if (!delayed) { + cpus_read_unlock(); + return -ENOMEM; + } + + *delayed = init_arg; + + per_cpu(delayed_probe, drvdata->cpu) = delayed; + + cpus_read_unlock(); + return 0; + } + cpus_read_unlock(); + + return etm4_add_coresight_dev(&init_arg); +} + static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -2040,6 +2077,35 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) return ret; } +static int etm4_probe_cpu(unsigned int cpu) +{ + int ret; + struct etm4_init_arg init_arg; + struct csdev_access access = { 0 }; + struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); + + if (!iap) + return 0; + + init_arg = *iap; + devm_kfree(init_arg.dev, iap); + *this_cpu_ptr(&delayed_probe) = NULL; + + ret = pm_runtime_resume_and_get(init_arg.dev); + if (ret < 0) { + dev_err(init_arg.dev, "Failed to get PM runtime!\n"); + return 0; + } + + init_arg.csa = &access; + etm4_init_arch_data(&init_arg); + + etm4_add_coresight_dev(&init_arg); + + pm_runtime_put(init_arg.dev); + return 0; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -2054,16 +2120,20 @@ static void clear_etmdrvdata(void *info) int cpu = *(int *)info; etmdrvdata[cpu] = NULL; + per_cpu(delayed_probe, cpu) = NULL; } static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) { - etm_perf_symlink(drvdata->csdev, false); + bool had_delayed_probe; /* * Taking hotplug lock here to avoid racing between etm4_remove_dev() * and CPU hotplug call backs. */ cpus_read_lock(); + + had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu); + /* * The readers for etmdrvdata[] are CPU hotplug call backs * and PM notification call backs. Change etmdrvdata[i] on @@ -2071,12 +2141,15 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) * inside one call back function. */ if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) - etmdrvdata[drvdata->cpu] = NULL; + clear_etmdrvdata(&drvdata->cpu); cpus_read_unlock(); - cscfg_unregister_csdev(drvdata->csdev); - coresight_unregister(drvdata->csdev); + if (!had_delayed_probe) { + etm_perf_symlink(drvdata->csdev, false); + cscfg_unregister_csdev(drvdata->csdev); + coresight_unregister(drvdata->csdev); + } return 0; } -- 2.17.1

3 years, 4 months

Re: [PATCH v6] coresight: etm4x: avoid build failure with unrolled loops

by Suzuki K Poulose

On 10/07/2022 20:13, Arnd Bergmann wrote: > On Sat, Jul 9, 2022 at 1:15 AM Nick Desaulniers <ndesaulniers(a)google.com> wrote: > >> ({ \ >> u64 __val; \ >> \ >> - if (__builtin_constant_p((offset))) \ >> + if (__is_constexpr((offset))) \ >> __val = read_etm4x_sysreg_const_offset((offset)); \ >> else \ >> __val = etm4x_sysreg_read((offset), true, (_64bit)); \ >> > > This is clearly better than the current version using > __builtin_constant_p(), but > I don't think it's safe in all cases, since there are expressions that > are constant > expressions to the compiler but are not valid input to the assembler. > > I would prefer to see this fixed differently, but doing this one first is also > fine with me: > > Acked-by: Arnd Bergmann <arnd(a)arndb.de> > > Arnd Thanks, I have queued this. Suzuki

3 years, 4 months

Patch series to add to and imporve tests for CoreSight

by carsten.haitzler＠foss.arm.com

This improves how perf test handles finding shell scripts to run as part of the testing allowing sub-directories, skipping files that are not intentional shell script tests and then adds a set of tests that improve what we cover for Arm CoreSight testing. The goal of these tests is to expand the scenarios and data traced and examined to track quality of trace data and improvements to that over time. Eventually it'd be neater to break up the current Arm CoreSight tests into smaller focused tests that share the same infrastructure, but this here would be a first step.

3 years, 4 months

Re: [PATCH 14/14] perf test: Add relevant documentation about CoreSight testing

by Carsten Haitzler

On 7/2/22 04:02, Bagas Sanjaya wrote: > On Fri, Jul 01, 2022 at 01:08:03PM +0100, carsten.haitzler(a)foss.arm.com wrote: >> From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> >> > > Hi Carsten, > > This doc patch can be improved, see below. I'll look at addressing the below - with some exceptions as they are not what you think they are. >> This adds/improves documentation helping people get started with >> CoreSight and perf as well as describing the testing and how it works. >> > > Use imperative mood instead of descriptive one for patch description. > >> Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> >> --- >> .../trace/coresight/coresight-perf.rst | 160 ++++++++++++++++++ >> tools/perf/Documentation/arm-coresight.txt | 5 + >> 2 files changed, 165 insertions(+) >> create mode 100644 Documentation/trace/coresight/coresight-perf.rst >> create mode 100644 tools/perf/Documentation/arm-coresight.txt >> >> diff --git a/Documentation/trace/coresight/coresight-perf.rst b/Documentation/trace/coresight/coresight-perf.rst >> new file mode 100644 >> index 000000000000..de25082447dd >> --- /dev/null >> +++ b/Documentation/trace/coresight/coresight-perf.rst >> @@ -0,0 +1,160 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +================ >> +CoreSight - Perf >> +================ >> + >> + :Author: Carsten Haitzler <carsten.haitzler(a)arm.com> >> + :Date: June 29th, 2022 >> + >> +Perf is able to locally access CoreSight trace data and store it to the >> +output perf data files. This data can then be later decoded to give the >> +instructions that were traced for debugging or profiling purposes. You >> +can log such data with a perf record command like: >> + >> + perf record -e cs_etm//u testbinary >> + > > Use literal code block. > >> +This would run some test binary (testbinary) until it exits and record >> +a perf.data trace file. That file would have AUX sections if CoreSight >> +is working correctly. You can dump the content of this file as >> +readable text with a command like: >> + >> + perf report --stdio --dump -i perf.data >> + > > Same as above. > >> +You should find some sections of this file have AUX data blocks like: >> + >> + 0x1e78 [0x30]: PERF_RECORD_AUXTRACE size: 0x11dd0 offset: 0 ref: 0x1b614fc1061b0ad1 idx: 0 tid: 531230 cpu: -1 >> + >> + . ... CoreSight ETM Trace data: size 73168 bytes >> + Idx:0; ID:10; I_ASYNC : Alignment Synchronisation. >> + Idx:12; ID:10; I_TRACE_INFO : Trace Info.; INFO=0x0 { CC.0 } >> + Idx:17; ID:10; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000000000000000; >> + Idx:26; ID:10; I_TRACE_ON : Trace On. >> + Idx:27; ID:10; I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFFB6069140; Ctxt: AArch64,EL0, NS; >> + Idx:38; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE >> + Idx:39; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE >> + Idx:40; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE >> + Idx:41; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEN >> + ... >> + > > Here too. > >> +If you see these above, then your system is tracing CoreSight data >> +correctly. >> + >> +To compile perf with CoreSight support in the tools/perf directory do >> + >> + make CORESIGHT=1 >> + > > Here too again. > >> +This requires OpenCSD to build. You may install distribution packages >> +for the support such as libopencsd and libopencsd-dev or download it >> +and build yourself. Upstream OpenCSD is located at: >> + >> + https://github.com/Linaro/OpenCSD >> + >> +For complete information on building perf with CoreSight support and >> +more extensive usage look at: >> + >> + https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md >> + >> + >> +Kernel CoreSight Support >> +------------------------ >> + >> +You will also want CoreSight support enabled in your kernel config. >> +Ensure it is enabled with: >> + >> + CONFIG_CORESIGHT=y >> + >> +There are various other CoreSight options you probably also want >> +enabled like: >> + >> + CONFIG_CORESIGHT_LINKS_AND_SINKS=y >> + CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y >> + CONFIG_CORESIGHT_CATU=y >> + CONFIG_CORESIGHT_SINK_TPIU=y >> + CONFIG_CORESIGHT_SINK_ETBV10=y >> + CONFIG_CORESIGHT_SOURCE_ETM4X=y >> + CONFIG_CORESIGHT_STM=y >> + CONFIG_CORESIGHT_CPU_DEBUG=y >> + CONFIG_CORESIGHT_CTI=y >> + CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y >> + > > Same as above again. > >> +Please refer to the kernel configuration help for more information. >> + >> +Perf test - Verify kernel and userspace perf CoreSight work >> +----------------------------------------------------------- >> + >> +When you run perf test, it will do a lot of self tests. Some of those >> +tests will cover CoreSight (only if enabled and on ARM64). You >> +generally would run perf test from the tools/perf directory in the >> +kernel tree. Some tests will check some internal perf support like: >> + >> + Check Arm CoreSight trace data recording and synthesized samples >> + Check Arm SPE trace data recording and synthesized samples >> + > > Use bullet lists. Actually this would be a code block - it is literally the stdout from perf test (just 2 lines of it for those tests). >> +Some others will actually use perf record and some test binaries that >> +are in tests/shell/coresight and will collect traces to ensure a >> +minimum level of functionality is met. The scripts that launch these >> +tests are in the same directory. These will all look like: >> + >> + CoreSight / ASM Pure Loop >> + CoreSight / Memcpy 16k 10 Threads >> + CoreSight / Thread Loop 10 Threads - Check TID >> + ... >> + > > Same as above. This too - a code block. >> +These perf record tests will not run if the tool binaries do not exist >> +in tests/shell/coresight/*/ and will be skipped. If you do not have >> +CoreSight support in hardware then either do not build perf with >> +CoreSight support or remove these binaries in order to not have these >> +tests fail and have them skip instead. >> + >> +These tests will log historical results in the current working >> +directory (e.g. tools/perf) and will be named stats-*.csv like: >> + >> + stats-asm_pure_loop-out.csv >> + stats-memcpy_thread-16k_10.csv >> + ... >> + > > These above causes htmldocs warning (unescaped wildcard), so I have to apply > the fixup: > > ---- >8 ---- > > diff --git a/Documentation/trace/coresight/coresight-perf.rst b/Documentation/trace/coresight/coresight-perf.rst > index de25082447dd50..a25fcda5c37c55 100644 > --- a/Documentation/trace/coresight/coresight-perf.rst > +++ b/Documentation/trace/coresight/coresight-perf.rst > @@ -102,13 +102,13 @@ tests are in the same directory. These will all look like: > ... > > These perf record tests will not run if the tool binaries do not exist > -in tests/shell/coresight/*/ and will be skipped. If you do not have > +in tests/shell/coresight/\*/ and will be skipped. If you do not have > CoreSight support in hardware then either do not build perf with > CoreSight support or remove these binaries in order to not have these > tests fail and have them skip instead. > > These tests will log historical results in the current working > -directory (e.g. tools/perf) and will be named stats-*.csv like: > +directory (e.g. tools/perf) and will be named stats-\*.csv like: > > stats-asm_pure_loop-out.csv > stats-memcpy_thread-16k_10.csv > > ---- >8 ---- > > Also, the output list above could be inside code block (since these > are output). Yup. >> +These statistic files log some aspects of the AUX data sections in >> +the perf data output counting some numbers of certain encodings (a >> +good way to know that it's working in a very simple way). One problem >> +with CoreSight is that given a large enough amount of data needing to >> +be logged, some of it can be lost due to the processor not waking up >> +in time to read out all the data from buffers etc.. You will notice >> +that the amount of data collected can vary a lot per run of perf test. >> +If you wish to see how this changes over time, simply run perf test >> +multiple times and all these csv files will have more and more data >> +appended to it that you can later examine, graph and otherwise use to >> +figure out if things have become worse or better. >> + >> +This means sometimes these tests fail as they don't capture all the >> +data needed. This is about tracking quality and amount of data >> +produced over time and to see when changes to the Linux kernel improve >> +quality of traces. >> + >> +Be aware that some of these tests take quite a while to run, specifically >> +in processing the perf data file and dumping contents to then examine what >> +is inside. >> + >> +You can change where these csv logs are stored by setting the >> +PERF_TEST_CORESIGHT_STATDIR environment variable before running perf >> +test like: >> + >> + export PERF_TEST_CORESIGHT_STATDIR=/var/tmp >> + perf test >> + >> +They will also store resulting perf output data in the current >> +directory for later inspection like: >> + >> + perf-asm_pure_loop-out.data >> + perf-memcpy_thread-16k_10.data >> + ... >> + >> +You can alter where the perf data files are stored by setting the >> +PERF_TEST_CORESIGHT_DATADIR environment variable such as: >> + >> + PERF_TEST_CORESIGHT_DATADIR=/var/tmp >> + perf test >> + > > Use code block. > >> +You may wish to set these above environment variables if you whish to >> +keep the output of tests outside of the current working directory for >> +longer term storage and examination. >> diff --git a/tools/perf/Documentation/arm-coresight.txt b/tools/perf/Documentation/arm-coresight.txt >> new file mode 100644 >> index 000000000000..f94743a4d161 >> --- /dev/null >> +++ b/tools/perf/Documentation/arm-coresight.txt >> @@ -0,0 +1,5 @@ >> +Arm CoreSight Support >> +===================== >> + >> +Please see docuentation in the central CoreSight location in the >> +kernel tree under Documentation/trace/coresight > > s/ducuentation/documentation/ > > So here's the improv: > > ---- >8 ---- > > diff --git a/Documentation/trace/coresight/coresight-perf.rst b/Documentation/trace/coresight/coresight-perf.rst > index a25fcda5c37c55..0dd4689a699ecd 100644 > --- a/Documentation/trace/coresight/coresight-perf.rst > +++ b/Documentation/trace/coresight/coresight-perf.rst > @@ -10,37 +10,37 @@ CoreSight - Perf > Perf is able to locally access CoreSight trace data and store it to the > output perf data files. This data can then be later decoded to give the > instructions that were traced for debugging or profiling purposes. You > -can log such data with a perf record command like: > +can log such data with a perf record command like:: > > - perf record -e cs_etm//u testbinary > + perf record -e cs_etm//u testbinary > > This would run some test binary (testbinary) until it exits and record > a perf.data trace file. That file would have AUX sections if CoreSight > is working correctly. You can dump the content of this file as > -readable text with a command like: > +readable text with a command like:: > > - perf report --stdio --dump -i perf.data > + perf report --stdio --dump -i perf.data > > -You should find some sections of this file have AUX data blocks like: > +You should find some sections of this file have AUX data blocks like:: > > - 0x1e78 [0x30]: PERF_RECORD_AUXTRACE size: 0x11dd0 offset: 0 ref: 0x1b614fc1061b0ad1 idx: 0 tid: 531230 cpu: -1 > + 0x1e78 [0x30]: PERF_RECORD_AUXTRACE size: 0x11dd0 offset: 0 ref: 0x1b614fc1061b0ad1 idx: 0 tid: 531230 cpu: -1 > > - . ... CoreSight ETM Trace data: size 73168 bytes > - Idx:0; ID:10; I_ASYNC : Alignment Synchronisation. > - Idx:12; ID:10; I_TRACE_INFO : Trace Info.; INFO=0x0 { CC.0 } > - Idx:17; ID:10; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000000000000000; > - Idx:26; ID:10; I_TRACE_ON : Trace On. > - Idx:27; ID:10; I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFFB6069140; Ctxt: AArch64,EL0, NS; > - Idx:38; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > - Idx:39; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > - Idx:40; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > - Idx:41; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEN > - ... > + . ... CoreSight ETM Trace data: size 73168 bytes > + Idx:0; ID:10; I_ASYNC : Alignment Synchronisation. > + Idx:12; ID:10; I_TRACE_INFO : Trace Info.; INFO=0x0 { CC.0 } > + Idx:17; ID:10; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000000000000000; > + Idx:26; ID:10; I_TRACE_ON : Trace On. > + Idx:27; ID:10; I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFFB6069140; Ctxt: AArch64,EL0, NS; > + Idx:38; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > + Idx:39; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > + Idx:40; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE > + Idx:41; ID:10; I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEN > + ... > > If you see these above, then your system is tracing CoreSight data > correctly. > > -To compile perf with CoreSight support in the tools/perf directory do > +To compile perf with CoreSight support in the tools/perf directory do:: > > make CORESIGHT=1 > > @@ -60,23 +60,23 @@ Kernel CoreSight Support > ------------------------ > > You will also want CoreSight support enabled in your kernel config. > -Ensure it is enabled with: > +Ensure it is enabled with:: > > - CONFIG_CORESIGHT=y > + CONFIG_CORESIGHT=y > > There are various other CoreSight options you probably also want > -enabled like: > +enabled like:: > > - CONFIG_CORESIGHT_LINKS_AND_SINKS=y > - CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y > - CONFIG_CORESIGHT_CATU=y > - CONFIG_CORESIGHT_SINK_TPIU=y > - CONFIG_CORESIGHT_SINK_ETBV10=y > - CONFIG_CORESIGHT_SOURCE_ETM4X=y > - CONFIG_CORESIGHT_STM=y > - CONFIG_CORESIGHT_CPU_DEBUG=y > - CONFIG_CORESIGHT_CTI=y > - CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y > + CONFIG_CORESIGHT_LINKS_AND_SINKS=y > + CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y > + CONFIG_CORESIGHT_CATU=y > + CONFIG_CORESIGHT_SINK_TPIU=y > + CONFIG_CORESIGHT_SINK_ETBV10=y > + CONFIG_CORESIGHT_SOURCE_ETM4X=y > + CONFIG_CORESIGHT_STM=y > + CONFIG_CORESIGHT_CPU_DEBUG=y > + CONFIG_CORESIGHT_CTI=y > + CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y > > Please refer to the kernel configuration help for more information. > > @@ -88,18 +88,18 @@ tests will cover CoreSight (only if enabled and on ARM64). You > generally would run perf test from the tools/perf directory in the > kernel tree. Some tests will check some internal perf support like: > > - Check Arm CoreSight trace data recording and synthesized samples > - Check Arm SPE trace data recording and synthesized samples > +* Check Arm CoreSight trace data recording and synthesized samples > +* Check Arm SPE trace data recording and synthesized samples > > Some others will actually use perf record and some test binaries that > are in tests/shell/coresight and will collect traces to ensure a > minimum level of functionality is met. The scripts that launch these > tests are in the same directory. These will all look like: > > - CoreSight / ASM Pure Loop > - CoreSight / Memcpy 16k 10 Threads > - CoreSight / Thread Loop 10 Threads - Check TID > - ... > +* CoreSight / ASM Pure Loop > +* CoreSight / Memcpy 16k 10 Threads > +* CoreSight / Thread Loop 10 Threads - Check TID > +* etc. > > These perf record tests will not run if the tool binaries do not exist > in tests/shell/coresight/\*/ and will be skipped. If you do not have > @@ -108,11 +108,11 @@ CoreSight support or remove these binaries in order to not have these > tests fail and have them skip instead. > > These tests will log historical results in the current working > -directory (e.g. tools/perf) and will be named stats-\*.csv like: > +directory (e.g. tools/perf) and will be named stats-\*.csv like:: > > - stats-asm_pure_loop-out.csv > - stats-memcpy_thread-16k_10.csv > - ... > + stats-asm_pure_loop-out.csv > + stats-memcpy_thread-16k_10.csv > + ... > > These statistic files log some aspects of the AUX data sections in > the perf data output counting some numbers of certain encodings (a > @@ -137,23 +137,23 @@ is inside. > > You can change where these csv logs are stored by setting the > PERF_TEST_CORESIGHT_STATDIR environment variable before running perf > -test like: > +test like:: > > - export PERF_TEST_CORESIGHT_STATDIR=/var/tmp > - perf test > + export PERF_TEST_CORESIGHT_STATDIR=/var/tmp > + perf test > > They will also store resulting perf output data in the current > -directory for later inspection like: > +directory for later inspection like:: > > - perf-asm_pure_loop-out.data > - perf-memcpy_thread-16k_10.data > - ... > + perf-asm_pure_loop-out.data > + perf-memcpy_thread-16k_10.data > + ... > > You can alter where the perf data files are stored by setting the > -PERF_TEST_CORESIGHT_DATADIR environment variable such as: > +PERF_TEST_CORESIGHT_DATADIR environment variable such as:: > > - PERF_TEST_CORESIGHT_DATADIR=/var/tmp > - perf test > + PERF_TEST_CORESIGHT_DATADIR=/var/tmp > + perf test > > You may wish to set these above environment variables if you whish to > keep the output of tests outside of the current working directory for > diff --git a/tools/perf/Documentation/arm-coresight.txt b/tools/perf/Documentation/arm-coresight.txt > index f94743a4d161f2..c117fc50a2a956 100644 > --- a/tools/perf/Documentation/arm-coresight.txt > +++ b/tools/perf/Documentation/arm-coresight.txt > @@ -1,5 +1,5 @@ > Arm CoreSight Support > ===================== > > -Please see docuentation in the central CoreSight location in the > -kernel tree under Documentation/trace/coresight > +For full documentation, see Documentation/trace/coresight/coresight-perf.rst > +in the kernel tree. > > ---- >8 ---- > > Note: since this is documentation patch, don't forget to Cc linux-doc list. > I add it for you. I'll split this out to a separate stand-alone patch from this series. I put docs in the place I was told to by the perf coresight maintainers, but that now complicates everyone to send the patch series to and so only the docs are relevant to the doc mailing list, so I'll split it off.

3 years, 4 months

Re: [PATCH] coresight: etm4x: add CPU hotplug support for probing

by Suzuki K Poulose

Hi Tamas Thanks for the patch. I have tested this on my Juno board and it works fine. I have some comments inline. On 16/06/2022 16:18, Tamas Zsoldos wrote: > etm4x devices cannot be successfully probed when their CPU is offline. > This adds a mechanism to delay the probing in this case and try again > once the CPU is brought online. It may be worth elaborating this a bit. e.g, "For e.g., if the system is booted with maxcpus=n, the ETM won't be probed on CPUs n+1, even when the CPUs are brought up online later" , > > Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> > --- > .../coresight/coresight-etm4x-core.c | 195 ++++++++++++++---- > 1 file changed, 155 insertions(+), 40 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 7f416a12000e..f0bff08e9de9 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -70,6 +70,14 @@ struct etm4_init_arg { > struct csdev_access *csa; > }; > > +struct etm4_delayed_probe { > + u32 etm_pid; > + struct device *dev; > +}; > + > +static DEFINE_PER_CPU(struct etm4_delayed_probe *, delayed_probe); > +static enum cpuhp_state hp_probe; I am wondering if we can reuse the existing hotplug notifier ? See more on this below. > + > /* > * Check if TRCSSPCICRn(i) is implemented for a given instance. > * > @@ -1938,48 +1946,20 @@ static void etm4_pm_clear(void) > } > } > > -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > +static int etm4_add_coresight_dev(struct device *dev, > + struct csdev_access *access) Could this be : etm4_add_coresight_dev(struct etm4_init_arg *init_arg) That provides us with "access". Also if replace init_arg.drvdata field with init_arg.dev we can use that for etm4_init_arch_data() and etm4_add_coresight_dev. we can get to drvdata from the dev via, dev_get_drvdata(dev). > { > int ret; > struct coresight_platform_data *pdata = NULL; > - struct etmv4_drvdata *drvdata; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); > struct coresight_desc desc = { 0 }; > - struct etm4_init_arg init_arg = { 0 }; > u8 major, minor; > char *type_name; > > - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > - return -ENOMEM; > - > - dev_set_drvdata(dev, drvdata); > - > - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) > - pm_save_enable = coresight_loses_context_with_cpu(dev) ? > - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; > - > - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { > - drvdata->save_state = devm_kmalloc(dev, > - sizeof(struct etmv4_save_state), GFP_KERNEL); > - if (!drvdata->save_state) > - return -ENOMEM; > - } > - > - drvdata->base = base; > - > - spin_lock_init(&drvdata->spinlock); > - > - drvdata->cpu = coresight_get_cpu(dev); > - if (drvdata->cpu < 0) > - return drvdata->cpu; > - > - init_arg.drvdata = drvdata; > - init_arg.csa = &desc.access; > - init_arg.pid = etm_pid; > + return -EINVAL; > > - if (smp_call_function_single(drvdata->cpu, > - etm4_init_arch_data, &init_arg, 1)) > - dev_err(dev, "ETM arch init failed\n"); > + desc.access = *access; > > if (!drvdata->arch) > return -EINVAL; > @@ -2050,6 +2030,69 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > return 0; > } > > +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > +{ > + struct etmv4_drvdata *drvdata; > + struct csdev_access access = { 0 }; > + struct etm4_init_arg init_arg = { 0 }; > + struct etm4_delayed_probe *delayed; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + dev_set_drvdata(dev, drvdata); > + > + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) > + pm_save_enable = coresight_loses_context_with_cpu(dev) ? > + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; > + > + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { > + drvdata->save_state = devm_kmalloc(dev, > + sizeof(struct etmv4_save_state), GFP_KERNEL); > + if (!drvdata->save_state) > + return -ENOMEM; > + } > + > + drvdata->base = base; > + > + spin_lock_init(&drvdata->spinlock); > + > + drvdata->cpu = coresight_get_cpu(dev); > + if (drvdata->cpu < 0) > + return drvdata->cpu; > + > + init_arg.drvdata = drvdata; > + init_arg.csa = &access; > + init_arg.pid = etm_pid; > + > + /* > + * Serialize against CPUHP callbacks to avoid race condition > + * between the smp call and saving the delayed probe. > + */ > + cpus_read_lock(); > + if (smp_call_function_single(drvdata->cpu, > + etm4_init_arch_data, &init_arg, 1)) { > + /* The CPU was offline, try again once it comes online. */ > + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); > + if (!delayed) { > + cpus_read_unlock(); > + return -ENOMEM; > + } > + > + delayed->etm_pid = etm_pid; > + delayed->dev = dev; > + > + per_cpu(delayed_probe, drvdata->cpu) = delayed; > + > + cpus_read_unlock(); > + return 0; > + } > + cpus_read_unlock(); > + > + return etm4_add_coresight_dev(dev, &access); > +} > + > static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) > { > void __iomem *base; > @@ -2088,6 +2131,64 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) > return ret; > } > > +static int etm4_probe_cpu(unsigned int cpu) > +{ > + int ret; > + struct etm4_delayed_probe di; > + struct csdev_access access = { 0 }; > + struct etm4_init_arg init_arg; > + struct etm4_delayed_probe *dp = *this_cpu_ptr(&delayed_probe); This could be called from the existing etm4_starting_cpu() ? static int etm4_starting_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); spin_lock(&etmdrvdata[cpu]->spinlock); if (!etmdrvdata[cpu]->os_unlock) etm4_os_unlock(etmdrvdata[cpu]); if (local_read(&etmdrvdata[cpu]->mode)) etm4_enable_hw(etmdrvdata[cpu]); spin_unlock(&etmdrvdata[cpu]->spinlock); } > + > + if (!dp) > + return 0; > + > + di = *dp; > + devm_kfree(di.dev, dp); > + *this_cpu_ptr(&delayed_probe) = NULL; > + > + ret = pm_runtime_resume_and_get(di.dev); > + if (ret < 0) { > + dev_err(di.dev, "Failed to get PM runtime!\n"); > + return 0; > + } > + > + init_arg.drvdata = dev_get_drvdata(di.dev); > + if (!init_arg.drvdata) > + return 0; > + > + init_arg.csa = &access; > + init_arg.pid = di.etm_pid; > + etm4_init_arch_data(&init_arg); > + > + etm4_add_coresight_dev(di.dev, &access); > + > + pm_runtime_put(di.dev); > + return 0; > +} > + > +static int etm4_setup_cpuhp_probe(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, > + "arm/coresight4:delayed_probe", > + etm4_probe_cpu, NULL); > + > + if (ret > 0) { > + hp_probe = ret; > + return 0; > + } > + return ret; > +} > + > +static void etm4_remove_cpuhp_probe(void) > +{ > + if (hp_probe) > + cpuhp_remove_state_nocalls(hp_probe); > + > + hp_probe = 0; > +} > + And we could get rid of the above ^^ > static struct amba_cs_uci_id uci_id_etm4[] = { > { > /* ETMv4 UCI data */ > @@ -2102,16 +2203,20 @@ static void clear_etmdrvdata(void *info) > int cpu = *(int *)info; > > etmdrvdata[cpu] = NULL; > + per_cpu(delayed_probe, cpu) = NULL; > } > > static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) > { > - etm_perf_symlink(drvdata->csdev, false); > + bool had_dev; > /* > * Taking hotplug lock here to avoid racing between etm4_remove_dev() > * and CPU hotplug call backs. > */ > cpus_read_lock(); > + > + had_dev = etmdrvdata[drvdata->cpu]; > + Is this ever false ? Why do we need this change ? How does this patch affect the tear down ? Suzuki

3 years, 4 months

[PATCH v4 0/7] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load and unload are provided to in the /config/cs-syscfg subsytem base group to implement the load functionality. Routines to generate binary configuration files are supplied in ./tools/coresight. Example generator and reader applications are provided. Tools may be cross compiled or built for use on host system. Documentation is updated to describe feature usage. Changes since v3: 1) Rebase & tested on coresight/next - 5.19-rc3 - which includes the fix patch for earlier configfs works. 2) Lockdep investigations resulted in re-design of some of the code accessing configfs. 3) moved load and unload attributes to root of cs-syscfg. (Mathieu) 4) Additional minor fixes suggested by Mathieu. 5) Memory for configfs loaded and unloaded configurations is now explicitly freed. 6) LOCKDEP nesting fix for configfs base code (fs/configfs/dir.c) Changes since v2: 1) Rebased & tested on coresight/next - 5.18-rc2 2) Moved coresight config generator and reader programs from samples to tools/coresight. Docs updated to match. (suggested by Mathieu) 3) userspace builds now use userspace headers from tools/... 4) Other minor fixes from Mathieu's review. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (7): coresight: configfs: Update memory allocation / free for configfs elements coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: tools: Add config file write and reader tools Documentation: coresight: docs for config load via configfs configfs: Fix LOCKDEP nesting issues with fragment semaphores .../trace/coresight/coresight-config.rst | 202 +++++- MAINTAINERS | 1 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 583 ++++++++++++++++++ .../coresight/coresight-config-file.h | 139 +++++ .../hwtracing/coresight/coresight-config.h | 27 + .../coresight/coresight-syscfg-configfs.c | 300 +++++++-- .../coresight/coresight-syscfg-configfs.h | 3 + .../hwtracing/coresight/coresight-syscfg.c | 107 ++++ .../hwtracing/coresight/coresight-syscfg.h | 2 + fs/configfs/configfs_internal.h | 3 + fs/configfs/dir.c | 45 ++ tools/coresight/Makefile | 52 ++ tools/coresight/coresight-cfg-bufw.c | 309 ++++++++++ tools/coresight/coresight-cfg-bufw.h | 26 + tools/coresight/coresight-cfg-example1.c | 62 ++ tools/coresight/coresight-cfg-example2.c | 95 +++ tools/coresight/coresight-cfg-examples.h | 22 + tools/coresight/coresight-cfg-file-gen.c | 61 ++ tools/coresight/coresight-cfg-file-read.c | 227 +++++++ tools/coresight/coresight-config-uapi.h | 76 +++ 21 files changed, 2298 insertions(+), 46 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 tools/coresight/Makefile create mode 100644 tools/coresight/coresight-cfg-bufw.c create mode 100644 tools/coresight/coresight-cfg-bufw.h create mode 100644 tools/coresight/coresight-cfg-example1.c create mode 100644 tools/coresight/coresight-cfg-example2.c create mode 100644 tools/coresight/coresight-cfg-examples.h create mode 100644 tools/coresight/coresight-cfg-file-gen.c create mode 100644 tools/coresight/coresight-cfg-file-read.c create mode 100644 tools/coresight/coresight-config-uapi.h -- 2.17.1

3 years, 4 months

[PATCH v11 0/9] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series "coresight: Add new API to allocate trace source ID values". https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220308205000.… Changes from V10: 1. Change dev_info to dev_dbg in TPDM/TPDA drivers. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Merge sysfs API change of integration_test to integration_test driver change. -- -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Mao Jinlong (9): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add coresight components arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 111 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++ MAINTAINERS | 2 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 671 ++++++++++++++++++ drivers/hwtracing/coresight/Kconfig | 23 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 206 ++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 + drivers/hwtracing/coresight/coresight-tpdm.c | 259 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 ++ include/linux/coresight.h | 1 + 13 files changed, 1508 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

3 years, 4 months

Re: [PATCH next] Documentation: coresight: escape coresight bindings file wildcard

by Mathieu Poirier

On Thu, Jun 30, 2022 at 05:13:17PM +0700, Bagas Sanjaya wrote: > Stephen Rothwell reported htmldocs warning: > > Documentation/trace/coresight/coresight.rst:133: WARNING: Inline emphasis start-string without end-string. > > The warning above is due to unescaped wildcard asterisk (*) on CoreSight > devicetree binding filename, which confuses Sphinx as emphasis instead. > > Escape the wildcard to fix the warning. > > Link: https://lore.kernel.org/linux-next/20220630173801.41bf22a2@canb.auug.org.au/ > Fixes: 3c15fddf312120 ("dt-bindings: arm: Convert CoreSight bindings to DT schema") > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Cc: Jonathan Corbet <corbet(a)lwn.net> > Cc: Rob Herring <robh(a)kernel.org> > Cc: coresight(a)lists.linaro.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-next(a)vger.kernel.org > Cc: linux-kernel(a)vger.kernel.org > Reported-by: Stephen Rothwell <sfr(a)canb.auug.org.au> > Signed-off-by: Bagas Sanjaya <bagasdotme(a)gmail.com> > --- > Documentation/trace/coresight/coresight.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied. Thanks, Mathieu > diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst > index 529b7c80e6f353..1644a0244ad10a 100644 > --- a/Documentation/trace/coresight/coresight.rst > +++ b/Documentation/trace/coresight/coresight.rst > @@ -130,7 +130,7 @@ Misc: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/arm,coresight-*.yaml for details. > +See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. > > As of this writing drivers for ITM, STMs and CTIs are not provided but are > expected to be added as the solution matures. > > base-commit: 6cc11d2a1759275b856e464265823d94aabd5eaf > -- > An old man doll... just what I always wanted! - Clara >

3 years, 4 months

[PATCH v5 0/2] Fix lockdep issues seen in CoreSight configfs interface

by Mike Leach

Issues with lockdep possible deadlock scenarios have been reported when using the coresight configfs interface handling complex configuration, when unloading modules. These are due to holding the main configuration mutex during configfs register, but taking it later when accessing configfs files. The patches improve the clean up of configurations and update load and unload of configurations and initialisation of configfs to fix the locking mechanisms. Applies to coresight/next (5.19-rc2) Tested on DB410c (with patch [0] also applied to fix separate console boot issue). Fixes: eb2ec49606c2 ("coresight: syscfg: Update load API for config loadable modules") Reported-by: Suzuki Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> [0] https://lkml.kernel.org/r/20220614124618.2830569-1-suzuki.poulose@arm.com Changes since v4: No functional change - fixed comment in patch header 1/2 and error string format to remove checkpatch warning as requested by Mathieu. Changes since v3: Addressed minor issues raised by Suzuki. Changes since v2: Added additional work to fix load and unload ops after issue recurred due to file access. Mike Leach (2): coresight: configfs: Fix unload of configurations on module exit coresight: syscfg: Update load and unload operations .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-syscfg.c | 298 +++++++++++++++--- .../hwtracing/coresight/coresight-syscfg.h | 13 + 3 files changed, 261 insertions(+), 52 deletions(-) -- 2.17.1

3 years, 4 months

Problems with On-Device Trace Capturing

by finn.burmester＠student.uni-luebeck.de

Hi, sorry for bothering you but I hope this is the right place for my questions, as I am kind of stuck right now. I am an undergrad student and currently experimenting with on-device Coresight Tracing. As a board I use the STM32MP157A-DK1, which has some Coresight devices, especially ETM v3.5 for the two A7 cores (32 Bit) and an ETF as a sink. I’d like to use CSAL for trace capturing and OpenCSD for trace decoding, but I’m facing some issues that I don’t understand. For tracing I use the “tracedemo” application from CSAL. As I want to trace userspace-code, I removed the kernel dump part from cs_util_create_snapshot. Except from this, I left everything unchanged, although I have already played around with some configurations. To avoid problems that may be caused by cpuidle, I pass the kernel parameter nohlt on boot, as suggested here in another thread. I also disabled ASLR. For the board configuration I added this function ```c static int do_registration_stm32(struct cs_devices_t *devices) { enum { A7_0, A7_1 }; cs_device_t funnel, etf, cti, etm, timestamp_gen, tpiu, cscti; //register the rom tables cs_register_romtable(0x50080000); cs_register_romtable(0x50090000); //CPU affinities /* ETM */ cs_device_set_affinity(cs_device_register(0x500DC000), A7_0); cs_device_set_affinity(cs_device_register(0x500DD000), A7_1); /* CTIs */ cs_device_set_affinity(cs_device_register(0x500D8000), A7_0); cs_device_set_affinity(cs_device_register(0x500D9000), A7_1); //register other devices timestamp_gen = cs_device_register(0x50082000); // funnels funnel = cs_device_get(0x50091000); cs_atb_register(cs_cpu_get_device(A7_0, CS_DEVCLASS_SOURCE), 0, funnel, 0); cs_atb_register(cs_cpu_get_device(A7_1, CS_DEVCLASS_SOURCE), 0, funnel, 1); //get the TPIU tpiu = cs_device_get(0x50093000); //get the ETF devices->etb = cs_device_get(0x50092000); /* It's ETF, not ETB actually */ cs_atb_register(funnel, 0, devices->etb, 0); cs_atb_register(devices->etb, 0, tpiu, 0); cscti = cs_device_register(0x50094000); /* the linux board probe does not set up CPUIDs correctly for stm32 - hardcode here for both linux and BAREMETAL. */ devices->cpu_id[0] = 0xC07; devices->cpu_id[1] = 0xC07; return 0; } ``` My Test-target application is as simple as this: ```c int main() { int a[20]; for (int i=0; i<10;i++) { a[i] = 1+i; } for (int i=0; i<13;i++) { a[i] = i; } return 0; } ``` The objdump of my target program looks like this: ```c 000103a0 <main>: 103a0: b480 push {r7} 103a2: b097 sub sp, #92 ; 0x5c 103a4: af00 add r7, sp, #0 103a6: 2300 movs r3, #0 103a8: 657b str r3, [r7, #84] ; 0x54 103aa: e00b b.n 103c4 <main+0x24> 103ac: 6d7b ldr r3, [r7, #84] ; 0x54 103ae: 1c5a adds r2, r3, #1 103b0: 6d7b ldr r3, [r7, #84] ; 0x54 103b2: 009b lsls r3, r3, #2 103b4: f107 0158 add.w r1, r7, #88 ; 0x58 103b8: 440b add r3, r1 103ba: f843 2c58 str.w r2, [r3, #-88] 103be: 6d7b ldr r3, [r7, #84] ; 0x54 103c0: 3301 adds r3, #1 103c2: 657b str r3, [r7, #84] ; 0x54 103c4: 6d7b ldr r3, [r7, #84] ; 0x54 103c6: 2b09 cmp r3, #9 103c8: ddf0 ble.n 103ac <main+0xc> 103ca: 2300 movs r3, #0 103cc: 653b str r3, [r7, #80] ; 0x50 103ce: e00a b.n 103e6 <main+0x46> 103d0: 6d3b ldr r3, [r7, #80] ; 0x50 103d2: 009b lsls r3, r3, #2 103d4: f107 0258 add.w r2, r7, #88 ; 0x58 103d8: 4413 add r3, r2 103da: 6d3a ldr r2, [r7, #80] ; 0x50 103dc: f843 2c58 str.w r2, [r3, #-88] 103e0: 6d3b ldr r3, [r7, #80] ; 0x50 103e2: 3301 adds r3, #1 103e4: 653b str r3, [r7, #80] ; 0x50 103e6: 6d3b ldr r3, [r7, #80] ; 0x50 103e8: 2b0c cmp r3, #12 103ea: ddf1 ble.n 103d0 <main+0x30> 103ec: 2300 movs r3, #0 103ee: 4618 mov r0, r3 103f0: 375c adds r7, #92 ; 0x5c 103f2: 46bd mov sp, r7 103f4: f85d 7b04 ldr.w r7, [sp], #4 103f8: 4770 bx lr ``` I start the trace capture with the command ./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name STM32 so that I only trace my main function. Then I start my target program and after this I stop the tracing. I try to look at the raw trace with OpenCSD, but I only get the following output: ```c $ ~/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister: CS Decode library testing ----------------------------------------------- ** Library Version : 1.3.1 Test Command Line:- /home/finn/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 bc bc bc b8 bc bc b8 bc Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 16; ID_DATA[0x10]; bc d4 bc bc bc bc bc bc bc bc bc bc ec 94 Idx:16; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 32; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 48 bytes. ``` So the trace stream seems to be not synchronized, but I have no idea why. I played around with the sync frequency, and set it to something low like 8. ```c cs_device_write(dev, CS_ETMSYNCFR, 8); ``` Then I get some readable trace, but of course the overhead is absurd. Also the trace only starts from 0x000103a8, while I would expect the first packet to be an i-sync for 0x000103a0, as this is the first address of my filter condition. ```c Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 00 00 00 00 00 80 90 08 Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Idx:6; ID:10; A_SYNC : Alignment Synchronisation. Idx:12; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 16; ID_DATA[0x10]; 09 a9 03 01 00 00 00 00 00 00 80 88 08 09 c5 Idx:13; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103a8; NS; ISA=Thumb2; Idx:21; ID:10; A_SYNC : Alignment Synchronisation. Idx:27; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 32; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 ad 03 01 Idx:28; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:35; ID:10; A_SYNC : Alignment Synchronisation. Idx:41; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 48; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 b3 03 01 00 00 Idx:42; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:49; ID:10; A_SYNC : Alignment Synchronisation. Idx:55; ID:10; P_HDR : Atom P-header.; EEE Idx:56; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 64; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 bb 03 01 00 00 00 00 Idx:62; ID:10; A_SYNC : Alignment Synchronisation. Idx:69; ID:10; P_HDR : Atom P-header.; EEE Idx:70; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 80; ID_DATA[0x10]; 00 00 80 8c 08 09 c3 03 01 00 00 00 00 00 00 Idx:76; ID:10; A_SYNC : Alignment Synchronisation. Idx:83; ID:10; P_HDR : Atom P-header.; EEE Idx:84; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 96; ID_DATA[0x10]; 80 88 08 09 c7 03 01 00 00 00 00 00 00 80 88 Idx:90; ID:10; A_SYNC : Alignment Synchronisation. Idx:97; ID:10; P_HDR : Atom P-header.; EE Idx:98; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:104; ID:10; A_SYNC : Alignment Synchronisation. Idx:110; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 112; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:112; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:118; ID:10; A_SYNC : Alignment Synchronisation. Idx:124; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 128; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb Idx:125; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:132; ID:10; A_SYNC : Alignment Synchronisation. Idx:138; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 144; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 Idx:139; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:147; ID:10; A_SYNC : Alignment Synchronisation. Idx:153; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 160; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 Idx:154; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:161; ID:10; A_SYNC : Alignment Synchronisation. Idx:167; ID:10; P_HDR : Atom P-header.; EE Idx:168; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 176; ID_DATA[0x10]; 00 00 00 00 80 88 08 09 ad 03 01 00 00 00 00 Idx:174; ID:10; A_SYNC : Alignment Synchronisation. Idx:181; ID:10; P_HDR : Atom P-header.; EE Idx:182; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Frame Data; Index 192; ID_DATA[0x10]; 00 00 80 8c 08 09 b3 03 01 00 00 00 00 00 00 Idx:188; ID:10; A_SYNC : Alignment Synchronisation. Idx:195; ID:10; P_HDR : Atom P-header.; EEE Idx:196; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 208; ID_DATA[0x10]; 80 8c 08 09 bb 03 01 00 00 00 00 00 00 80 8c Idx:202; ID:10; A_SYNC : Alignment Synchronisation. Idx:209; ID:10; P_HDR : Atom P-header.; EEE Idx:210; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:216; ID:10; A_SYNC : Alignment Synchronisation. Idx:222; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 224; ID_DATA[0x10]; 08 09 c3 03 01 00 00 00 00 00 00 80 88 08 09 Idx:224; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:230; ID:10; A_SYNC : Alignment Synchronisation. Idx:236; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 240; ID_DATA[0x10]; c7 03 01 00 00 00 00 00 00 80 88 08 09 ad 03 Idx:237; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:244; ID:10; A_SYNC : Alignment Synchronisation. Idx:250; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 256; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 b3 03 01 Idx:251; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:258; ID:10; A_SYNC : Alignment Synchronisation. Idx:264; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 272; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 00 Idx:265; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:273; ID:10; A_SYNC : Alignment Synchronisation. Idx:279; ID:10; P_HDR : Atom P-header.; EEE Idx:280; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 288; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 00 Idx:286; ID:10; A_SYNC : Alignment Synchronisation. Idx:293; ID:10; P_HDR : Atom P-header.; EEE Idx:294; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 304; ID_DATA[0x10]; 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 00 Idx:300; ID:10; A_SYNC : Alignment Synchronisation. Idx:307; ID:10; P_HDR : Atom P-header.; EE Idx:308; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 320; ID_DATA[0x10]; 80 88 08 09 ad 03 01 00 00 00 00 00 00 80 8c Idx:314; ID:10; A_SYNC : Alignment Synchronisation. Idx:321; ID:10; P_HDR : Atom P-header.; EE Idx:322; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:328; ID:10; A_SYNC : Alignment Synchronisation. Idx:334; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 336; ID_DATA[0x10]; 08 09 b3 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:336; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:342; ID:10; A_SYNC : Alignment Synchronisation. Idx:348; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 352; ID_DATA[0x10]; bb 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 Idx:349; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:356; ID:10; A_SYNC : Alignment Synchronisation. Idx:362; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 368; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 Idx:363; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:370; ID:10; A_SYNC : Alignment Synchronisation. Idx:376; ID:10; P_HDR : Atom P-header.; EE Idx:377; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 384; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 b1 03 01 00 00 Idx:384; ID:10; A_SYNC : Alignment Synchronisation. Idx:390; ID:10; P_HDR : Atom P-header.; EEEE Idx:391; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 400; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 b9 03 01 00 00 00 00 Idx:397; ID:10; A_SYNC : Alignment Synchronisation. Idx:405; ID:10; P_HDR : Atom P-header.; EEE Idx:406; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 416; ID_DATA[0x10]; 00 00 80 88 08 09 bf 03 01 00 00 00 00 00 00 Idx:412; ID:10; A_SYNC : Alignment Synchronisation. Idx:419; ID:10; P_HDR : Atom P-header.; EE Idx:420; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Frame Data; Index 432; ID_DATA[0x10]; 80 8c 08 09 c5 03 01 00 00 00 00 00 00 80 8c Idx:426; ID:10; A_SYNC : Alignment Synchronisation. Idx:433; ID:10; P_HDR : Atom P-header.; EEE Idx:434; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:440; ID:10; A_SYNC : Alignment Synchronisation. Idx:446; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 448; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:448; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:454; ID:10; A_SYNC : Alignment Synchronisation. Idx:460; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 464; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb 03 Idx:461; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:468; ID:10; A_SYNC : Alignment Synchronisation. Idx:474; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 480; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 00 Idx:475; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:482; ID:10; A_SYNC : Alignment Synchronisation. Idx:488; ID:10; P_HDR : Atom P-header.; EEE Idx:489; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 496; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 00 Idx:496; ID:10; A_SYNC : Alignment Synchronisation. Idx:502; ID:10; P_HDR : Atom P-header.; EE Idx:503; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 512; ID_DATA[0x10]; 00 00 00 80 90 08 09 b1 03 01 00 00 00 00 Idx:509; ID:10; A_SYNC : Alignment Synchronisation. Idx:516; ID:10; P_HDR : Atom P-header.; EEEE Idx:517; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 528; ID_DATA[0x10]; 00 00 80 8c 08 09 b9 03 01 00 00 00 00 00 00 Idx:523; ID:10; A_SYNC : Alignment Synchronisation. Idx:531; ID:10; P_HDR : Atom P-header.; EEE Idx:532; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 544; ID_DATA[0x10]; 80 88 08 09 bf 03 01 00 00 00 00 00 00 80 8c Idx:538; ID:10; A_SYNC : Alignment Synchronisation. Idx:545; ID:10; P_HDR : Atom P-header.; EE Idx:546; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:552; ID:10; A_SYNC : Alignment Synchronisation. Idx:558; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 560; ID_DATA[0x10]; 08 09 c5 03 01 00 00 00 00 00 00 80 90 08 09 Idx:560; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:566; ID:10; A_SYNC : Alignment Synchronisation. Idx:572; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 576; ID_DATA[0x10]; af 03 01 00 00 00 00 00 00 80 88 08 09 b3 03 Idx:573; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ae; NS; ISA=Thumb2; Idx:580; ID:10; A_SYNC : Alignment Synchronisation. Idx:586; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 592; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 Idx:587; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:594; ID:10; A_SYNC : Alignment Synchronisation. Idx:600; ID:10; P_HDR : Atom P-header.; EEE Idx:601; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 608; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 Idx:608; ID:10; A_SYNC : Alignment Synchronisation. Idx:614; ID:10; P_HDR : Atom P-header.; EEE Idx:615; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 624; ID_DATA[0x10]; 00 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 Idx:621; ID:10; A_SYNC : Alignment Synchronisation. Idx:628; ID:10; P_HDR : Atom P-header.; EE Idx:629; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 640; ID_DATA[0x10]; 00 80 90 08 09 b1 03 01 00 00 00 00 00 00 Idx:635; ID:10; A_SYNC : Alignment Synchronisation. Idx:642; ID:10; P_HDR : Atom P-header.; EEEE Idx:643; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 656; ID_DATA[0x10]; 80 8c 08 09 b9 03 01 00 00 00 00 00 00 80 88 Idx:649; ID:10; A_SYNC : Alignment Synchronisation. Idx:657; ID:10; P_HDR : Atom P-header.; EEE Idx:658; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Idx:664; ID:10; A_SYNC : Alignment Synchronisation. Idx:670; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 672; ID_DATA[0x10]; 08 09 bf 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:672; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:678; ID:10; A_SYNC : Alignment Synchronisation. Idx:684; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 688; ID_DATA[0x10]; c5 03 01 00 c8 00 00 00 00 00 80 08 09 cb 03 Idx:685; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:692; ID:10; P_HDR : Atom P-header.; EEN Idx:693; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 704; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e7 03 01 00 Idx:699; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ca; NS; ISA=Thumb2; Idx:706; ID:10; A_SYNC : Alignment Synchronisation. Idx:712; ID:10; P_HDR : Atom P-header.; EEE Idx:713; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e6; NS; ISA=Thumb2; Frame Data; Index 720; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 d1 03 01 00 00 00 Idx:720; ID:10; A_SYNC : Alignment Synchronisation. Idx:726; ID:10; P_HDR : Atom P-header.; EEE Idx:727; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 736; ID_DATA[0x10]; 00 00 00 80 88 08 09 d5 03 01 00 00 00 00 00 Idx:733; ID:10; A_SYNC : Alignment Synchronisation. Idx:740; ID:10; P_HDR : Atom P-header.; EE Idx:741; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 752; ID_DATA[0x10]; 00 80 8c 08 09 dd 03 01 00 00 00 00 00 00 80 Idx:747; ID:10; A_SYNC : Alignment Synchronisation. Idx:754; ID:10; P_HDR : Atom P-header.; EEE Idx:755; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:761; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 768; ID_DATA[0x10]; 8c 08 09 e5 03 01 00 00 00 00 00 00 80 88 Idx:768; ID:10; P_HDR : Atom P-header.; EEE Idx:769; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:775; ID:10; A_SYNC : Alignment Synchronisation. Idx:781; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 784; ID_DATA[0x10]; 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:784; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:790; ID:10; A_SYNC : Alignment Synchronisation. Idx:796; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 800; ID_DATA[0x10]; d3 03 01 00 00 00 00 00 00 80 90 08 09 dd 03 Idx:797; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:804; ID:10; A_SYNC : Alignment Synchronisation. Idx:810; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 816; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 00 Idx:811; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:818; ID:10; A_SYNC : Alignment Synchronisation. Idx:824; ID:10; P_HDR : Atom P-header.; EEE Idx:825; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 832; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 00 Idx:832; ID:10; A_SYNC : Alignment Synchronisation. Idx:838; ID:10; P_HDR : Atom P-header.; EE Idx:839; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 848; ID_DATA[0x10]; 00 00 00 80 88 08 09 d1 03 01 00 00 00 00 00 Idx:845; ID:10; A_SYNC : Alignment Synchronisation. Idx:852; ID:10; P_HDR : Atom P-header.; EE Idx:853; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 864; ID_DATA[0x10]; 00 80 88 08 09 d5 03 01 00 00 00 00 00 00 80 Idx:859; ID:10; A_SYNC : Alignment Synchronisation. Idx:866; ID:10; P_HDR : Atom P-header.; EE Idx:867; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:873; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 880; ID_DATA[0x10]; 8c 08 09 dd 03 01 00 00 00 00 00 00 80 8c 08 Idx:880; ID:10; P_HDR : Atom P-header.; EEE Idx:881; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:887; ID:10; A_SYNC : Alignment Synchronisation. Idx:893; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 896; ID_DATA[0x10]; 09 e5 03 01 00 00 00 00 00 00 80 88 08 09 e9 Idx:894; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:901; ID:10; A_SYNC : Alignment Synchronisation. Idx:907; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 912; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 d1 03 Idx:908; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:915; ID:10; A_SYNC : Alignment Synchronisation. Idx:921; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 928; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 d5 03 01 00 Idx:922; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:930; ID:10; A_SYNC : Alignment Synchronisation. Idx:936; ID:10; P_HDR : Atom P-header.; EE Idx:937; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 944; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 dd 03 01 00 00 00 Idx:944; ID:10; A_SYNC : Alignment Synchronisation. Idx:950; ID:10; P_HDR : Atom P-header.; EEE Idx:951; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 960; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:957; ID:10; A_SYNC : Alignment Synchronisation. Idx:964; ID:10; P_HDR : Atom P-header.; EEE Idx:965; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 976; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:971; ID:10; A_SYNC : Alignment Synchronisation. Idx:978; ID:10; P_HDR : Atom P-header.; EE Idx:979; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:985; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 992; ID_DATA[0x10]; 8c 08 09 d3 03 01 00 00 00 00 00 00 80 90 08 Idx:992; ID:10; P_HDR : Atom P-header.; EEE Idx:993; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:999; ID:10; A_SYNC : Alignment Synchronisation. Idx:1005; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1008; ID_DATA[0x10]; 09 dd 03 01 00 00 00 00 00 00 80 8c 08 09 e5 Idx:1006; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1013; ID:10; A_SYNC : Alignment Synchronisation. Idx:1019; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1024; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 e9 03 01 Idx:1020; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1027; ID:10; A_SYNC : Alignment Synchronisation. Idx:1033; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1040; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 d3 03 01 00 Idx:1034; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1041; ID:10; A_SYNC : Alignment Synchronisation. Idx:1047; ID:10; P_HDR : Atom P-header.; EEE Idx:1048; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1056; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 dd 03 01 00 00 00 Idx:1056; ID:10; A_SYNC : Alignment Synchronisation. Idx:1062; ID:10; P_HDR : Atom P-header.; EEEE Idx:1063; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1072; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:1069; ID:10; A_SYNC : Alignment Synchronisation. Idx:1076; ID:10; P_HDR : Atom P-header.; EEE Idx:1077; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 1088; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:1083; ID:10; A_SYNC : Alignment Synchronisation. Idx:1090; ID:10; P_HDR : Atom P-header.; EE Idx:1091; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1097; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1104; ID_DATA[0x10]; 88 08 09 d1 03 01 00 00 00 00 00 00 80 88 08 Idx:1104; ID:10; P_HDR : Atom P-header.; EE Idx:1105; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:1111; ID:10; A_SYNC : Alignment Synchronisation. Idx:1117; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1120; ID_DATA[0x10]; 09 d5 03 01 00 00 00 00 00 00 80 8c 08 09 dd Idx:1118; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:1125; ID:10; A_SYNC : Alignment Synchronisation. Idx:1131; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1136; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1132; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1139; ID:10; A_SYNC : Alignment Synchronisation. Idx:1145; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1152; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1146; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1153; ID:10; A_SYNC : Alignment Synchronisation. Idx:1159; ID:10; P_HDR : Atom P-header.; EE Idx:1160; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1168; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 Idx:1166; ID:10; A_SYNC : Alignment Synchronisation. Idx:1173; ID:10; P_HDR : Atom P-header.; EEE Idx:1174; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1184; ID_DATA[0x10]; 00 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1180; ID:10; A_SYNC : Alignment Synchronisation. Idx:1188; ID:10; P_HDR : Atom P-header.; EEEE Idx:1189; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1200; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1195; ID:10; A_SYNC : Alignment Synchronisation. Idx:1202; ID:10; P_HDR : Atom P-header.; EEE Idx:1203; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1209; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1216; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1216; ID:10; P_HDR : Atom P-header.; EE Idx:1217; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1223; ID:10; A_SYNC : Alignment Synchronisation. Idx:1229; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1232; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1230; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1237; ID:10; A_SYNC : Alignment Synchronisation. Idx:1243; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1248; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1244; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1251; ID:10; A_SYNC : Alignment Synchronisation. Idx:1257; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1264; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1258; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1265; ID:10; A_SYNC : Alignment Synchronisation. Idx:1271; ID:10; P_HDR : Atom P-header.; EE Idx:1272; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1280; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1278; ID:10; A_SYNC : Alignment Synchronisation. Idx:1285; ID:10; P_HDR : Atom P-header.; EEE Idx:1286; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1296; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1292; ID:10; A_SYNC : Alignment Synchronisation. Idx:1299; ID:10; P_HDR : Atom P-header.; EEEE Idx:1300; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1312; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1306; ID:10; A_SYNC : Alignment Synchronisation. Idx:1314; ID:10; P_HDR : Atom P-header.; EEE Idx:1315; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1321; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1328; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1328; ID:10; P_HDR : Atom P-header.; EE Idx:1329; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1335; ID:10; A_SYNC : Alignment Synchronisation. Idx:1341; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1344; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1342; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1349; ID:10; A_SYNC : Alignment Synchronisation. Idx:1355; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1360; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1356; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1363; ID:10; A_SYNC : Alignment Synchronisation. Idx:1369; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1376; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1370; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1377; ID:10; A_SYNC : Alignment Synchronisation. Idx:1383; ID:10; P_HDR : Atom P-header.; EE Idx:1384; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1392; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1390; ID:10; A_SYNC : Alignment Synchronisation. Idx:1397; ID:10; P_HDR : Atom P-header.; EEE Idx:1398; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1408; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 00 Idx:1404; ID:10; A_SYNC : Alignment Synchronisation. Idx:1411; ID:10; P_HDR : Atom P-header.; EEEE Idx:1412; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1424; ID_DATA[0x10]; 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1418; ID:10; A_SYNC : Alignment Synchronisation. Idx:1425; ID:10; P_HDR : Atom P-header.; EEE Idx:1426; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1432; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1440; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1440; ID:10; P_HDR : Atom P-header.; EE Idx:1441; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1447; ID:10; A_SYNC : Alignment Synchronisation. Idx:1453; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1456; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1454; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1461; ID:10; A_SYNC : Alignment Synchronisation. Idx:1467; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1472; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1468; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1475; ID:10; A_SYNC : Alignment Synchronisation. Idx:1481; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1488; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 c4 Idx:1482; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1489; ID:10; A_SYNC : Alignment Synchronisation. Idx:1495; ID:10; P_HDR : Atom P-header.; EE Idx:1496; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1502; ID:10; P_HDR : Atom P-header.; EN Frame Data; Index 1504; ID_DATA[0x10]; 00 00 00 00 00 80 08 09 ed 03 01 00 00 00 00 Idx:1504; ID:10; A_SYNC : Alignment Synchronisation. Idx:1510; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ec; NS; ISA=Thumb2; Frame Data; Index 1520; ID_DATA[0x10]; 00 00 80 90 08 09 f5 03 01 00 84 Idx:1516; ID:10; A_SYNC : Alignment Synchronisation. Idx:1523; ID:10; P_HDR : Atom P-header.; EEEE Idx:1524; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103f4; NS; ISA=Thumb2; Idx:1530; ID:10; P_HDR : Atom P-header.; E Frame Data; Index 1530; ID_DATA[0x00]; 00 00 00 Frame Data; Index 1536; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 1552 bytes. ``` As far as I understand the ETM should emit an i-sync packet when the address-range-filter triggers, so the first packet I should see in the trace should be that i-sync packet with the first address of my function. And then I would expect some atoms or other trace. It should be possible to accurately trace also small portions of code (starting from the instruction that triggers the enabling of the ETM), right? I would be very happy if you could tell me if I have understood or done something wrong and would be glad about any hints for successfully obtaining and reading traces on my device. Best regards, Finn

3 years, 4 months

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