CoreSight

coresight@lists.linaro.org

4 participants
2607 discussions

Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready

by James Clark

On 09/01/2023 23:43, Yabin Cui wrote: > Otherwise, it may cause error in AXI bus and result in a kernel panic. Hi Yabin, Thanks for the fix. Do you have a reproducer for this or some more info? For example is it a regression or has it always been there? And on which platform. Thanks James > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 4 +++- > .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++--- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > 3 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 07abf28ad725..c106d142e632 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > struct csdev_access *csa = &csdev->access; > @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { > dev_err(&csdev->dev, > "timeout while waiting for TMC to be Ready\n"); > + return -EBUSY; > } > + return 0; > } > > void tmc_flush_and_stop(struct tmc_drvdata *drvdata) > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 867ad8bb9b0c..2da99dd41ed6 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) > etr_buf->ops->sync(etr_buf, rrp, rwp); > } > > -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > { > u32 axictl, sts; > struct etr_buf *etr_buf = drvdata->etr_buf; > + int rc = 0; > > CS_UNLOCK(drvdata->base); > > /* Wait for TMCSReady bit to be set */ > - tmc_wait_for_tmcready(drvdata); > + rc = tmc_wait_for_tmcready(drvdata); > + if (rc) { > + dev_err(&drvdata->csdev->dev, "not ready ETR isn't enabled\n"); > + CS_LOCK(drvdata->base); > + return rc; > + } > > writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); > writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); > @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > tmc_enable_hw(drvdata); > > CS_LOCK(drvdata->base); > + return rc; > } > > static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > rc = coresight_claim_device(drvdata->csdev); > if (!rc) { > drvdata->etr_buf = etr_buf; > - __tmc_etr_enable_hw(drvdata); > + rc = __tmc_etr_enable_hw(drvdata); > + if (rc) { > + drvdata->etr_buf = NULL; > + coresight_disclaim_device(drvdata->csdev); > + tmc_etr_disable_catu(drvdata); > + } > } > > return rc; > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 66959557cf39..01c0382a29c0 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -255,7 +255,7 @@ struct tmc_sg_table { > }; > > /* Generic functions */ > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > void tmc_flush_and_stop(struct tmc_drvdata *drvdata); > void tmc_enable_hw(struct tmc_drvdata *drvdata); > void tmc_disable_hw(struct tmc_drvdata *drvdata);

3 years

[PATCH v2 0/3] coresight: cti: Add PM runtime call in enable_store

by James Clark

This should be a slight improvement on Jinlong's previous version. Now it's not possible to trigger the error message from pm_runtime_put() by calling disable twice. It's also similar to the original pre-breaking change version where pm_runtime_put() was only called if the device was actually disabled, but with one difference: Previously pm_runtime_put() was only called once for the last disable call, but because of the reference counting in pm_runtime, it should have been called once for each enable call. This meant that the clock would have never been disabled if there were ever multiple enable calls. This is now fixed. The third commit is a refactor and doesn't need to be backported. I removed one of the atomic types because it didn't appear to be required. Maybe it was added for a reason which I'm not aware of, if so it should be pretty easy to drop that change. James Clark (2): coresight: cti: Prevent negative values of enable count coresight: cti: Remove atomic type from enable_req_count Mao Jinlong (1): coresight: cti: Add PM runtime call in enable_store .../hwtracing/coresight/coresight-cti-core.c | 23 ++++++++++++------- .../hwtracing/coresight/coresight-cti-sysfs.c | 15 +++++++++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) base-commit: c767c34740132ffc478226864a7461493cdc2413 -- 2.25.1

3 years

Re: [PATCH v16 0/8] Coresight: Add support for TPDM and TPDA

by Suzuki K Poulose

On 06/01/2023 20:50, Trilok Soni wrote: > On 1/6/2023 1:21 AM, Mao Jinlong wrote: >> This patch series depends on patch series: >> "[v6,00/14] coresight: Add new API to allocate trace source ID values" >> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221123195010.… > > Do we know now when these patches will get revived and accepted to > unblock us? This is all reviewed, and awaiting Peter's Ack for the perf generic change. Once we have that, it will be pushed to coresight tree. Suzuki

3 years

[PATCH v6 00/14] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Appies to coresight/next Changes since v5: (requested by suzuki) 1) Prefer odd ID values for system IDs to avoid overlap with legacy CPU IDs 2) Some style changes Changes since v4: 1) update to ensure that compiling after each individual patch added still works - ie. git bisect not broken through the patchset.. 2) Revision to some of the now redundant code in cs-etm (James) 3) Comments and other minor fixes requested by Suzuki. Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (14): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: perf: traceid: Add perf ID allocation and notifiers coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: trace id: Remove legacy get trace ID function. perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 45 --- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 93 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 73 +++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 298 ++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 156 +++++++++ include/linux/coresight-pmu.h | 34 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 328 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 1024 insertions(+), 231 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

3 years

[PATCH] coresight: cti: Add PM runtime call in enable_store

by Mao Jinlong

In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When enabling CTI by writing enable sysfs node, clock for accessing CTI register won't be enabled. Device will crash due to register access issue. Add PM runtime call in enable_store to fix this issue. Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6d59c815ecf5..b1ed424ae043 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, if (ret) return ret; - if (val) + if (val) { + ret = pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; ret = cti_enable(drvdata->csdev); - else + if (ret) + pm_runtime_put(dev->parent); + } else { ret = cti_disable(drvdata->csdev); + pm_runtime_put(dev->parent); + } if (ret) return ret; return size; -- 2.17.1

3 years

[PATCH v2 0/7] perf cs_etm: Basic support for virtual/kernel timestamps

by James Clark

Changes since v1: * Add 3 refactor commits for sysfs reading around pmu.c as suggested by Arnaldo here [1] * The dependency on [2] has now reached mainline so is no longer blocking * Rebase on perf/core [1]: https://lore.kernel.org/all/YnqVqq5QW%2Fb14oPZ@kernel.org/ [2]: https://lore.kernel.org/all/20220503123537.1003035-1-german.gomez@arm.com/ German Gomez (4): perf pmu: Add function to check if a pmu file exists perf cs_etm: Keep separate symbols for ETMv4 and ETE parameters perf cs_etm: Record ts_source in AUXTRACE_INFO for ETMv4 and ETE perf cs_etm: Set the time field in the synthetic samples James Clark (3): perf: Remove duplication around EVENT_SOURCE_DEVICE_PATH perf: Use perf_pmu__open_file() and perf_pmu__scan_file() perf: Remove remaining duplication of bus/event_source/devices/... tools/perf/arch/arm/util/auxtrace.c | 5 +- tools/perf/arch/arm/util/cs-etm.c | 91 +++++++++++- tools/perf/arch/x86/util/pmu.c | 12 +- tools/perf/tests/evsel-roundtrip-name.c | 3 +- tools/perf/tests/parse-events.c | 3 +- tools/perf/util/cputopo.c | 9 +- tools/perf/util/cs-etm-base.c | 34 +++-- tools/perf/util/cs-etm.c | 86 +++++++++-- tools/perf/util/cs-etm.h | 13 +- tools/perf/util/pmu-hybrid.c | 27 +--- tools/perf/util/pmu-hybrid.h | 2 +- tools/perf/util/pmu.c | 183 ++++++++++-------------- tools/perf/util/pmu.h | 10 +- 13 files changed, 292 insertions(+), 186 deletions(-) base-commit: 573de010917836f198a4e579d40674991659668b -- 2.25.1

3 years

[PATCH v15 0/2] Add support for UltraSoc System Memory Buffer

by Junhao He

Add support for UltraSoc System Memory Buffer. Change since v14: - Add some helpers to the buffer and simplify dumping data according to Jonathan's comment. - Link: https://lore.kernel.org/lkml/20221123123823.27973-1-hejunhao3@huawei.com/ Change since v13: - Modify document and the patches description according to Bagas's comment. - Add dependency on config ACPI, drop redundant enable hw in smb_update_buffer(), Modify smb_purge_data() description according to Suzuki's comment. - Link: https://lore.kernel.org/lkml/20221114090316.63157-1-hejunhao3@huawei.com/ Change since v12: - Modify the code style and add "#ifdef CONFIG_ACPI" according to Jonathan's comment. - Address the comments from Yicong, included drop "buf_base"__iomem attribute, modify the "reading" type to bool and fix FIELD_PREP. - Link: https://lore.kernel.org/lkml/20221109135008.9485-1-hejunhao3@huawei.com/ Change since v11: - Modify the code style and rename the macro according to Jonathan's comment. - Link: https://lore.kernel.org/lkml/20221107130624.59886-1-hejunhao3@huawei.com/ Change since v10: - Rebase onto v6.1-rc4, included similar sysfs register accessors (as same as James's patch) - Link: https://lore.kernel.org/lkml/20221022115929.7503-1-hejunhao3@huawei.com/ Change since v9: - Update the Contact tag in SMB document. - Replace the spinlock with mutex. - Do some clean-ups in "smb_enable()" and "smb_release()". - Use classic memory mapped interface. - Link: https://lore.kernel.org/linux-arm-kernel/20220818132231.28240-1-hejunhao3@h… Change since v8: - Insert a blank line at the end of the config tag in Kconfig according to Randy's comment. - Link: https://lore.kernel.org/linux-arm-kernel/20220816131634.38195-1-hejunhao3@h… Change since v7: - Use the macros for register bit flags and numbers of resource. - Cleanup punctuation. - Update the Date tag and the KernelVersion tag in the document. - Link: https://lore.kernel.org/lkml/20220712091353.34540-1-hejunhao3@huawei.com/ Change since v6: - Modify the code style and driver description according to Suzuki's comment. - Modify configuration of "drvdata->reading", to void problems in open/read concurrency scenario. - Rename the macro of "SMB_FLOW_MASK". - Use the "handle->head" to determine the page number and offset. - Link: https://lore.kernel.org/linux-arm-kernel/20220606130223.57354-1-liuqi115@hu… Change since v5: - Address the comments from Suzuki, add some comments in SMB document, and modify configuration of "drvdata->reading", to void problems in multi-core concurrency scenario - Link: https://lore.kernel.org/linux-arm-kernel/20220416083953.52610-1-liuqi115@hu… Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - Link: https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link: https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi115@hu… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight by Mathieu's comment. - Link: https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB driver .../sysfs-bus-coresight-devices-ultra_smb | 31 + .../trace/coresight/ultrasoc-smb.rst | 83 +++ drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 648 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 125 ++++ 6 files changed, 900 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.33.0

3 years

Re: [PATCH v15 2/2] Documentation: Add document for UltraSoc SMB driver

by hejunhao

On 2022/12/21 12:02, Bagas Sanjaya wrote: > On Tue, Dec 20, 2022 at 05:29:45PM +0800, Junhao He wrote: >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> new file mode 100644 >> index 000000000000..f6526882c627 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> @@ -0,0 +1,31 @@ >> +What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink >> +Date: December 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (RW) Add/remove a SMB device from a trace path. There can be >> + multiple sources for a single SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size >> +Date: December 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the buffer size of each UltraSoc SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status >> +Date: December 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos >> +Date: December 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Read Pointer register. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos >> +Date: December 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Write Pointer register. > s/Read/RO/ and s/value held by/value of/ Ok, will fix it. Thanks. >> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst >> new file mode 100644 >> index 000000000000..056dd120e14c >> --- /dev/null >> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst >> @@ -0,0 +1,83 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +====================================== >> +UltraSoc - HW Assisted Tracing on SoC >> +====================================== >> + :Author: Qi Liu <liuqi115(a)huawei.com> >> + :Date: December 2022 >> + >> +Introduction >> +------------ >> + >> +UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a >> +way to buffer and store CPU trace messages in a region of shared system >> +memory. The device acts as a coresight sink device and the >> +corresponding trace generators (ETM) are attached as source devices. >> + >> +Sysfs files and directories >> +--------------------------- >> + >> +The SMB devices appear on the existing coresight bus alongside other >> +devices:: >> + >> + $# ls /sys/bus/coresight/devices/ >> + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 >> + >> +The ``ultra_smb<N>`` names SMB device associated with SCCL.:: >> + >> + $# ls /sys/bus/coresight/devices/ultra_smb0 >> + enable_sink mgmt >> + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt >> + buf_size buf_status read_pos write_pos >> + >> +Key file items are: >> + >> + * ``read_pos``: Shows the value on the read pointer register. >> + * ``write_pos``: Shows the value on the write pointer register. >> + * ``buf_status``: Shows the value on the status register. >> + BIT(0) is zero value which means the buffer is empty. >> + * ``buf_size``: Shows the buffer size of each device. >> + >> +Firmware Bindings >> +----------------- >> + >> +The device is only supported with ACPI. Its binding describes device >> +identifier, resource information and graph structure. >> + >> +The device is identified as ACPI HID "HISI03A1". Device resources are allocated >> +using the _CRS method. Each device must present two base address; the first one >> +is the configuration base address of the device, the second one is the 32-bit >> +base address of shared system memory. >> + >> +Example:: >> + >> + Device(USMB) { \ >> + Name(_HID, "HISI03A1") \ >> + Name(_CRS, ResourceTemplate() { \ >> + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, NonCacheable, \ >> + ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \ >> + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, Cacheable, \ >> + ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \ >> + }) \ >> + Name(_DSD, Package() { \ >> + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ >> + /* Use CoreSight Graph ACPI bindings to describe connections topology */ >> + Package() { \ >> + 0, \ >> + 1, \ >> + Package() { \ >> + 1, \ >> + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ >> + 8, \ >> + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ >> + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ >> + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ >> + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ >> + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ >> + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ >> + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ >> + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ >> + } \ >> + } \ >> + }) \ >> + } > This doc LGTM, thanks. > > For this doc, > > Reviewed-by: Bagas Sanjaya <bagasdotme(a)gmail.com> Thanks for your comments. Best regards, Junhao.

3 years

by Jinlong Mao

Hi James & Mike, With this patch "[PATCH] coresight: cti: Fix hang in cti_disable_hw()", runtime PM calls are removed in cti_enable_hw/cti_disable_hw. There will be register access issue when write 1 to enable sysfs node of CTI directly as clock is not enabled for accessing CTI registers. echo 1 > cti0/enable static ssize_t enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) Is there fix for the enable_store case ? Thanks Jinlong Mao

3 years

[PATCH v5 0/6] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load and unload are provided to in the /config/cs-syscfg subsytem base group to implement the load functionality. Routines to generate binary configuration files are supplied in ./tools/coresight. Example generator and reader applications are provided. Tools may be cross compiled or built for use on host system. Documentation is updated to describe feature usage. Changes since v4: 1) Update coresight/next - 6.1-rc3 2) Update to lockdep fixes to avoid read lock race in configfs. Changes since v3: 1) Rebase & tested on coresight/next - 5.19-rc3 - which includes the fix patch for earlier configfs works. 2) Lockdep investigations resulted in re-design of some of the code accessing configfs. 3) moved load and unload attributes to root of cs-syscfg. (Mathieu) 4) Additional minor fixes suggested by Mathieu. 5) Memory for configfs loaded and unloaded configurations is now explicitly freed. 6) LOCKDEP nesting fix for configfs base code (fs/configfs/dir.c) Changes since v2: 1) Rebased & tested on coresight/next - 5.18-rc2 2) Moved coresight config generator and reader programs from samples to tools/coresight. Docs updated to match. (suggested by Mathieu) 3) userspace builds now use userspace headers from tools/... 4) Other minor fixes from Mathieu's review. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (6): coresight: configfs: Update memory allocation / free for configfs elements coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: tools: Add config file write and reader tools Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 202 +++++- MAINTAINERS | 1 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 583 ++++++++++++++++++ .../coresight/coresight-config-file.h | 139 +++++ .../hwtracing/coresight/coresight-config.h | 27 + .../coresight/coresight-syscfg-configfs.c | 361 +++++++++-- .../coresight/coresight-syscfg-configfs.h | 4 + .../hwtracing/coresight/coresight-syscfg.c | 137 +++- .../hwtracing/coresight/coresight-syscfg.h | 6 +- tools/coresight/Makefile | 52 ++ tools/coresight/coresight-cfg-bufw.c | 309 ++++++++++ tools/coresight/coresight-cfg-bufw.h | 26 + tools/coresight/coresight-cfg-example1.c | 62 ++ tools/coresight/coresight-cfg-example2.c | 95 +++ tools/coresight/coresight-cfg-examples.h | 22 + tools/coresight/coresight-cfg-file-gen.c | 61 ++ tools/coresight/coresight-cfg-file-read.c | 227 +++++++ tools/coresight/coresight-config-uapi.h | 76 +++ 19 files changed, 2339 insertions(+), 53 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 tools/coresight/Makefile create mode 100644 tools/coresight/coresight-cfg-bufw.c create mode 100644 tools/coresight/coresight-cfg-bufw.h create mode 100644 tools/coresight/coresight-cfg-example1.c create mode 100644 tools/coresight/coresight-cfg-example2.c create mode 100644 tools/coresight/coresight-cfg-examples.h create mode 100644 tools/coresight/coresight-cfg-file-gen.c create mode 100644 tools/coresight/coresight-cfg-file-read.c create mode 100644 tools/coresight/coresight-config-uapi.h -- 2.17.1

3 years

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight