CoreSight November 2026

coresight@lists.linaro.org

3 participants
27 discussions

Re: [PATCH] coresight: fix resource leaks on path build failure

by James Clark

On 09/11/2026 01:24, Jie Gan wrote: > > > On 5/13/2026 9:32 AM, Jie Gan wrote: >> Two related leaks when _coresight_build_path() encounters an error after >> coresight_grab_device() has already incremented the pm_runtime, module, >> and device references for a node: >> >> 1. In _coresight_build_path(), if kzalloc_obj() for the path node fails >> after coresight_grab_device() succeeds, coresight_drop_device() was >> never called, permanently leaking all three references. >> >> 2. In coresight_build_path(), on failure the partial path was freed with >> kfree(path) instead of coresight_release_path(path). kfree() only >> frees the coresight_path struct itself; it does not iterate path_list >> to call coresight_drop_device() and kfree() for each coresight_node >> already added by deeper recursive calls, leaking both the pm_runtime, >> module, and device references and the node memory for every element >> on the partial path. >> >> Fix both by adding coresight_drop_device() in the OOM unwind of >> _coresight_build_path(), and replacing kfree(path) with >> coresight_release_path(path) in coresight_build_path(). >> >> Fixes: 32b0707a4182 ("coresight: Add try_get_module() in >> coresight_grab_device()") >> Fixes: b3e94405941e ("coresight: associating path with session rather >> than tracer") >> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > > Gentle ping. > >> --- >> drivers/hwtracing/coresight/coresight-core.c | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/ >> hwtracing/coresight/coresight-core.c >> index 46f247f73cf6..c1354ea8e11d 100644 >> --- a/drivers/hwtracing/coresight/coresight-core.c >> +++ b/drivers/hwtracing/coresight/coresight-core.c >> @@ -825,8 +825,10 @@ static int _coresight_build_path(struct >> coresight_device *csdev, >> return ret; >> node = kzalloc_obj(struct coresight_node); >> - if (!node) >> + if (!node) { >> + coresight_drop_device(csdev); >> return -ENOMEM; >> + } >> node->csdev = csdev; >> list_add(&node->link, &path->path_list); >> @@ -851,7 +853,7 @@ struct coresight_path *coresight_build_path(struct >> coresight_device *source, >> rc = _coresight_build_path(source, source, sink, path); >> if (rc) { >> - kfree(path); >> + coresight_release_path(path); @Suzuki, there's a conflict here. This will need to be coresight_release_path_locked() if we also take "coresight: etm-perf: Serialize AUX topology access" from my Sashiko fixes. >> return ERR_PTR(rc); >> } >> >> --- >> base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83 >> change-id: 20260513-fix-memory-leak-issue-034b4a45265e >> >> Best regards, >

1 hour, 36 minutes

Re: [PATCH] [v2] coresight: funnel: inport schedule by priority can not take work

by Suzuki K Poulose

On Tue, 27 Oct 2026 23:14:56 +0800, Chao Xu wrote: > The CoreSight SoC-600 TRM, section 10.11.2, PRIORITYCONTROL, a funnel > rejects priority register writes whenever any port is enabled. The > current sequence therefore prevent the configured priorities from > taking effect. Write the priority register before enabling the > first port. > > > [...] Applied, thanks! [1/1] coresight: funnel: inport schedule by priority can not take work https://git.kernel.org/coresight/c/533e91f192eb Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 hour, 58 minutes

Re: [PATCH v3 0/2] fix clock refcount imbalance for all Coresight platform drivers

by Suzuki K Poulose

On Fri, 10 Jul 2026 09:14:46 +0800, Jie Gan wrote: > Found a clock imbalance issue when remove the CTCU module. > > coresight_get_enable_clocks() enables the programming clock and the > optional AT clock through devm_clk_get_optional_enabled(), which also > registers a devm action to call clk_disable_unprepare() when the driver > detaches. > > [...] Applied, thanks! [1/2] coresight: Fix clock refcount imbalance on platform remove https://git.kernel.org/coresight/c/c2d0f71617f4 [2/2] coresight: tnoc: Fix clock refcount imbalance on platform remove https://git.kernel.org/coresight/c/69285a3b57db Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 hour, 58 minutes

Re: [PATCH v2] coresight: tnoc: fix trace ID path assignment failure on non-AMBA tnoc

by Suzuki K Poulose

On Wed, 02 Sep 2026 17:41:43 +0800, Jie Gan wrote: > For a tnoc device not on the AMBA bus, atid was set to -EOPNOTSUPP. > trace_noc_id() returns this value directly to > coresight_path_assign_trace_id(), which only treats a literal 0 > return as "this device has no ID, keep searching the path" - > any other value is checked against IS_VALID_CS_TRACE_ID() and > rejected. A negative atid therefore made path assignment fail with > -EINVAL instead of falling through to the next device in the path > that could supply a valid trace ID. > > [...] Applied, thanks! [1/1] coresight: tnoc: fix trace ID path assignment failure on non-AMBA tnoc https://git.kernel.org/coresight/c/bfe43f1d7905 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 hour, 58 minutes

Re: [PATCH] coresight: tpda: fix race between refcnt check and register access

by Suzuki K Poulose

On Wed, 08 Apr 2026 21:23:44 +0800, Jie Gan wrote: > Several sysfs show/store handlers check csdev->refcnt before acquiring > the spinlock, then access hardware registers inside the lock. This is > a race: between the check and the lock acquisition, the following can > occur on another CPU: > > CPU 0 (sysfs reader) CPU 1 (disable path) > ───────────────────────────── ────────────────────────────────── > refcnt == 1, check passes > [waiting for spinlock] tpda_disable(): refcnt → 0 > debug clock disabled > spinlock acquired > readl_relaxed() ← FAULT/hang > > [...] Applied, thanks! [1/1] coresight: tpda: fix race between refcnt check and register access https://git.kernel.org/coresight/c/4f5f1e5ae120 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 hour, 58 minutes

[PATCH v2 0/9] coresight: Fix assorted bugs reported by Sashiko

by James Clark

Small fixes for bugs in the CoreSight drivers that were found by Sashiko. Mostly reference and resource leaks on error paths, plus a deadlock, a missing lock, and a sysfs store that should return -EBUSY while a sysfs session is enabled. Assisted by Claude Opus 5.5 and Sashiko Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Cherry pick "coresight: etm-perf: Serialize AUX topology access" into this set so that it now has no dependencies. - Drop "coresight: cpu-debug: Fix PM usage counter leak in debug_enable_func()" which is fixed more generally by https://lore.kernel.org/linux-arm-kernel/20260911-b4-coresight-runtime-pm-f… - Link to v1: https://patch.msgid.link/20261027-james-cs-sashiko-easy-fixes-1-v1-0-db43c4… --- James Clark (9): coresight: etm-perf: Serialize AUX topology access coresight: etm4x: Remove perf symlink if config registration fails coresight: etm4x: Fix truncation of nr_ext_inp coresight: etm-perf: Fix sink device reference leak in etm_setup_aux() coresight: syscfg: Take csdev lock when removing owned features coresight: syscfg: Fix deadlock in cscfg_create_device() error path coresight: Fix resource leaks on coresight_build_path() errors coresight: etm3x: Don't ignore etm_parse_event_config() errors coresight: etm3x: Prohibit modifying seq_curr_state while session is enabled drivers/hwtracing/coresight/coresight-core.c | 26 +++++++++++++++++----- drivers/hwtracing/coresight/coresight-etm-perf.c | 15 +++++++++---- drivers/hwtracing/coresight/coresight-etm3x-core.c | 6 ++++- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 5 +++++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-syscfg.c | 8 ++++++- drivers/hwtracing/coresight/coresight-sysfs.c | 4 ++-- 9 files changed, 53 insertions(+), 15 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261027-james-cs-sashiko-easy-fixes-1-692d80016a89 Best regards, -- James Clark <james.clark(a)linaro.org>

1 hour, 58 minutes

Re: [PATCH v6 0/5] Fix traceNoC probe issue on multiple QCOM platforms

by Suzuki K Poulose

On 09/11/2026 01:25, Jie Gan wrote: > > > On 7/10/2026 10:38 AM, Jie Gan wrote: >> The CoreSight TNOC (Trace Network-On-Chip) binding so far only allowed >> the >> two-string AMBA form "qcom,coresight-tnoc", "arm,primecell". That form >> forces the device onto the AMBA bus, where the driver must read the >> peripheral ID from the device registers during probe. On several QCOM >> platforms this AMBA peripheral-ID probing fails, so the traceNoC device >> never probes and its trace path is unavailable. >> >> This series drops the "arm,primecell" entry and turns "qcom,coresight- >> tnoc" >> into a standalone platform compatible. Without "arm,primecell" the device >> is created on the platform bus and probes through the platform driver by >> compatible string, bypassing the AMBA peripheral-ID read while >> remaining a >> fully functional Aggregator TNOC that allocates a system trace ID (ATID). >> >> The series is organized as: binding first, then the driver support for >> the >> platform-bus compatible, followed by the per-platform DT fixes that >> switch >> the affected nodes over to it. >> >> - Patch 1 (dt-bindings) drops "arm,primecell" and makes >> "qcom,coresight-tnoc" a single standalone compatible, and updates the >> example node accordingly. >> - Patch 2 (driver) adds "qcom,coresight-tnoc" to the platform driver's >> match table and renames the itnoc-specific names to generic tnoc names, >> since the platform driver now serves both the Interconnect and Aggregator >> TNOC. It also restricts the ATID-unsupported handling to >> "qcom,coresight-itnoc" only, so the Aggregator TNOC on the platform >> bus is >> no longer wrongly covered and correctly allocates a trace ID. >> - Patches 3-4 (kaanapali, sm8750) drop the "arm,primecell" entry on the >> traceNoC nodes and use the standalone "qcom,coresight-tnoc" compatible, >> fixing the probe failure on those platforms. >> - Patch 5 (glymur) switches the node from "qcom,coresight-itnoc" to >> "qcom,coresight-tnoc". This node is actually an Aggregator TNOC (its >> tn_ag_* endpoints show aggregation), so it should expose a system trace >> ID rather than being treated as an Interconnect TNOC. >> > > Gentle ping. Apologies for missing this. Please could you resend it based on v7.4-rc, as this doesn't apply cleanly on coresight/next Cheers Suzuki

2 hours, 35 minutes

Re: [PATCH] [v2] coresight: funnel: inport schedule by priority can not take work

by James Clark

On 27/10/2026 15:14, Chao Xu wrote: > The CoreSight SoC-600 TRM, section 10.11.2, PRIORITYCONTROL, a funnel > rejects priority register writes whenever any port is enabled. The > current sequence therefore prevent the configured priorities from > taking effect. Write the priority register before enabling the > first port. > > Signed-off-by: Chao Xu <xuchao066(a)163.com> > --- > drivers/hwtracing/coresight/coresight-funnel.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c > index 0abc11f0690c..500ff72a83c8 100644 > --- a/drivers/hwtracing/coresight/coresight-funnel.c > +++ b/drivers/hwtracing/coresight/coresight-funnel.c > @@ -62,13 +62,15 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) > rc = coresight_claim_device_unlocked(csdev); > if (rc) > goto done; > + > + /* Update priorities while all ports are disabled */ > + writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); > } > > functl &= ~FUNNEL_HOLDTIME_MASK; > functl |= FUNNEL_HOLDTIME; > functl |= (1 << port); > writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); > - writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); > done: > CS_LOCK(drvdata->base); > return rc; Reviewed-by: James Clark <james.clark(a)linaro.org>

2 hours, 43 minutes

Re: [PATCH v16 0/7] Provide support for Trigger Generation Unit

by Suzuki K Poulose

Hi On 05/11/2026 12:19, Songwei.Chai wrote: > Hi Suzuki, > > I wanted to follow up and see if you might have some time to take a look > at this patch. Apologies for the delay in responding on this one. But I have now reviewed the series, please address the comments and repost them based on 7.4-rcX Cheers Suzuki > > We’d really appreciate any feedback you may have, as it would help us > determine the next steps and move this work forward. > Thanks for your time. > > Best regards, > Songwei > > On 7/30/2026 4:06 PM, Songwei Chai wrote: >> From: Songwei Chai <songchai(a)qti.qualcomm.com> >> >> We propose creating a new qcom directory under drivers/hwtracing >> to host this TGU driver, as well as additional Qualcomm-specific >> hwtracing drivers that we plan to submit in the coming months. >> This structure will help organize vendor-specific implementations >> and facilitate future development and maintenance. >> >> Feedback from the community on this proposal is highly appreciated. >> >> - Why we are proposing this: >> >> TGU has the ability to monitor signal conditions and trigger debug- >> related >> actions, serving as a programmable hardware component that enhances >> system >> trace and debug capabilities. Placing it under drivers/hwtracing aligns >> with its function as a trace generation utility. >> >> We previously attempted to push this driver to drivers/hwtracing/ >> coresight, >> but did not receive support from the maintainers of the CoreSight >> subsystem. The reason provided was: “This component is primarily a part >> of the Qualcomm proprietary QPMDA subsystem, and is capable of operating >> independently from the CoreSight hardware trace generation system.” >> >> Chat history : https://lore.kernel.org/all/ >> CAJ9a7ViKxHThyZfFFDV_FkNRimk4uo1NrMtQ-kcaj1qO4ZcGnA(a)mail.gmail.com/ >> >> Given this, we have been considering whether it would be appropriate >> to create a dedicated drivers/hwtracing/qcom directory for >> Qualcomm-related hwtracing drivers. This would follow the precedent set >> by Intel, which maintains its own directory at drivers/hwtracing/ >> intel_th. >> We believe this structure would significantly facilitate >> future submissions of related Qualcomm drivers. >> >> - Maintenance of drivers/hwtracing/qcom: >> >> Bjorn, who maintains linux-arm-msm, will be the maintainer of this >> directory — we’ve discussed this with him and he’s aware that his task >> list may grow accordingly. Additionally, Qualcomm engineers familiar with >> the debug hardware — such as [Tingwei Zhang, Jinlong Mao, Songwei Chai], >> will be available to review incoming patches and support ongoing >> development. >> >> - Detail for TGU: >> >> This component can be utilized to sense a plurality of signals and >> create a trigger into the CTI or generate interrupts to processors >> once the input signal meets the conditions. We can treat the TGU’s >> workflow as a flowsheet, it has some “steps” regions for customization. >> In each step region, we can set the signals that we want with priority >> in priority_group, set the conditions in each step via condition_decode, >> and set the resultant action by condition_select. Meanwhile, >> some TGUs (not all) also provide timer/counter functionality. >> Based on the characteristics described above, we consider the TGU as a >> helper in the CoreSight subsystem. Its master device is the TPDM, which >> can transmit signals from other subsystems, and we reuse the existing >> ports mechanism to link the TPDM to the connected TGU. >> >> Here is a detailed example to explain how to use the TGU: >> >> In this example, the TGU is configured to use 2 conditions, 2 steps, and >> the timer. The goal is to look for one of two patterns which are >> generated >> from TPDM, giving priority to one, and then generate a trigger once the >> timer reaches a certain value. In other words, two conditions are used >> for the first step to look for the two patterns, where the one with the >> highest priority is used in the first condition. Then, in the second >> step, >> the timer is enabled and set to be compared to the given value at each >> clock cycle. These steps are better shown below. >> |-----------------| >> | | >> | TPDM | >> | | >> |-----------------| >> | >> | >> --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- >> ------ >> | | >> | >> | | >> |--------------------| | >> | |---- ---> | | Go to next >> steps | | >> | | | |--- ---> | Enable >> timer | | >> | | v | | >> | | >> | | |-----------------| | >> |--------------------| | >> | | | | Yes | | >> | >> | | | inputs==0xB | ----->| | >> <-------- | >> | | | | | | >> No | | >> | No | |-----------------| | >> v | | >> | | | | >> |-----------------| | | >> | | | | | >> | | | >> | | | | | timer>=3 >> |-- | >> | | v | | >> | | >> | | |-----------------| | >> |-----------------| | >> | | | | Yes | | >> | >> | |--- | inputs==0xA | ----->| | >> Yes | >> | | | | >> | >> | |-----------------| >> v | >> | >> |-----------------| | >> | | >> | | >> | | Trigger >> | | >> | | >> | | >> | >> |-----------------| | >> | TGU | >> | >> |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- >> -- | >> | >> v >> |-----------------| >> |The controllers | >> |which will use | >> |triggers further | >> |-----------------| >> >> steps: >> 1. Reset TGU /*it will disable tgu and reset dataset*/ >> - echo 1 > /sys/bus/amba/devices/<tgu-name>/reset_tgu >> >> 2. Set the pattern match for priority0 to 0xA = 0b1010 and for >> priority 1 to 0xB = 0b1011. >> - echo 0x11113232 > /sys/bus/amba/devices/<tgu-name>/ >> step0_priority0/reg0 >> - echo 0x11113233 > /sys/bus/amba/devices/<tgu-name>/ >> step0_priority1/reg0 >> >> Note: >> Bit distribution diagram for each priority register >> >> |-------------------------------------------------------------------| >> | Bits | Field Nam | >> Description | >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> | | | 00 = bypass for OR >> output | >> | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND >> output | >> | | | 10 = sense input '0' is >> true| >> | | | 11 = sense input '1' is >> true| >> >> |-------------------------------------------------------------------| >> These bits are used to identify the signals we want to sense, with >> a maximum signal number of 140. For example, to sense the signal >> 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which >> represents 1010. The remaining bits are set to 1, as we want to use >> AND gate to summarize all the signals we want to sense here. For >> rising or falling edge detection of any input to the priority, set >> the remaining bits to 0 to use an OR gate. >> >> 3. look for the pattern for priority_i i=0,1. >> - echo 0x3 > /sys/bus/amba/devices/<tgu-name>/ >> step0_condition_decode/reg0 >> - echo 0x30 > /sys/bus/amba/devices/<tgu-name>/ >> step0_condition_decode/reg1 >> >> >> |-------------------------------------------------------------------------------| >> | Bits | Field Nam | >> Description | >> >> |-------------------------------------------------------------------------------| >> | | |For each decoded >> condition, this | >> | 24 | NOT |inverts the output. If >> the condition | >> | | |decodes to true, and the >> NOT field | >> | | |is '1', then the output >> is NOT true. | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | 21 | BC0_COMP_ACTIVE |comparator will be >> actively included in| >> | | |the decoding of this >> particular | >> | | | >> condition. | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | | |comparator will need to >> be 1 to affect | >> | 20 | BC0_COMP_HIGH |the decoding of this >> condition. | >> | | |Conversely, a '0' here >> requires a '0' | >> | | |from the >> comparator | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | 17 | |comparator will be >> actively included in| >> | | TC0_COMP_ACTIVE |the decoding of this >> particular | >> | | | >> condition. | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | | |comparator will need to >> be 1 to affect | >> | 16 | TC0_COMP_HIGH |the decoding of this >> particular | >> | | |condition.Conversely, a >> 0 here | >> | | |requires a '0' from the >> comparator | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> Priority_n | >> | | |OR logic will be >> actively | >> | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding >> of | >> | | (n=0,1,2,3) |this particular >> condition. | >> | | | >> | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> Priority_n | >> | | |will need to be '1' to >> affect the | >> | 4n+2 | Priority_n_OR_HIGH |decoding of this >> particular | >> | | (n=0,1,2,3) |condition. Conversely, a >> '0' here | >> | | |requires a '0' from >> Priority_n OR logic| >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> Priority_n | >> | | |AND logic will be >> actively | >> | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding >> of this | >> | | (n=0,1,2,3) |particular >> condition. | >> | | | >> | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> Priority_n | >> | | |AND logic will need to >> be '1' to | >> | 4n | Priority_n_AND_HIGH |affect the decoding of >> this | >> | | (n=0,1,2,3) |particular condition. >> Conversely, | >> | | |a '0' here requires a >> '0' from | >> | | |Priority_n AND >> logic. | >> >> |-------------------------------------------------------------------------------| >> Since we use `priority_0` and `priority_1` with an AND output in >> step 2, we set `0x3` >> and `0x30` here to activate them. >> >> 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions >> are met then the next step will be step 1 and the timer will >> be enabled. >> - echo 0x20008 > /sys/bus/amba/devices/<tgu-name>/ >> step0_condition_select/reg0 >> - echo 0x20008 > /sys/bus/amba/devices/<tgu-name>/ >> step0_condition_select/reg1 >> >> >> |-----------------------------------------------------------------------------| >> | Bits | Field Nam | >> Description | >> >> |-----------------------------------------------------------------------------| >> | | |This field defines the >> next step the | >> | 18:17 | NEXT_STEP |TGU will 'goto' for the >> associated | >> | | |Condition and >> Step. | >> >> |-----------------------------------------------------------------------------| >> | | |For each possible output >> trigger | >> | 13 | TRIGGER |available, set a '1' if >> you want | >> | | |the trigger to go active >> for the | >> | | |associated condition and >> Step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will cause BC0 to >> increment if the| >> | 9 | BC0_INC |associated Condition is >> decoded for | >> | | |this >> step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will cause BC0 to >> decrement if the| >> | 8 | BC0_DEC |associated Condition is >> decoded for | >> | | |this >> step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will clear BC0 count >> value to 0 if| >> | 7 | BC0_CLEAR |the associated Condition >> is decoded | >> | | |for this >> step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will cause TC0 to >> increment until | >> | 3 | TC0_ENABLE |paused or cleared if the >> associated | >> | | |Condition is decoded for >> this step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will cause TC0 to >> pause until | >> | 2 | TC0_PAUSE |enabled if the associated >> Condition | >> | | |is decoded for this >> step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will clear TC0 count >> value to 0 | >> | 1 | TC0_CLEAR |if the associated >> Condition is | >> | | |decoded for this >> step. | >> >> |-----------------------------------------------------------------------------| >> | | |This will set the done >> signal to the | >> | 0 | DONE |TGU FSM if the associated >> Condition | >> | | |is decoded for this >> step. | >> >> |-----------------------------------------------------------------------------| >> Based on the distribution diagram, we set `0x20008` for >> `priority0` and `priority1` to >> achieve "jump to step 1 and enable TC0" once the signal is sensed. >> >> 5. activate the timer comparison for this step. >> - echo 0x30000 > /sys/bus/amba/devices/<tgu-name>/ >> step1_condition_decode/reg0 >> >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | 17 | |comparator will be >> actively included in| >> | | TC0_COMP_ACTIVE |the decoding of this >> particular | >> | | | >> condition. | >> >> |-------------------------------------------------------------------------------| >> | | |When '1' the output from >> the associated| >> | | |comparator will need to >> be 1 to affect | >> | 16 | TC0_COMP_HIGH |the decoding of this >> particular | >> | | |condition.Conversely, a >> 0 here | >> | | |requires a '0' from the >> comparator | >> >> |-------------------------------------------------------------------------------| >> Accroding to the decode distribution diagram , we give 0x30000 >> here to set 16th&17th bit >> to enable timer comparison. >> >> 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once >> the timer >> has reached the given value. >> - echo 0x6 > /sys/bus/amba/devices/<tgu-name>/ >> step1_condition_select/reg0 >> >> 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, >> i.e. when the timer reaches 3. >> - echo 0x2000 > /sys/bus/amba/devices/<tgu-name>/ >> step1_condition_select/default >> >> Note: >> 1. 'default' register allows for establishing the resultant >> action for >> the default condition >> >> 2. Trigger:For each possible output trigger available from >> the Design document, there are three triggers: interrupts, CTI, >> and Cross-TGU mapping.All three triggers can occur, but >> the choice of which trigger to use depends on the user's >> needs. >> >> 8. Compare the timer to 3 in step 1. >> - echo 0x3 > /sys/bus/amba/devices/<tgu-name>/step1_timer/reg0 >> >> 9. enale tgu >> - echo 1 > /sys/bus/amba/devices/<tgu-name>/enable_tgu >> --- >> Link to V15: https://lore.kernel.org/all/20260701055529.445819-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V16: >> - Fixed enable/disable race and PM refcount handling. >> - Fixed sysfs exposure before driver initialization. >> - Fixed priority allocation and access races. >> - Fixed uninitialized return value in condition decode. >> - Fixed sysfs attribute naming collision issues. >> - Added ABI documentation for the default node. >> --- >> Link to V14: https://lore.kernel.org/all/20260417073336.2712426-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V15: >> - Add a maintainer for "drivers/hwtracing/qcom" in MAINTAINERS >> --- >> Link to V13: https://lore.kernel.org/all/20260402092838.341295-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V14: >> - Fix some typos and formatting. >> --- >> Link to V12: https://lore.kernel.org/all/20260317032639.2393221-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V13: >> - add ":" after "KernelVersion" >> - add an enablement check in the enable function to avoid increasing >> the counter each time >> --- >> Link to V11: https://lore.kernel.org/all/ee1ca8e6-8e5f-47d8-8a24- >> f904ee2fc6d0(a)oss.qualcomm.com/ >> >> Changes in V12: >> - Remove the in-ports property from the bindings, as this device is >> decoupled from CoreSight. >> - Update kernel version and date. >> --- >> Link to V10: https://lore.kernel.org/ >> all/20c5406d-3e9f-4fdb-84ba-4cbe629c79b5(a)oss.qualcomm.com/ >> >> Changes in V11: >> - Change the names of members in drvdata: max_xxx -> num_xxx, enable - >> > enabled >> - Use "FIELD_GET" to replace "BMVAL" >> - Use devm_kcalloc to replace devm_kzalloc once create members of >> value_table >> - Keep a consistent \n above return >> - Keep reverse-Christmas-tree style >> - Add checks so that the enable and reset nodes only accept 0 or 1 >> --- >> Link to V9: https://lore.kernel.org/all/20251219065902.2296896-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V10: >> - Modified code formatting based on Jie's feedback to improve >> readability. >> - Applied inverse Christmas tree order to the variables. >> --- >> Link to V8: https://lore.kernel.org/all/20251203090055.2432719-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V9: >> - Decoupled the tgu driver from coresight header file and registered >> it as an amba device. >> - Retained Rob's reviewed-by tag on patch1/7 since the file remains >> unchanged. >> - Updated the sysfs node path in the Documentation directory. >> --- >> Link to V7: https://lore.kernel.org/all/20251104064043.88972-1- >> songwei.chai(a)oss.qualcomm.com/ >> >> Changes in V8: >> - Add "select" section in bindings. >> - Update publish date in "sysfs-bus-coresight-devices-tgu". >> --- >> Link to V6: https://lore.kernel.org/all/20250709104114.22240-1- >> songchai(a)qti.qualcomm.com/ >> >> Changes in V7: >> - Move the TGU code location from 'drivers/hwtracing/coresight/' to >> 'drivers/hwtracing/qcom/'. >> - Rename the spinlock used in the code from 'spinlock' to 'lock'. >> - Perform the 'calculate_array_location' separately, instead of doing >> it within the function. >> - Update the sender email address. >> --- >> Link to V5: https://lore.kernel.org/all/20250529081949.26493-1- >> quic_songchai(a)quicinc.com/ >> >> Changes in V6: >> - Replace spinlock with guard(spinlock) in tgu_enable. >> - Remove redundant blank line. >> - Update publish date and contact member's name in "sysfs-bus- >> coresight-devices-tgu". >> --- >> Link to V4: https://patchwork.kernel.org/project/linux-arm-msm/ >> cover/20250423101054.954066-1-quic_songchai(a)quicinc.com/ >> >> Changes in V5: >> - Update publish date and kernel_version in "sysfs-bus-coresight- >> devices-tgu" >> --- >> Link to V3: https://lore.kernel.org/all/20250227092640.2666894-1- >> quic_songchai(a)quicinc.com/ >> >> Changes in V4: >> - Add changlog in coverletter. >> - Correct 'year' in Copyright in patch1. >> - Correct port mechansim description in patch1. >> - Remove 'tgu-steps','tgu-regs','tgu-conditions','tgu-timer-counters' >> from dt-binding >> and set them through reading DEVID register as per Mike's suggestion. >> - Modify tgu_disable func to make it have single return point in >> patch2 as per >> Mike's suggestion. >> - Use sysfs_emit in enable_tgu_show func in ptach2. >> - Remove redundant judgement in enable_tgu_store in patch2. >> - Correct typo in description in patch3. >> - Set default ret as SYSFS_GROUP_INVISIBLE, and returnret at end in >> pacth3 as >> per Mike's suggestion. >> - Remove tgu_dataset_ro definition in patch3 >> - Use #define constants with explanations of what they are rather than >> arbitrary magic numbers in patch3 and patch4. >> - Check -EINVAL before using 'calculate_array_location()' in array in >> patch4. >> - Add 'default' in 'tgu_dataset_show''s switch part in patch4. >> - Document the value needed to initiate the reset in pacth7. >> - Check "value" in 'reset_tgu_store' and bail out with an error code >> if 0 in patch7. >> - Remove dev_dbg in 'reset_tgu_store' in patch7. >> --- >> Link to V2: https://lore.kernel.org/all/20241010073917.16023-1- >> quic_songchai(a)quicinc.com/ >> >> Changes in V3: >> - Correct typo and format in dt-binding in patch1 >> - Rebase to the latest kernel version >> --- >> Link to V1: https://lore.kernel.org/all/20240830092311.14400-1- >> quic_songchai(a)quicinc.com/ >> >> Changes in V2: >> - Use real name instead of login name, >> - Correct typo and format in dt-binding and code. >> - Bring order in tgu_prob(declarations with and without assignments) >> as per >> Krzysztof's suggestion. >> - Add module device table in patch2. >> - Set const for tgu_common_grp and tgu_ids in patch2. >> - Initialize 'data' in tgu_ids to fix the warning in pacth2. >> --- >> >> Songwei Chai (7): >> dt-bindings: arm: Add support for Qualcomm TGU trace >> qcom-tgu: Add TGU driver >> qcom-tgu: Add signal priority support >> qcom-tgu: Add TGU decode support >> qcom-tgu: Add support to configure next action >> qcom-tgu: Add timer/counter functionality for TGU >> qcom-tgu: Add reset node to initialize >> >> .../ABI/testing/sysfs-bus-amba-devices-tgu | 60 ++ >> .../devicetree/bindings/arm/qcom,tgu.yaml | 71 ++ >> MAINTAINERS | 11 + >> drivers/Makefile | 1 + >> drivers/hwtracing/Kconfig | 2 + >> drivers/hwtracing/qcom/Kconfig | 20 + >> drivers/hwtracing/qcom/Makefile | 3 + >> drivers/hwtracing/qcom/tgu.c | 782 ++++++++++++++++++ >> drivers/hwtracing/qcom/tgu.h | 318 +++++++ >> 9 files changed, 1268 insertions(+) >> create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu >> create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml >> create mode 100644 drivers/hwtracing/qcom/Kconfig >> create mode 100644 drivers/hwtracing/qcom/Makefile >> create mode 100644 drivers/hwtracing/qcom/tgu.c >> create mode 100644 drivers/hwtracing/qcom/tgu.h >>

2 days, 22 hours

Re: [PATCH] Revert "perf/aux: Allocate non-contiguous AUX pages by default"

by Leo Yan

On Wed, Nov 04, 2026 at 12:59:13PM +0000, Will Deacon wrote: [...] > > Sorry for the late reply, and sorry that the commit message in > > 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by default") > > was imprecise about "exacerbating memory fragmentation". You and Dev are > > right that grouping same-lifetime pages into higher-order allocations > > does not itself worsen fragmentation, and the TLB reduction numbers for > > TRBE and SPE with large vmap() mappings make total sense given TRBE's > > tiny TLB. > > > > However, a straight revert will reintroduce a severe production issue we > > hit on Android devices, so I'd like to share what actually happened and > > suggest a way to get large mappings for SPE/TRBE without bringing back > > the regression. > > [...] > > Thanks, Yabin. This just hardens my stance [1] that the allocation decision > should be driven by userspace and not second-guessed by the kernel. So the > revert is _not_ the right approach, in my view. If a userspace interface is needed, what remaining reclaim or allocation policy should userspace control? I am not clear how userspace control would fix the PSI reclaim stalls described in Yabin's reply. Alternatively, we could optimize the reported reclaim cost in the kernel by clearing __GFP_RECLAIM for optional higher-order attempts, while preserving the existing policy at order 0 and for PERF_PMU_CAP_AUX_NO_SG PMUs. If testing confirms this works, combining this mitigation with a revert of 18049c8cff9c would be a reasonable way to restore higher-order allocations for SPE/TRBE without adding a userspace interface. Thanks, Leo

3 days, 3 hours

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight November 2026