CoreSight November 2026

coresight@lists.linaro.org

3 participants
27 discussions

[PATCH v3 00/18] perf cs-etm: Per-thread mode fixes and snapshot wrap support

by James Clark

Fix a few issues with per-thread mode: - On nVHE, everything looks like guest trace instead of host - Tracing multiple threads didn't really work After adding a tests for those, it turns out there were some snapshot bugs not picked up by the other snapshot tests. That showed that the different snapshot searches for Intel BTS and Arm SPE were inconsistent and I think all tracers can benefit from using the same pointer fixup logic, so that gets refactored into the common auxtrace.c. Then SPE can just share the Intel BTS search as it was obviously copied from it originally. IntelPT keeps the more advanced duplicate data search, but in the future that could probably be made the common one and all tracers would benefit from using it (except maybe BTS if it always has a very small buffer, but I doubt the overhead of the duplicate search would be an issue). For now this is more of a refactor rather than behavioral change so don't do that yet. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Keep the find_snapshot() callback instead of adding snapshot_has_wrapped() and monotonic_snapshot_head boolean (Adrian) - Add auxtrace_record__default_find_snapshot() for the simple search for BTS and SPE (Adrian) - Add auxtrace_record__snapshot_fixup() for any snapshot search implementation to use to update the pointers (Adrian) - Reword UINT64_MAX timestamp comment (Leo) - Fix disassembly test after rebasing onto exception sample fixes - Only take 'perf_guest' into account if there is no PIDFMT_CTXTID2 - Improve decoding of old files by hard coding queue 0 for per-thread - Link to v2: https://patch.msgid.link/20260821-james-cs-unformatted-per-thread-fix-v2-0-… Changes in v2: - Remove stale "may be reset to -1 in per-thread mode" comment - Set CPU when queueing auxtrace fragments otherwise auxtrace_queues__add_event() overwrites the queue's CPU - Link to v1: https://patch.msgid.link/20260811-james-cs-unformatted-per-thread-fix-v1-0-… --- James Clark (18): perf cs-etm: Fix nVHE per-thread decoding perf cs-etm: Warn for invalid timestamp option perf cs-etm: Turn on context packet timestamps in per-thread mode perf cs-etm: Use per-CPU queues for per-thread mode perf test: cs-etm: Increase window size in disassembly test perf cs-etm: Don't drop previous target for kernel samples perf python: Expose sample instruction length perf cs-etm: Use instruction length in disassembly script perf cs-etm: Increase default timestamp generation period perf auxtrace: Turn Intel BTS snapshot search into a generic one perf arm-spe: Use generic snapshot search perf auxtrace: intel-pt: Use common snapshot pointer fixup perf cs-etm: Queue partial AUX records perf cs-etm: Don't print missing buffers in snapshot mode perf auxtrace: cs-etm: Capture wrapped snapshots perf test: Allow infinite named_thread loops perf test: cs-etm: Add test for per-thread mode perf test: cs-etm: Test multiple per-thread threads tools/perf/Documentation/perf-test.txt | 2 +- tools/perf/arch/arm/util/cs-etm.c | 34 ++++- tools/perf/arch/arm64/util/arm-spe.c | 147 +-------------------- tools/perf/arch/x86/util/intel-bts.c | 115 +--------------- tools/perf/arch/x86/util/intel-pt.c | 21 +-- tools/perf/python/arm-cs-trace-disasm.py | 22 +-- tools/perf/python/perf.pyi | 1 + .../perf/tests/shell/coresight/per-thread-multi.sh | 76 +++++++++++ tools/perf/tests/shell/coresight/per-thread.sh | 48 +++++++ .../perf/tests/shell/coresight/raw_dump_stress.sh | 5 - .../shell/coresight/test_arm_coresight_disasm.sh | 4 +- tools/perf/tests/workloads/named_threads.c | 7 +- tools/perf/util/auxtrace.c | 145 +++++++++++++++++++- tools/perf/util/auxtrace.h | 18 +++ tools/perf/util/cs-etm.c | 113 +++++++++++----- tools/perf/util/python.c | 1 + 16 files changed, 418 insertions(+), 341 deletions(-) --- base-commit: 790454475c15508d68ccfc4b023642305100f18f change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e prerequisite-message-id: <20261030-perf_cs_etm_fix_non_taken-v3-0-7629b52ab047(a)arm.com> prerequisite-patch-id: 4ef889ad751e344ae47c1d75a2a2e6cb2eadf6e1 prerequisite-patch-id: 636b39730334cbc5a76642c070e704ffe178e7be prerequisite-patch-id: fb58f6daebdf5a194f8aa56ccc4022f932a5a6e5 prerequisite-patch-id: d240c10c6824f8ae6c3f10a1da01226a957f05fb prerequisite-patch-id: 17b291db261e32dcb0d6f1ab2ed0adb7e0411813 prerequisite-patch-id: 45ae1d523c9e5c8c573309f1dab107a598f3d4f8 prerequisite-patch-id: 39a3eb25b3a45f4481760c25fa270773bcfd94f5 prerequisite-patch-id: 5723a15636c2a28ec40eb6b5c9836d162e971786 prerequisite-patch-id: d18054b586fc38bc832ead185e8c1fbb0ce46f39 prerequisite-patch-id: 6735b192189d7945613458abce3da871cb79b35d prerequisite-patch-id: 387cb2c6181bef8f45a8fb167e8ef86e4a54ff69 prerequisite-patch-id: 50243a8d1739141aa24aa371a8452d4d2d078a99 prerequisite-patch-id: 2ae6f1e7707ba0c71a0678331b02d738fb25cb3c prerequisite-patch-id: 1fa0a90cfbc904c4429c1427409125ac44b27aed Best regards, -- James Clark <james.clark(a)linaro.org>

4 days, 2 hours

[PATCH 0/9] coresight: Fix assorted bugs reported by Sashiko

by James Clark

Small fixes for bugs in the CoreSight drivers that were found by Sashiko. Mostly reference and resource leaks on error paths, plus a deadlock, a missing lock, and a sysfs store that should return -EBUSY while a sysfs session is enabled. This series depends on "coresight: Prevent per-thread events from sharing a sink" v4 [1]. That series takes coresight_mutex for perf AUX setup and adds coresight_release_path_locked(), which the etm_setup_aux() and coresight_build_path() fixes here are based on. [1]: https://lore.kernel.org/r/20261016-james-cs-multiple-per-threads-v4-0-dedf9… Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (9): coresight: cpu-debug: Fix PM usage counter leak in debug_enable_func() coresight: etm4x: Remove perf symlink if config registration fails coresight: etm4x: Fix truncation of nr_ext_inp coresight: etm-perf: Fix sink device reference leak in etm_setup_aux() coresight: syscfg: Take csdev lock when removing owned features coresight: syscfg: Fix deadlock in cscfg_create_device() error path coresight: Fix resource leaks on coresight_build_path() errors coresight: etm3x: Don't ignore etm_parse_event_config() errors coresight: etm3x: Prohibit modifying seq_curr_state while session is enabled drivers/hwtracing/coresight/coresight-core.c | 6 ++++-- drivers/hwtracing/coresight/coresight-cpu-debug.c | 4 ++-- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 6 +++++- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 5 +++++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-syscfg.c | 8 +++++++- 8 files changed, 29 insertions(+), 7 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261027-james-cs-sashiko-easy-fixes-1-692d80016a89 prerequisite-message-id: <20261016-james-cs-multiple-per-threads-v4-0-dedf961aca0e(a)linaro.org> prerequisite-patch-id: 81acda380ba25acd3845eb58d5ded812175b9631 prerequisite-patch-id: 430caddc9c87948d4e9a0d1967bf3d8a50bca06b prerequisite-patch-id: 633377150141300f7578b265fcc02eba52e592a8 prerequisite-patch-id: 9a82ffe5d705ac1fdf1250ff6bf242cfcd9d8fbf prerequisite-patch-id: cf211801575d6bd0aa7fc0f6e19c3b90cea446a0 prerequisite-patch-id: d22fee48bf4aa3e01536e4683ccd797b3dbe1c91 prerequisite-patch-id: 55eeffb37cae55a1f47c2827899e0512b47a6efa prerequisite-patch-id: c542d74cd4bc76158d5872bab12b8bd7a00f0c27 prerequisite-patch-id: 71cd37ed83d3e01d7a0321cdfa5cfc5ee113fe7b prerequisite-patch-id: 74c1e3ed6dba4e25bfd3c39f06d43b079eed45e1 Best regards, -- James Clark <james.clark(a)linaro.org>

4 days, 22 hours

Re: [PATCH][next] perf cs-etm: Fix spelling mistake "should't" -> "shouldn't"

by James Clark

On 02/11/2026 18:01, Ian Rogers wrote: > On Mon, Nov 2, 2026 at 2:52 AM James Clark <james.clark(a)linaro.org> wrote: >> >> >> >> On 28/10/2026 18:31, Colin Ian King wrote: >>> There is a spelling mistake in a pr_err error message. Fix it. >>> >>> Signed-off-by: Colin Ian King <colin.i.king(a)gmail.com> >>> --- >>> tools/perf/util/cs-etm.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c >>> index bdcf94813129..65bce2450549 100644 >>> --- a/tools/perf/util/cs-etm.c >>> +++ b/tools/perf/util/cs-etm.c >>> @@ -434,7 +434,7 @@ static int cs_etm__map_unformatted_trace_ids(struct cs_etm_auxtrace *etm) >>> continue; >>> >>> if (!intlist__empty(etmq->traceid_list)) { >>> - pr_err("CS_ETM: Unformatted queue should't have trace ID\n"); >>> + pr_err("CS_ETM: Unformatted queue shouldn't have trace ID\n"); >>> return -EINVAL; >>> } >>> >> >> Reviewed-by: James Clark <james.clark(a)linaro.org> >> > > I was curious how this passed Sashiko's review. Did Sashiko flag the > spelling mistake but the fix was missed, or did Sashiko not flag it at > all? > > Thanks! > Ian It reviewed it, but it didn't flag it. What kind of typos is it supposed to look for? I haven't seen it flag one before. I have a spellchecker in my IDE which didn't catch it either because should is correct and t is only 1 letter. Maybe there is a setting I can tweak.

6 days, 3 hours

[PATCH] coresight: etm3x: Remove redundant NULL check on perf event attr

by James Clark

attr is derived from &event->attr, so it can never be NULL even if event were NULL, making the check dead code. The only caller, etm_enable_perf(), always passes a valid event anyway, so remove the check. Reported-by: Sashiko <sashiko-bot(a)kernel.org> Closes: https://sashiko.dev/#/bug/linux-c4ca0d3c-1e98-4965-aa46-da226c756b83 Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index b670a324bb41..755141691f69 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -313,9 +313,6 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event_attr *attr = &event->attr; u8 ts_level; - if (!attr) - return -EINVAL; - /* Clear configuration from previous run */ memset(curr_config, 0, sizeof(struct etm_config)); --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261027-james-cs-redundant-null-check-b1489a0ba03c Best regards, -- James Clark <james.clark(a)linaro.org>

6 days, 19 hours

Re: [PATCH v6] coresight: coresight.h: add '*' to kernel-doc lines

by Suzuki K Poulose

On Mon, 02 Nov 2026 09:57:51 -0800, Randy Dunlap wrote: > kernel-doc reports 2 (kernel-doc) lines in coresight.h that don't have > a beginning '*' in them, so fix these lines. > > Also convert struct coresight_trace_id_map to kernel-doc format to > remove another warning. > > Warning: include/linux/coresight.h:173 bad line: > connected to @src_port. NULL until the device is created > Warning: include/linux/coresight.h:177 bad line: > needs to be filtered. > Warning: include/linux/coresight.h:236 This comment starts with '/**', > but isn't a kernel-doc comment. > > [...] Applied, thanks! [1/1] coresight: coresight.h: add '*' to kernel-doc lines https://git.kernel.org/coresight/c/02ab6256e4f5 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

6 days, 19 hours

Re: [PATCH][next] perf cs-etm: Fix spelling mistake "should't" -> "shouldn't"

by James Clark

On 28/10/2026 18:31, Colin Ian King wrote: > There is a spelling mistake in a pr_err error message. Fix it. > > Signed-off-by: Colin Ian King <colin.i.king(a)gmail.com> > --- > tools/perf/util/cs-etm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index bdcf94813129..65bce2450549 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -434,7 +434,7 @@ static int cs_etm__map_unformatted_trace_ids(struct cs_etm_auxtrace *etm) > continue; > > if (!intlist__empty(etmq->traceid_list)) { > - pr_err("CS_ETM: Unformatted queue should't have trace ID\n"); > + pr_err("CS_ETM: Unformatted queue shouldn't have trace ID\n"); > return -EINVAL; > } > Reviewed-by: James Clark <james.clark(a)linaro.org>

1 week

[PATCH v3 00/14] perf cs-etm: Fix bogus branch samples on exceptions

by Leo Yan

CoreSight currently models exception entry by changing the preceding instruction range into a taken branch. This can give an IRQ the source PC of an instruction that already retired and overwrite a real branch immediately before the exception. For an untaken B.LS followed by an IRQ, perf script currently reports: hw int 4000f8 => ffff800080010c80 b.ls #0x400118 ... iret ffff800080012284 => 4000fc eret The hardware trace supplies 0x4000fc as the preferred return address. For an IRQ, this is the architectural resume PC (Arm ARM, R_VBQMV). B.LS has retired, and the saved PC identifies the boundary before the following MOV. Using this PC as the IRQ source reflects the architectural state at exception entry: hw int 4000fc => ffff800080010c80 movz x2, #0x1796 ... iret ffff800080012284 => 4000fc eret The IRQ sample represents the transfer from this architectural execution position to the handler. The series synthesizes exception entries from exception packets, preserving the preceding branch and its outcome. The supporting changes: - Let decoders supply sample.ret_addr so later instruction fetching cannot change thread-stack return addresses. Apply this to Intel PT asynchronous samples as well. - Prepare packet ISA and instruction-size handling and share sample synthesis helpers. Mark untaken branches and break history when instruction memory is unavailable. - Add a thread-stack regression test and four AArch64 CoreSight tests. IRQs and page faults must resume at the entry PC; SVC and emulated MRS must resume four bytes later. Based on the AI search and test on my x86 machine, this matches perf's Intel PT handling of IRQs. Intel PT records the next instruction's IP in the FUP packet, and Perf uses that IP as the interrupt sample's source. This series is verified on Orion6 board with "perf test coresight". Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v3: - Introduced the pref_ret_addr/end_addr union (James). - Clarified zero-size A32/A64 exception handling and why T32 retains per-address instruction decoding (James). - Retreed missing exception pairs for up to three recordings, then fail instead of skipping (James). - Shorten the IRQ workload (James). - Fix FIFO argument quoting and remove redundant ShellCheck source directives (James). - Checked instruction length before copying bytes into sample->insn (Sashiko). - Retried MRS checks when instruction page faults may match the opcode filter (Sashiko). - Rebased onto the updated perf tree and collect review tags. - Link to v2: https://lore.kernel.org/r/20260923-perf_cs_etm_fix_non_taken-v2-0-6ab8c07a5… Changes in v2: - Rework the fix around exception packets to preserve both exception entries and preceding branches. - Add explicit return addresses and the Intel PT asynchronous-branch fix. - Split out packet/synthesis preparation, record not-taken branches and handle unreadable instruction memory. - Add thread-stack regression coverage and four CoreSight tests. - Link to v1: https://lore.kernel.org/r/20260713-perf_cs_etm_fix_non_taken-v1-0-4561607fc… --- Leo Yan (14): perf sample: Allow decoders to supply branch return addresses perf intel-pt: Preserve return addresses for asynchronous branches perf cs-etm: Break branch history when instruction memory is unavailable perf cs-etm: Centralize packet ISA initialization perf cs-etm: Use the recorded instruction size for A32 and A64 perf cs-etm: Mark branches that were not taken perf cs-etm: Factor out final instruction sample synthesis perf cs-etm: Centralize branch sample synthesis checks perf cs-etm: Classify exception calls using the exception packet perf cs-etm: Synthesize exception entries separately from branches perf tests: Check CoreSight IRQ entry and exit perf tests: Check CoreSight syscall entry and exit perf tests: Check CoreSight abort entry and exit perf tests: Check CoreSight emulated instruction entry and exit tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 3 + .../perf/tests/shell/coresight/abort_entry_exit.sh | 32 +++ tools/perf/tests/shell/coresight/irq_entry_exit.sh | 36 +++ .../tests/shell/coresight/syscall_entry_exit.sh | 32 +++ .../perf/tests/shell/coresight/trap_entry_exit.sh | 39 ++++ tools/perf/tests/shell/lib/coresight_exception.sh | 164 ++++++++++++++ tools/perf/tests/tests.h | 3 + tools/perf/tests/thread-stack.c | 106 +++++++++ tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/branch_not_taken_loop.c | 33 +++ tools/perf/tests/workloads/page_fault_loop.c | 37 ++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 106 ++++++--- tools/perf/util/cs-etm.c | 246 +++++++++++---------- tools/perf/util/cs-etm.h | 6 +- tools/perf/util/intel-pt.c | 7 + tools/perf/util/sample.c | 1 + tools/perf/util/sample.h | 5 + tools/perf/util/thread-stack.c | 5 +- 19 files changed, 714 insertions(+), 152 deletions(-) --- base-commit: 4626d370ae89b8af4d46a45372b269f926ec662d change-id: 20260713-perf_cs_etm_fix_non_taken-5b4d7f73f41e Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 week

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CoreSight November 2026