CoreSight September 2026

coresight@lists.linaro.org

6 participants
37 discussions

Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

by Leo Yan

Hi Will, On Mon, Aug 10, 2026 at 04:10:48PM +0100, Will Deacon wrote: > On Mon, Aug 10, 2026 at 03:44:42PM +0100, Leo Yan wrote: > > Commit 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by > > default") made the AUX allocator use order-0 pages by default unless a > > PMU explicitly asks for contiguous allocations. > > But that commit specifically calls out SPE as benefitting from > non-contiguous pages: > > "For instance, ARM SPE and TRBE operate with virtual pages, and > Coresight ETR allocates a separate buffer. For these PMUs, > allocating contiguous AUX pages unnecessarily exacerbates memory > fragmentation. This fragmentation can prevent their use on > long-running devices." > > so why doesn't passing PERF_PMU_CAP_AUX_PREFER_LARGE reintroduce the > problems that 18049c8cff9c was trying to solve? How about adding a field to struct pmu to specify a preferred maximum page order for the AUX buffer? The perf core could try that order first and fall back to smaller orders if the allocation fails. For example, the Neoverse V2 TRM documents: L1 Trace Buffer Extension (TRBE) TLB: 1 entry Given the single L1 TRBE TLB entry, the TRBE driver could prefer PMD_ORDER (2 MiB with 4 KiB pages) to reduce TLB pressure. This reflects the hardware characteristic. This could be a trade-off instead of using PERF_PMU_CAP_AUX_PREFER_LARGE, avoiding large contiguous allocations that could reintroduce the Android OOM issue. I did a quick test with this approach and the results look positive. Does this sound like a reasonable direction? I might also need Yabin's judgement from Android side. Thanks, Leo

11 hours, 42 minutes

[PATCH v2] coresight: trbe: Hide enable_sink sysfs file

by James Clark

TRBE doesn't support sysfs mode, but the enable_sink file can still be successfully written to enable the device, and only attempting to enable the source would later fail. Avoid misleading users by adding a flag that devices can use to hide either the enable_sink or enable_source files, and set it for TRBE. Don't set it for ETE as it's possible that ETE could appear on the legacy bus and work with sysfs, and writing to enable_source already reports EINVAL if the device doesn't support sysfs mode. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Re-use CORESIGHT_DESC flags in csdev instead of converting to bool. - Hide all remaining attrs after label instead of only source and sink attrs as there aren't any others anyway (Leo). - Link to v1: https://lore.kernel.org/r/20260507-james-cs-hide-trbe-enable-v1-1-b4e40439f… --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 15 +++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 7 +++++++ include/linux/coresight.h | 4 ++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f7b1308a759c..a0c098980096 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1543,6 +1543,7 @@ coresight_init_device(struct coresight_desc *desc) csdev->ops = desc->ops; csdev->access = desc->access; csdev->orphan = true; + csdev->flags = desc->flags; if (desc->flags & CORESIGHT_DESC_CPU_BOUND) { csdev->cpu = desc->cpu; diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 4b010f8bc4c0..75000fe64fda 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -346,16 +346,19 @@ static ssize_t label_show(struct device *dev, } static DEVICE_ATTR_RO(label); -static umode_t label_is_visible(struct kobject *kobj, - struct attribute *attr, int n) +static umode_t coresight_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) { struct device *dev = kobj_to_dev(kobj); + struct coresight_device *csdev = to_coresight_device(dev); if (attr == &dev_attr_label.attr) { if (fwnode_property_present(dev_fwnode(dev), "label")) return attr->mode; else return 0; + } else if (csdev->flags & CORESIGHT_DESC_NO_SYSFS_MODE) { + return 0; } return attr->mode; @@ -369,7 +372,7 @@ static struct attribute *coresight_sink_attrs[] = { static struct attribute_group coresight_sink_group = { .attrs = coresight_sink_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_sink); @@ -381,7 +384,7 @@ static struct attribute *coresight_source_attrs[] = { static struct attribute_group coresight_source_group = { .attrs = coresight_source_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_source); @@ -392,7 +395,7 @@ static struct attribute *coresight_link_attrs[] = { static struct attribute_group coresight_link_group = { .attrs = coresight_link_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_link); @@ -403,7 +406,7 @@ static struct attribute *coresight_helper_attrs[] = { static struct attribute_group coresight_helper_group = { .attrs = coresight_helper_attrs, - .is_visible = label_is_visible, + .is_visible = coresight_attr_is_visible, }; __ATTRIBUTE_GROUPS(coresight_helper); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index c7cbca45f2de..eca8e13a9744 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1348,6 +1348,13 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp desc.dev = dev; desc.cpu = cpu; desc.flags = CORESIGHT_DESC_CPU_BOUND; + /* + * ETE isn't connected to TRBE with a link like other Coresight devices + * and the TRBE driver has been written to always assume Perf mode, so + * Prevent sysfs from being used. + */ + desc.flags |= CORESIGHT_DESC_NO_SYSFS_MODE; + trbe_csdev = coresight_register(&desc); if (IS_ERR(trbe_csdev)) goto cpu_clear; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index add0579cad88..6cd1d01b843b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -142,6 +142,8 @@ struct csdev_access { }) #define CORESIGHT_DESC_CPU_BOUND BIT(0) +/* Device can't be activated from sysfs, only via Perf. */ +#define CORESIGHT_DESC_NO_SYSFS_MODE BIT(1) /** * struct coresight_desc - description of a component required from drivers @@ -310,6 +312,8 @@ struct coresight_device { struct list_head config_csdev_list; raw_spinlock_t cscfg_csdev_lock; void *active_cscfg_ctxt; + /* CORESIGHT_DESC_[x] flags */ + u32 flags; }; /* --- base-commit: c8eb4a8dd259fb2b215da32764fa8c6c76519896 change-id: 20260506-james-cs-hide-trbe-enable-3c8d784e72d8 Best regards, -- James Clark <james.clark(a)linaro.org>

15 hours, 2 minutes

[PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions

by Leo Yan

CoreSight currently models exception entry by changing the preceding instruction range into a taken branch. This can give an IRQ the source PC of an instruction that already retired and overwrite a real branch immediately before the exception. For an untaken B.LS followed by an IRQ, perf script currently reports: hw int 4000f8 => ffff800080010c80 b.ls #0x400118 ... iret ffff800080012284 => 4000fc eret The hardware trace supplies 0x4000fc as the preferred return address. For an IRQ, this is the architectural resume PC (Arm ARM, R_VBQMV). B.LS has retired, and the saved PC identifies the boundary before the following MOV. Using this PC as the IRQ source reflects the architectural state at exception entry: hw int 4000fc => ffff800080010c80 movz x2, #0x1796 ... iret ffff800080012284 => 4000fc eret The IRQ sample represents the transfer from this architectural execution position to the handler. The series synthesizes exception entries from exception packets, preserving the preceding branch and its outcome. The supporting changes: - Let decoders supply sample.ret_addr so later instruction fetching cannot change thread-stack return addresses. Apply this to Intel PT asynchronous samples as well. - Prepare packet ISA and instruction-size handling and share sample synthesis helpers. Mark untaken branches and break history when instruction memory is unavailable. - Add a thread-stack regression test and four AArch64 CoreSight tests. IRQs and page faults must resume at the entry PC; SVC and emulated MRS must resume four bytes later. Based on the AI search and test on my x86 machine, this matches perf's Intel PT handling of IRQs. Intel PT records the next instruction's IP in the FUP packet, and Perf uses that IP as the interrupt sample's source. This series is verified on Orion6 board with "perf test coresight". Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Rework the fix around exception packets to preserve both exception entries and preceding branches. - Add explicit return addresses and the Intel PT asynchronous-branch fix. - Split out packet/synthesis preparation, record not-taken branches and handle unreadable instruction memory. - Add thread-stack regression coverage and four CoreSight tests. - Link to v1: https://lore.kernel.org/r/20260713-perf_cs_etm_fix_non_taken-v1-0-4561607fc… --- Leo Yan (14): perf sample: Allow decoders to supply branch return addresses perf intel-pt: Preserve return addresses for asynchronous branches perf cs-etm: Break branch history when instruction memory is unavailable perf cs-etm: Centralize packet ISA initialization perf cs-etm: Use the recorded instruction size for A32 and A64 perf cs-etm: Mark branches that were not taken perf cs-etm: Factor out final instruction sample synthesis perf cs-etm: Centralize branch sample synthesis checks perf cs-etm: Classify exception calls using the exception packet perf cs-etm: Synthesize exception entries separately from branches perf tests: Check CoreSight IRQ entry and exit perf tests: Check CoreSight syscall entry and exit perf tests: Check CoreSight abort entry and exit perf tests: Check CoreSight emulated instruction entry and exit tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 3 + .../perf/tests/shell/coresight/abort_entry_exit.sh | 21 ++ tools/perf/tests/shell/coresight/irq_entry_exit.sh | 37 ++++ .../tests/shell/coresight/syscall_entry_exit.sh | 21 ++ .../perf/tests/shell/coresight/trap_entry_exit.sh | 24 +++ tools/perf/tests/shell/lib/coresight_exception.sh | 165 +++++++++++++++ tools/perf/tests/tests.h | 3 + tools/perf/tests/thread-stack.c | 106 ++++++++++ tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/branch_not_taken_loop.c | 33 +++ tools/perf/tests/workloads/page_fault_loop.c | 37 ++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 106 +++++++--- tools/perf/util/cs-etm.c | 222 ++++++++++----------- tools/perf/util/cs-etm.h | 2 + tools/perf/util/intel-pt.c | 7 + tools/perf/util/sample.c | 1 + tools/perf/util/sample.h | 5 + tools/perf/util/thread-stack.c | 5 +- 19 files changed, 656 insertions(+), 147 deletions(-) --- base-commit: edd8a9fe2eca009599e013a29c421c7a6b5ad1b9 change-id: 20260713-perf_cs_etm_fix_non_taken-5b4d7f73f41e Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 day, 13 hours

Re: [PATCH] coresight: syscfg: Fix null pointer dereference when configfs init fails

by Mike Leach

Reviewed-by: Mike Leach <mike.leach(a)arm.com> On 9/28/26 13:35, Yingchao Deng wrote: > If cscfg_configfs_init() fails, cscfg_init() takes the exit_err path: > > cscfg_init() -> cscfg_clear_device() -> cscfg_configfs_release() > -> configfs_unregister_subsystem() > > which tears down a configfs subsystem that was never registered. > configfs_unregister_subsystem() begins with: > > struct dentry *dentry = dget(group->cg_item.ci_dentry); > struct dentry *root = dentry->d_sb->s_root; > > ci_dentry is assigned in configfs_create_dir() only once the subsystem > directory has been created, which never happened here. cscfg_mgr > comes from kzalloc_obj(), so ci_dentry is still NULL, and dget() > hands a NULL dentry back unchanged - the next line dereferences it. > > Handle the failure in cscfg_init() directly: unregister the device and > return the error, releasing the devres-allocated config item type and > cscfg_mgr without touching the subsystem. > > Fixes: a13d5a246aca ("coresight: syscfg: Add initial configfs support") > Suggested-by: Leo Yan <leo.yan(a)arm.com> > Link: https://lore.kernel.org/all/20260924162404.GN200420@e132581.arm.com/ > Signed-off-by: Yingchao Deng <dengyingchao(a)kylinsec.com.cn> > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 2bfdd7b45e49..00b29d1656c0 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -1299,8 +1299,10 @@ int __init cscfg_init(void) > > /* initialise configfs subsystem */ > err = cscfg_configfs_init(cscfg_mgr); > - if (err) > - goto exit_err; > + if (err) { > + device_unregister(cscfg_device()); > + return err; > + } > > /* preload built-in configurations */ > err = cscfg_preload(THIS_MODULE);

1 day, 16 hours

[PATCH v12 00/14] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - curr_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v11 to v12: - rename active_config to curr_config. - rename config to sysfs_config. - remove redundant config argument in etmX_args. - add read-back and copy from curr_config to sysfs_config TRCSEQSTR (seq_state). - add r-b and t-b tags. - Link to v11: https://lore.kernel.org/r/20260915-separate_etm_cfg_v2-v11-0-d2b258d51747@a… from v10 to v11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@a… from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (14): coresight: etm4x: read-back TRCSEQSTR at disabling and prohibit modifying seq_state while enabling. coresight: etm4x: prohibit modifying cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: rename local config as curr_config referring drvdata->curr_config coresight: etm4x: rename drvdata->config to sysfs_config coresight: etm3x: introduce struct etm_caps coresight: etm3x: rename local config as curr_config referring drvdata->curr_config coresight: etm3x: rename drvdata->config to sysfs_config drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 + drivers/hwtracing/coresight/coresight-etm.h | 48 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 196 +++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 461 +++++----- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 567 ++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 961 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 199 +++-- 9 files changed, 1340 insertions(+), 1146 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

1 day, 17 hours

[PATCH v2] perf test: Record kcore for the CoreSight callchain test

by Leo Yan

The CoreSight callchain test traces both userspace and kernel execution and checks the callchain across a syscall. Add --kcore to perf record to save the running kernel image alongside the trace data so perf script can use it to decode the kernel trace. If kcore is not available, the test will be skipped. Add a Fixes tag so the change can be backported to stable kernels and improve the test reliability. Fixes: ca0e19074bd6 ("perf test: Add Arm CoreSight callchain test") Reviewed-by: James Clark <james.clark(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Add check /proc/kcore and skip test if absent. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- tools/perf/tests/shell/coresight/callchain.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/coresight/callchain.sh b/tools/perf/tests/shell/coresight/callchain.sh index 13cca7dc11184002e3ddc058c0d0ffa1c458c483..43ad90bc30345efdd40ba4649ceeb435a1781a4b 100755 --- a/tools/perf/tests/shell/coresight/callchain.sh +++ b/tools/perf/tests/shell/coresight/callchain.sh @@ -30,6 +30,11 @@ skip_if_system_is_not_ready() return 2 } + [ -e /proc/kcore ] || { + echo "[Skip] /proc/kcore is not available" >&2 + return 2 + } + return 0 } @@ -43,7 +48,7 @@ record_trace() mkfifo "$cf" "$af" - perf record -o "$data" -e cs_etm// --per-thread -D -1 --control fifo:"$cf","$af" -- \ + perf record --kcore -o "$data" -e cs_etm// --per-thread -D -1 --control fifo:"$cf","$af" -- \ perf test --record-ctl fifo:"$cf","$af" -w callchain >/dev/null 2>&1 && # It is safe to use 'i3i' with a three-instruction interval, since the --- base-commit: 0ae6fc78c5ce0dfd18d8712a50f0fd4602eff103 change-id: 20260928-perf_cs_etm_callchain_test_add_kcore-f96e891f91c5 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 days, 11 hours

[PATCH 0/3] perf: Suppress redundant ITRACE start records for Arm SPE and CoreSight

by Leo Yan

Thanks to Tamas Petz for noticing that Arm CoreSight perf data can contain many PERF_RECORD_ITRACE_START records. PERF_RECORD_ITRACE_START provides the decoder with the initial thread context when that information is absent from the trace stream. Once tracing has started, Arm SPE and CoreSight decoders track subsequent context changes using context packets or recorded sched_switch events. Have both drivers call perf_event_itrace_started() after successfully starting event. This prevents perf core from emitting redundant PERF_RECORD_ITRACE_START records when an event is scheduled in again. Since the Arm SPE and CoreSight drivers can be built as modules, export perf_event_itrace_started() before using it in those drivers. This series was verified with Arm CoreSight using the commands below. The perf data contains 100 sched_switch events but only one PERF_RECORD_ITRACE_START record: taskset -c 2 perf record -e cs_etm//u -e sched:sched_switch -- \ taskset -c 2 bash -c 'while true; do sleep 0.01; done' ^C perf script -D 2>&1 | grep -c sched_switch 100 perf script -D 2>&1 | grep -c PERF_RECORD_ITRACE_START 1 Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (3): perf/core: Export perf_event_itrace_started() perf: arm_spe: Suppress redundant ITRACE start records coresight: perf: Suppress ITRACE start records drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/perf/arm_spe_pmu.c | 2 ++ kernel/events/core.c | 1 + 3 files changed, 5 insertions(+) --- base-commit: 786262be6048deab760f68c8acc2c85607165894 change-id: 20260901-perf_suppress_itrace_start_records-42faf45e9ce9 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 days, 18 hours

[PATCH] perf test: Record kcore for the CoreSight callchain test

by Leo Yan

The CoreSight callchain test traces both userspace and kernel execution and checks the callchain across a syscall. Add --kcore to perf record to save the running kernel image alongside the trace data so perf script can use it to decode the kernel trace. Add a Fixes tag so the change can be backported to stable kernels and improve the test reliability. Fixes: ca0e19074bd6 ("perf test: Add Arm CoreSight callchain test") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- tools/perf/tests/shell/coresight/callchain.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/coresight/callchain.sh b/tools/perf/tests/shell/coresight/callchain.sh index 13cca7dc1118..b69187f1a37f 100755 --- a/tools/perf/tests/shell/coresight/callchain.sh +++ b/tools/perf/tests/shell/coresight/callchain.sh @@ -43,7 +43,7 @@ record_trace() mkfifo "$cf" "$af" - perf record -o "$data" -e cs_etm// --per-thread -D -1 --control fifo:"$cf","$af" -- \ + perf record --kcore -o "$data" -e cs_etm// --per-thread -D -1 --control fifo:"$cf","$af" -- \ perf test --record-ctl fifo:"$cf","$af" -w callchain >/dev/null 2>&1 && # It is safe to use 'i3i' with a three-instruction interval, since the -- 2.34.1

2 days, 19 hours

Re: [PATCH] coresight: cti: Add const to con_groups allocation type

by Leo Yan

On Thu, Sep 17, 2026 at 02:14:29PM -0700, Kees Cook wrote: > From: Kees Cook <kees+treewide(a)kernel.org> > ... As there is no general way to > safely add const qualifiers, take the size from the assignment target > instead. No change in allocation size results. > > Build tested ARCH=arm64 allmodconfig with GCC aarch64-linux-gnu 16.1.0: > drivers/hwtracing/coresight/coresight-cti-sysfs.o > > Assisted-by: LLM coccinelle > Signed-off-by: Kees Cook <kees+treewide(a)kernel.org> Reviewed-by: Leo Yan <leo.yan(a)arm.com>

2 days, 19 hours

Re: [PATCH v2 1/1] coresight: syscfg: fix deadlock on device registration failure

by Leo Yan

On Fri, Sep 25, 2026 at 10:40:22AM +0800, yingchao deng wrote: [...] > > @Yingchao, do you mind to work out a formal patch for this? > Happy to. I'll send the patch. Thanks!

2 days, 19 hours

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