CoreSight

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2603 discussions

Re: [PATCH v9 7/7] qcom-tgu: Add reset node to initialize

by Suzuki K Poulose

On 19/12/2025 06:59, Songwei Chai wrote: > Add reset node to initialize the value of > priority/condition_decode/condition_select/timer/counter nodes. > > Signed-off-by: Songwei Chai <songwei.chai(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++ > drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++ > 2 files changed, 81 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > index 010eade0a1c5..0733b3e07b45 100644 > --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu > @@ -42,3 +42,10 @@ KernelVersion 6.19 > Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Songwei Chai <songwei.chai(a)oss.qualcomm.com> > Description: > (RW) Set/Get the counter value with specific step for TGU. > + > +What: /sys/bus/amba/devices/<tgu-name>/reset_tgu > +Date: December 2025 > +KernelVersion 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Songwei Chai <songwei.chai(a)oss.qualcomm.com> > +Description: > + (Write) Write 1 to reset the dataset for TGU. > diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c > index d4210869556e..5a8c6af9b719 100644 > --- a/drivers/hwtracing/qcom/tgu.c > +++ b/drivers/hwtracing/qcom/tgu.c > @@ -425,8 +425,82 @@ static ssize_t enable_tgu_store(struct device *dev, > + > + dev_dbg(dev, "Coresight-TGU reset complete\n"); Qualcomm-TGU ? Suzuki

1 day, 9 hours

[PATCH RESEND v5 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v5: - Add the missing review-by tag for patch 3. - Link to v4: https://lore.kernel.org/r/20250831-itnoc-v4-0-f0fb0ef822a5@oss.qualcomm.com Changes in v4: - Fix unintended blank line removals in trace_noc_enable_hw. - Link to v3: https://lore.kernel.org/r/20250828-itnoc-v3-0-f1b55dea7a27@oss.qualcomm.com Changes in v3: - Add detail for changes in V2. - Remove '#address-cells' and '#size-cells' properties from in-ports field. - Fix comment indentation for packet description. - Link to v2: https://lore.kernel.org/r/20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com Changes in v2: - Removed the trailing '|' after the description in qcom,coresight-itnoc.yaml. - Dropped the 'select' section from the YAML file. - Updated node name to use a more generic naming convention. - Removed the 'items' property from the compatible field. - Deleted the description for the reg property. - Dropped clock-names and adjusted the order of clock-names and clocks. - Moved additionalProperties to follow the $ref of out-ports. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 90 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 136 +++++++++++++++++++-- 2 files changed, 215 insertions(+), 11 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

1 day, 13 hours

Re: [PATCH v8 0/4] add sysfs nodes to configure TPDA's registers

by Suzuki K Poulose

On Tue, 23 Dec 2025 18:09:49 +0800, Jie Gan wrote: > Patchset 1 introduces configuration of the global control register with > appropriate values to enable proper generation of cross-trigger packets. > > Patchset 2 introduces a sysfs node for triggering global flush for all > ports. > > Patchset 3 introduces a logic to configure the TPDA_SYNCR register, > which determines the frequency of ASYNC packet generation. These packets > assist userspace tools in accurately identifying each valid packet. > > [...] Applied, thanks! [1/4] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration https://git.kernel.org/coresight/c/f9cc5b5a9e9a [2/4] coresight: tpda: add global_flush_req sysfs node https://git.kernel.org/coresight/c/8e1c358a3b0e [3/4] coresight: tpda: add logic to configure TPDA_SYNCR register https://git.kernel.org/coresight/c/33f04ead7c49 [4/4] coresight: tpda: add sysfs node to flush specific port https://git.kernel.org/coresight/c/a089d585a7f4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 days, 3 hours

[PATCH v8 00/13] coresight: Update timestamp attribute to be an interval instead of bool

by James Clark

Do some cleanups then expand the timestamp format attribute from 1 bit to 4 bits for ETMv4 in Perf mode. The current interval is too high for most use cases, and particularly on the FVP the number of timestamps generated is excessive. This change not only still allows disabling or enabling timestamps, but also allows the interval to be configured. The old bit is kept deprecated and undocumented for now. There are known broken versions of Perf that don't read the format attribute positions from sysfs and instead hard code the timestamp bit. We can leave the old bit in the driver until we need the bit for another feature or enough time has passed that these old Perfs are unlikely to be used. The interval option is added as an event format attribute, rather than a Coresight config because it's something that the driver is already configuring automatically in Perf mode using any unused counter, so it's not possible to modify this with a config. Applies to coresight/next Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v8: - Handle ts_level attribute outside etm4_config_timestamp_event() (Mike) - Flip commits 11 and 12 so that the new attribute works as soon as it's published to sysfs for bisecting (Suzuki) - Remove some spurious header includes - Link to v7: https://lore.kernel.org/r/20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@lina… Changes in v7: - Change TRCCNTCTLRn and TRCTSCTLR register definitions to use a combined field for TYPE and SEL (EVENT) so that they can be used with the new utilities. - Add utility functions for creating resource selectors that do compile and runtime checking of the resource selector ID. - Link to v6: https://lore.kernel.org/r/20251119-james-cs-syncfreq-v6-0-740d24a29e51@lina… Changes in v6: - #ifdef out format attributes for ETMv3 instead of using is_visible(). Then the same block can be used to define format_attr_contextid_show() which avoids an awkward WARN_ONCE() and comments in arm32 for a function that's never called. - Link to v5: https://lore.kernel.org/r/20251118-james-cs-syncfreq-v5-0-82efd7b1a751@lina… Changes in v5: - Add parens to interval calculation in docs (Randy) - Swap "minimum interval" and "maximum interval" in docs. (Leo) - Add TRCSYNCPR.PERIOD to docs (Leo) - Use CONFIG_ARM64 to avoid is_kernel_in_hyp_mode() (Leo) - Add a comment for hidden ETMv3 format attributes (Leo) - Hide configid for ETMv3 (Leo) - Link to v4: https://lore.kernel.org/r/20251112-james-cs-syncfreq-v4-0-165ba21401dc@lina… Changes in v4: - Add #defines for true and false resources ETM_RES_SEL_TRUE/FALSE - Reword comment about finding a counter to say if there are no resources there are no counters. - Extend existing timestamp format attribute instead of adding a new one - Refactor all the config definitions and parsing to use GEN_PMU_FORMAT_ATTR()/ATTR_CFG_GET_FLD() so we can see where the unused bits are. - Link to v3: https://lore.kernel.org/r/20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@lina… Changes in v3: - Move the format attr definitions to coresight-etm-perf.h we can compile on arm32 without #ifdefs - (Leo) - Convert the new #ifdefs to a single one in an is_visible() function so that the code is cleaner - (Leo) - Drop the change to remove the holes in struct etmv4_config as they were grouped by function - (Mike) - Link to v2: https://lore.kernel.org/r/20250814-james-cs-syncfreq-v2-0-c76fcb87696d@lina… Changes in v2: - Only show the attribute for ETMv4 to improve usability and fix the arm32 build error. Wrapping everything in IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) isn't ideal, but the -perf.c file is shared between ETMv3 and ETMv4, and there is already precedent for doing it this way. - Link to v1: https://lore.kernel.org/r/20250811-james-cs-syncfreq-v1-0-b001cd6e3404@lina… --- James Clark (13): coresight: Change syncfreq to be a u8 coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Hide unused ETMv3 format attributes coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() coresight: Don't reject unrecognized ETMv3 format attributes coresight: Interpret perf config with ATTR_CFG_GET_FLD() coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() coresight: Remove misleading definitions coresight: Prepare to allow setting the timestamp interval coresight: Extend width of timestamp format attribute coresight: docs: Document etm4x timestamp interval option Documentation/trace/coresight/coresight.rst | 16 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 68 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.h | 38 +++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 39 +++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 175 ++++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 92 ++++++++--- include/linux/coresight-pmu.h | 24 --- 7 files changed, 279 insertions(+), 173 deletions(-) --- base-commit: 9e9182cab5ebc3ee7544e60ef08ba19fdf216920 change-id: 20250724-james-cs-syncfreq-7c2257a38ed3 Best regards, -- James Clark <james.clark(a)linaro.org>

2 days, 3 hours

[PATCH] MAINTAINERS: Change of email address

by Mike Leach

My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..e3974f9f300a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2657,7 +2657,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20476,7 +20476,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.32.0

2 days, 8 hours

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1 week, 2 days

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1 week, 2 days

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1 week, 2 days

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1 week, 2 days

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