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This patchset builds upon Yicong's previous patches [1].
Patch 2 introducing fix race issues found by using TMC-ETR.
Patch 1 & 3 introducing two cleanups found when debugging the issues.
[1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@…
---
Changes in v4:
- a) Add comment at the context of set etr to sysfs mode.
- b) Move the check on drvdata->read to the start of enable etr.
- c) Add checks to prevent multiple sysfs processes from simultaneously
competing to enable ETR.
- d) Fix the issue with the guard used.
Link: https://lore.kernel.org/linux-arm-kernel/20250818080600.418425-1-hejunhao3@…
---
Changes in v3:
- Patches 1: Additional comment for tmc_drvdata::etr_mode. Update
comment for tmc_drvdata::reading with Jonathan's Tag.
- Patches 2: Replace scoped_guard with guard with Jonathan's Tag.
- Patches 2: Fix spinlock to raw_spinlock, and refactor this code based
on Leo's suggested solution.
- Patches 3: change the size's type to ssize_t and use max_t to simplify
the code with Leo's Tag.
Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@…
Changes in v2:
- Updated the commit of patch2.
- Rebase to v6.16-rc1
Junhao He (1):
coresight: tmc: refactor the tmc-etr mode setting to avoid race
conditions
Yicong Yang (2):
coresight: tmc: Add missing doc including reading and etr_mode of
struct tmc_drvdata
coresight: tmc: Decouple the perf buffer allocation from sysfs mode
.../hwtracing/coresight/coresight-tmc-etr.c | 136 +++++++++---------
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 66 insertions(+), 72 deletions(-)
--
2.33.0
The specific config field that an event format attribute is in is
consistently hard coded, even though the API is supposed to be that the
driver publishes the config field name. To stop this pattern from being
copy pasted and causing problems in the future, replace them all with
calls to a new helper that returns the value that a user set.
This reveals some issues in evsel__set_config_if_unset(). It doesn't
work with sparse bitfields, which are an unused but documented feature.
And it also only writes to the attr.config field. To fix it we need to
start tracking user changes for all config fields and then use existing
helper functions that support sparse bitfields. Some other refactoring
was also required and a test was added.
---
Changes in v4:
- Constify some function args (Ian)
- Move some evsel__* functions to evsel.c and make some pmu.c functions
public to support this (Ian)
- Drop pmu arg where it can be fetched from evsel->pmu (Ian)
- Link to v3: https://lore.kernel.org/r/20251212-james-perf-config-bits-v3-0-aa36a4846776…
Changes in v3:
- Fix uninitialized variable warning on GCC
- Fix leak of evlist in test
- Confirm no type punning issues with ubsan (Ian)
- Link to v2: https://lore.kernel.org/r/20251208-james-perf-config-bits-v2-0-4ac0281993b0…
Changes in v2:
- Remove macros in get_config_chgs() and some other refactoring.
- Support sparse bitfields in evsel__set_config_if_unset().
- Always track user changes instead of only when
'pmu->perf_event_attr_init_default' is set.
- Add a test.
- Don't bail out in cs-etm.c if any format fields are missing (Leo).
- Rename 'guess' to 'synth' (Mike).
- Link to v1: https://lore.kernel.org/r/20251201-james-perf-config-bits-v1-0-22ecbbf8007c…
---
James Clark (14):
perf parse-events: Refactor get_config_terms() to remove macros
perf evsel: Refactor evsel__set_config_if_unset() arguments
perf evsel: Move evsel__* functions to evsel.c
perf evsel: Support sparse fields in evsel__set_config_if_unset()
perf parse-events: Track all user changed config bits
perf evsel: apply evsel__set_config_if_unset() to all config fields
perf evsel: Add a helper to get the value of a config field
perf parse-events: Always track user config changes
perf tests: Test evsel__set_config_if_unset() and config change tracking
perf cs-etm: Make a helper to find the Coresight evsel
perf cs-etm: Don't use hard coded config bits when setting up ETMCR
perf cs-etm: Don't use hard coded config bits when setting up TRCCONFIGR
perf cs-etm: Don't hard code config attribute when configuring the event
perf arm-spe: Don't hard code config attribute
tools/perf/arch/arm/util/cs-etm.c | 201 +++++++++++++++-------------
tools/perf/arch/arm64/util/arm-spe.c | 17 +--
tools/perf/arch/x86/util/intel-pt.c | 3 +-
tools/perf/tests/pmu.c | 91 +++++++++++++
tools/perf/util/evsel.c | 112 +++++++++++++++-
tools/perf/util/evsel.h | 6 +-
tools/perf/util/evsel_config.h | 7 +-
tools/perf/util/parse-events.c | 248 ++++++++++++++++++++---------------
tools/perf/util/pmu.c | 95 ++++----------
tools/perf/util/pmu.h | 34 ++++-
10 files changed, 529 insertions(+), 285 deletions(-)
---
base-commit: cbd41c6d4c26c161a2b0e70ad411d3885ff13507
change-id: 20251112-james-perf-config-bits-bee7106f0f00
Best regards,
--
James Clark <james.clark(a)linaro.org>
On Mon, 03 Nov 2025 15:06:20 +0800, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
>
> Changes in V4:
> 1. dtsi file has been renamed from qcs8300.dtsi -> monaco.dtsi
> Link to V3 - https://lore.kernel.org/all/20251013-enable-ctcu-for-qcs8300-v3-0-611e6e0d3…
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: add CTCU device for monaco
https://git.kernel.org/coresight/c/51cd1fb70e08
Best regards,
--
Suzuki K Poulose <suzuki.poulose(a)arm.com>
Hi,
On Fri, Dec 19, 2025 at 10:39:49AM +0800, Ma Ke wrote:
[...]
> From the discussion, I note two possible fix directions:
>
> 1. Release the initial reference in etm_setup_aux() (current v2 patch)
> 2. Modify the behavior of coresight_get_sink_by_id() itself so it
> doesn't increase the reference count.
The option 2 is the right way to go.
> To ensure the correctness of the v3 patch, I'd like to confirm which
> patch is preferred. If option 2 is the consensus, I'm happy to modify
> the implementation of coresight_get_sink_by_id() as suggested.
It is good to use a separate patch to fix
coresight_find_device_by_fwnode() mentioned by James:
diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index 0db64c5f4995..2b34f818ba88 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -107,14 +107,16 @@ coresight_find_device_by_fwnode(struct fwnode_handle *fwnode)
* platform bus.
*/
dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
- if (dev)
- return dev;
/*
* We have a configurable component - circle through the AMBA bus
* looking for the device that matches the endpoint node.
*/
- return bus_find_device_by_fwnode(&amba_bustype, fwnode);
+ if (!dev)
+ dev = bus_find_device_by_fwnode(&amba_bustype, fwnode);
+
+ put_device(dev);
+ return dev;
}
/*
@@ -274,7 +276,6 @@ static int of_coresight_parse_endpoint(struct device *dev,
of_node_put(rparent);
of_node_put(rep);
- put_device(rdev);
return ret;
}
Thanks for working on this.
On 19/12/2025 09:08, Jie Gan wrote:
>
>
> On 11/3/2025 3:06 PM, Jie Gan wrote:
>> The CTCU device for monaco shares the same configurations as SA8775p. Add
>> a fallback to enable the CTCU for monaco to utilize the compitable of the
>> SA8775p.
>>
>
> Gentle reminder.
I was under the assumption that this was going via msm tree ? Sorry, I
misunderstood. I can pull this in for v6.20
Suzuki
>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
>> Reviewed-by: Bjorn Andersson <andersson(a)kernel.org>
>> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +
>> ++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml
>> index c969c16c21ef..460f38ddbd73 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> @@ -26,8 +26,13 @@ description: |
>> properties:
>> compatible:
>> - enum:
>> - - qcom,sa8775p-ctcu
>> + oneOf:
>> + - items:
>> + - enum:
>> + - qcom,qcs8300-ctcu
>> + - const: qcom,sa8775p-ctcu
>> + - enum:
>> + - qcom,sa8775p-ctcu
>> reg:
>> maxItems: 1
>>
>