The current ETMx configuration via sysfs can lead to the following inconsistencies:
- If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in.
- If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4).
- There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4).
To resolve these inconsistencies, the configuration should be separated into:
- active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs.
and apply configuration from configfs after taking a mode.
Patch History ============= from v10 to 11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@ar...
from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/
from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/
from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/
from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/
from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/
from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/
from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/
from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/
from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/
--- Yeoreum Yun (9): coresight: etm4x: prohibit modifying ss_status and cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm3x: introduce struct etm_caps
drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 ++ drivers/hwtracing/coresight/coresight-etm.h | 46 ++- drivers/hwtracing/coresight/coresight-etm3x-core.c | 126 +++--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 104 +++-- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 426 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 210 ++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 196 +++++----- 9 files changed, 676 insertions(+), 486 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff
Best regards,
ss_status and cntr_val are overwritten with the values read from the corresponding registers by etm4_disable_hw() when the session is disabled.
This means that any changes to these values made while the session is enabled would be lost when the session is disabled.
Therefore, prohibit modifying ss_status and cntr_val while the session is enabled.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc6cdd3ae29d5..8d73248b840a6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,6 +1613,8 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL; + if (coresight_get_mode(drvdata->csdev)) + return -EBUSY;
raw_spin_lock(&drvdata->spinlock); idx = config->cntr_idx; @@ -1797,6 +1799,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
if (kstrtoul(buf, 16, &val)) return -EINVAL; + if (coresight_get_mode(drvdata->csdev)) + return -EBUSY;
raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; @@ -1847,6 +1851,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
if (kstrtoul(buf, 16, &val)) return -EINVAL; + if (coresight_get_mode(drvdata->csdev)) + return -EBUSY;
raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx;
Hi,
Preventing a write to the counter value register is correct, but protecting the ss_status is redundant.
On 9/15/26 12:34, Yeoreum Yun wrote:
ss_status and cntr_val are overwritten with the values read from the corresponding registers by etm4_disable_hw() when the session is disabled.
This means that any changes to these values made while the session is enabled would be lost when the session is disabled.
Therefore, prohibit modifying ss_status and cntr_val while the session is enabled.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc6cdd3ae29d5..8d73248b840a6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,6 +1613,8 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;raw_spin_lock(&drvdata->spinlock); idx = config->cntr_idx; @@ -1797,6 +1799,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;
This is protecting a write clearing the STATUS bit in TRCSSCSR - but this is cleared automatically when next time the hardware is enabled in etm4_enable_hw(). So the write to ss_status in this function is redundant as is this protection.
The actual write to the targeted control register will persist.
raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; @@ -1847,6 +1851,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx;
as above
Regards
Mike
Hi Mike,
Hi,
Preventing a write to the counter value register is correct, but protecting the ss_status is redundant.
On 9/15/26 12:34, Yeoreum Yun wrote:
ss_status and cntr_val are overwritten with the values read from the corresponding registers by etm4_disable_hw() when the session is disabled.
This means that any changes to these values made while the session is enabled would be lost when the session is disabled.
Therefore, prohibit modifying ss_status and cntr_val while the session is enabled.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc6cdd3ae29d5..8d73248b840a6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,6 +1613,8 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;@@ -1797,6 +1799,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;This is protecting a write clearing the STATUS bit in TRCSSCSR - but this is cleared automatically when next time the hardware is enabled in etm4_enable_hw(). So the write to ss_status in this function is redundant as is this protection.
The actual write to the targeted control register will persist.
Acked, I'll remove this protection in here.
Thanks!
[...]
cntr_val are overwritten with the values read from the corresponding registers by etm_disable_hw() when the session is disabled.
This means that any changes to this value made while the session is enabled would be lost when the session is disabled.
Also, reset shouldn't be called while session is enabled.
Therefore, prohibit modifying cntr_val and reset while the session is enabled.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index b3c67e96a82a4..d4846d6364945 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -74,6 +74,8 @@ static ssize_t reset_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret; + if (coresight_get_mode(drvdata->csdev)) + return -EBUSY;
if (val) { spin_lock(&drvdata->spinlock); @@ -744,6 +746,8 @@ static ssize_t cntr_val_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret; + if (coresight_get_mode(drvdata->csdev)) + return -EBUSY;
spin_lock(&drvdata->spinlock); config->cntr_val[config->cntr_idx] = val;
Reviewed-by: Mike Leach mike.leach@arm.com
On 9/15/26 12:34, Yeoreum Yun wrote:
cntr_val are overwritten with the values read from the corresponding registers by etm_disable_hw() when the session is disabled.
This means that any changes to this value made while the session is enabled would be lost when the session is disabled.
Also, reset shouldn't be called while session is enabled.
Therefore, prohibit modifying cntr_val and reset while the session is enabled.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index b3c67e96a82a4..d4846d6364945 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -74,6 +74,8 @@ static ssize_t reset_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;if (val) { spin_lock(&drvdata->spinlock); @@ -744,6 +746,8 @@ static ssize_t cntr_val_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (coresight_get_mode(drvdata->csdev))
return -EBUSY;spin_lock(&drvdata->spinlock); config->cntr_val[config->cntr_idx] = val;
The current ETM4x configuration via sysfs can lead to several inconsistencies:
- If the configuration is modified via sysfs while a perf session is active, the running configuration may differ before a sched-out and after a subsequent sched-in.
- If a perf session and a sysfs session enable tracing concurrently, the configuration from configfs may become corrupted.
- There is a risk of corrupting drvdata->config if a perf session enables tracing while cscfg_csdev_disable_active_config() is being handled in etm4_disable_sysfs().
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session - config: the configuration set via sysfs
Additionally:
- Apply the configuration from configfs after taking the appropriate mode.
- Since active_config and related fields are accessed only by the local CPU in etm4_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and startup/dying_cpu except when to access config fields.
As the active_config is used for cfg-configfs, etmv4 doesn't need to set its lock for the cfg-configfs since the active_config is proceted by cs_mode otherwise it would make a possible cpu-stall when it get interrupt while setting the sysfs configuration.
Therefore, set the drv_spinlock for cfg-configfs as NULL and let the cfg-configfs disable irq without grap drv_spinlock when it is NULL.
Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-config.c | 18 ++-- drivers/hwtracing/coresight/coresight-config.h | 22 ++++ drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 13 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 118 ++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- 6 files changed, 113 insertions(+), 68 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.c b/drivers/hwtracing/coresight/coresight-config.c index 4f72ae71b696e..0e296289f286d 100644 --- a/drivers/hwtracing/coresight/coresight-config.c +++ b/drivers/hwtracing/coresight/coresight-config.c @@ -73,13 +73,12 @@ static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev, /* set values into the driver locations referenced in cscfg_reg_csdev */ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) { - unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags); - for (i = 0; i < feat_csdev->nr_regs; i++) - cscfg_set_reg(&feat_csdev->regs_csdev[i]); - raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); + scoped_guard(feat_csdev_lock, feat_csdev) { + for (i = 0; i < feat_csdev->nr_regs; i++) + cscfg_set_reg(&feat_csdev->regs_csdev[i]); + } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "set on enable"); return 0; @@ -88,13 +87,12 @@ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) /* copy back values from the driver locations referenced in cscfg_reg_csdev */ static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev) { - unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags); - for (i = 0; i < feat_csdev->nr_regs; i++) - cscfg_save_reg(&feat_csdev->regs_csdev[i]); - raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags); + scoped_guard(feat_csdev_lock, feat_csdev) { + for (i = 0; i < feat_csdev->nr_regs; i++) + cscfg_save_reg(&feat_csdev->regs_csdev[i]); + } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "save on disable"); } diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 90fd937d3bd83..ae6295e308131 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_CORESIGHT_CONFIG_H #define _CORESIGHT_CORESIGHT_CONFIG_H
+#include <linux/cleanup.h> #include <linux/coresight.h> #include <linux/types.h>
@@ -259,4 +260,25 @@ void cscfg_csdev_disable_config(struct cscfg_config_csdev *config_csdev); /* reset a feature to default values */ void cscfg_reset_feat(struct cscfg_feature_csdev *feat_csdev);
+#define feat_csdev_lock(feat_csdev, flags) \ + do { \ + raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \ + typecheck(unsigned long, flags); \ + if (__lock) \ + raw_spin_lock_irqsave(__lock, flags); \ + } while (0) + +#define feat_csdev_unlock(feat_csdev, flags) \ + do { \ + raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \ + typecheck(unsigned long, flags); \ + if (__lock) \ + raw_spin_unlock_irqrestore(__lock, flags); \ + } while (0) + +DEFINE_LOCK_GUARD_1(feat_csdev_lock, struct cscfg_feature_csdev, + feat_csdev_lock(_T->lock, _T->flags), + feat_csdev_unlock(_T->lock, _T->flags), + unsigned long flags) + #endif /* _CORESIGHT_CORESIGHT_CONFIG_H */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index e1a59b4345052..d24f533c623d0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, struct cscfg_regval_csdev *reg_csdev, u32 offset) { int err = -EINVAL, idx; - struct etmv4_config *drvcfg = &drvdata->config; + struct etmv4_config *drvcfg = &drvdata->active_config; u32 off_mask;
if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || @@ -154,11 +154,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, int i = 0, err = 0;
/* - * essential we set the device spinlock - this is used in the generic - * programming routines when copying values into the drvdata structures - * via the pointers setup in etm4_cfg_map_reg_offset(). + * drvdata structure of etm4 for configfs is active_config and + * this active_config is protected with csdev->mode by restricting + * access to active_config after mode changed to PERF or SYSFS. + * + * Therefore, it doesn't need to protected with etmv4_drvdata->spinlock + * to feature applying and set the NULL. */ - feat_csdev->drv_spinlock = &drvdata->spinlock; + feat_csdev->drv_spinlock = NULL;
/* process the register descriptions */ for (i = 0; i < feat_csdev->nr_regs && !err; i++) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2247ad55d4442..2df7f592bb5cf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -239,6 +239,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata) struct etm4_enable_arg { struct etmv4_drvdata *drvdata; struct coresight_path *path; + struct etmv4_config config; int rc; };
@@ -264,10 +265,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) { u64 trfcr = drvdata->trfcr; + struct etmv4_config *config = &drvdata->active_config;
- if (drvdata->config.mode & ETM_MODE_EXCL_KERN) + if (config->mode & ETM_MODE_EXCL_KERN) trfcr &= ~TRFCR_EL1_ExTRE; - if (drvdata->config.mode & ETM_MODE_EXCL_USER) + if (config->mode & ETM_MODE_EXCL_USER) trfcr &= ~TRFCR_EL1_E0TRE;
return trfcr; @@ -275,7 +277,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
/* * etm4x_allow_trace - Allow CPU tracing in the respective ELs, - * as configured by the drvdata->config.mode for the current + * as configured by the drvdata->active_config.mode for the current * session. Even though we have TRCVICTLR bits to filter the * trace in the ELs, it doesn't prevent the ETM from generating * a packet (e.g, TraceInfo) that might contain the addresses from @@ -286,12 +288,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) { u64 trfcr, guest_trfcr; + struct etmv4_config *config = &drvdata->active_config;
/* If the CPU doesn't support FEAT_TRF, nothing to do */ if (!drvdata->trfcr) return;
- if (drvdata->config.mode & ETM_MODE_EXCL_HOST) + if (config->mode & ETM_MODE_EXCL_HOST) trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else trfcr = etm4x_get_kern_user_filter(drvdata); @@ -299,7 +302,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) write_trfcr(trfcr);
/* Set filters for guests and pass to KVM */ - if (drvdata->config.mode & ETM_MODE_EXCL_GUEST) + if (config->mode & ETM_MODE_EXCL_GUEST) guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else guest_trfcr = etm4x_get_kern_user_filter(drvdata); @@ -492,7 +495,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; @@ -612,27 +615,44 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) static void etm4_enable_sysfs_smp_call(void *info) { struct etm4_enable_arg *arg = info; + struct etmv4_drvdata *drvdata; struct coresight_device *csdev; + unsigned long cfg_hash; + int preset;
if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev; - if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { - /* Someone is already using the tracer */ - arg->rc = -EBUSY; - return; + drvdata = arg->drvdata; + csdev = drvdata->csdev; + + drvdata->active_config = arg->config; + + /* enable any config activated by configfs */ + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); + if (cfg_hash) { + arg->rc = cscfg_csdev_enable_active_config(csdev, + cfg_hash, + preset); + if (arg->rc) + return; }
- arg->rc = etm4_enable_hw(arg->drvdata); + drvdata->trcid = arg->path->trace_id;
- /* The tracer didn't start */ + /* Tracer will never be paused in sysfs mode */ + drvdata->paused = false; + + arg->rc = etm4_enable_hw(drvdata); if (arg->rc) { - coresight_set_mode(csdev, CS_MODE_DISABLED); + cscfg_csdev_disable_active_config(csdev); return; }
+ drvdata->sticky_enable = true; csdev->path = arg->path; + + return; }
/* @@ -669,7 +689,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, { int ctridx; int rselector; - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config;
/* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) @@ -752,7 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, { int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config; struct perf_event_attr max_timestamp = { .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, }; @@ -919,46 +939,36 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etm4_enable_arg arg = { }; - unsigned long cfg_hash; - int ret, preset; + int ret;
- /* enable any config activated by configfs */ - cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); - if (cfg_hash) { - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); - if (ret) { - etm4_release_trace_id(drvdata); - return ret; - } + if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { + /* Someone is already using the tracer */ + return -EBUSY; }
- raw_spin_lock(&drvdata->spinlock); - - drvdata->trcid = path->trace_id; - - /* Tracer will never be paused in sysfs mode */ - drvdata->paused = false; - /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. */ arg.drvdata = drvdata; arg.path = path; + + scoped_guard(raw_spinlock, &drvdata->spinlock) { + arg.config = drvdata->config; + } + ret = smp_call_function_single(drvdata->cpu, etm4_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc; - if (!ret) - drvdata->sticky_enable = true; - - if (ret) + if (!ret) { + dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + } else { etm4_release_trace_id(drvdata); + /* The tracer didn't start */ + coresight_set_mode(csdev, CS_MODE_DISABLED); + }
- raw_spin_unlock(&drvdata->spinlock); - - if (!ret) - dev_dbg(&csdev->dev, "ETM tracing enabled\n"); return ret; }
@@ -1044,7 +1054,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control; - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; int i; @@ -1086,8 +1096,9 @@ static void etm4_disable_sysfs_smp_call(void *info)
etm4_disable_hw(drvdata);
+ cscfg_csdev_disable_active_config(drvdata->csdev); + drvdata->csdev->path = NULL; - coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); }
static int etm4_disable_perf(struct coresight_device *csdev, @@ -1130,8 +1141,9 @@ static int etm4_disable_perf(struct coresight_device *csdev, static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - raw_spin_lock(&drvdata->spinlock); + struct etmv4_config *config = &drvdata->config; + const struct etmv4_config *active_config = &drvdata->active_config; + int i;
/* * Executing etm4_disable_hw on the cpu whose ETM is being disabled @@ -1140,9 +1152,17 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, drvdata, 1);
- raw_spin_unlock(&drvdata->spinlock); + /* + * Userspace may read ss_status and cntr_val through sysfs after + * the sysfs-session has been disabled. + */ + for (i = 0; i < drvdata->nr_ss_cmp; i++) + config->ss_status[i] = active_config->ss_status[i];
- cscfg_csdev_disable_active_config(csdev); + for (i = 0; i < drvdata->nr_cntr; i++) + config->cntr_val[i] = active_config->cntr_val[i]; + + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
/* * we only release trace IDs when resetting sysfs. @@ -1690,7 +1710,7 @@ static void etm4_set_default(struct etmv4_config *config) static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) { int nr_comparator, index = 0; - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config;
/* * nr_addr_cmp holds the number of comparator _pair_, so time 2 @@ -1731,7 +1751,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, { int i, comparator, ret = 0; u64 address; - struct etmv4_config *config = &drvdata->config; + struct etmv4_config *config = &drvdata->active_config; struct etm_filters *filters = event->hw.addr_filters;
if (!filters) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 8d73248b840a6..f64c0acebc701 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,7 +1613,7 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL; - if (coresight_get_mode(drvdata->csdev)) + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); @@ -1799,7 +1799,7 @@ static ssize_t sshot_ctrl_store(struct device *dev,
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (coresight_get_mode(drvdata->csdev)) + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); @@ -1851,7 +1851,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (coresight_get_mode(drvdata->csdev)) + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index df9e0748d71ec..c33700711154d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1019,7 +1019,8 @@ struct etmv4_save_state { * allows tracing at all ELs. We don't want to compute this * at runtime, due to the additional setting of TRFCR_CX when * in EL2. Otherwise, 0. - * @config: structure holding configuration parameters. + * @active_config: structure holding current applied configuration. + * @config: structure holding sysfs mode configuration. * @save_state: State to be preserved across power loss * @skip_power_up: Indicates if an implementation can skip powering up * the trace unit. @@ -1077,6 +1078,7 @@ struct etmv4_drvdata { bool skip_power_up : 1; bool paused : 1; u64 trfcr; + struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
Hi,
On 9/15/26 12:34, Yeoreum Yun wrote:
The current ETM4x configuration via sysfs can lead to several inconsistencies:
If the configuration is modified via sysfs while a perf session is active, the running configuration may differ before a sched-out and after a subsequent sched-in.
If a perf session and a sysfs session enable tracing concurrently, the configuration from configfs may become corrupted.
There is a risk of corrupting drvdata->config if a perf session enables tracing while cscfg_csdev_disable_active_config() is being handled in etm4_disable_sysfs().
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
I'll add a comment about naming here - active_config is a bit overloaded in the code as it is also used by the csconfig code to represent a loaded and active configuration - which may at some point be applied to the active_config above.
If active_config is for the current session then curr_config would work.
Additionally config also appears as a local pointer in many of the functions. If this is the sysfs config then sysfs_config would work better.
This should make all the code a lot more readable, and easier to spot exactly which config we are dealing with.
Additionally:
Apply the configuration from configfs after taking the appropriate mode.
Since active_config and related fields are accessed only by the local CPU in etm4_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and startup/dying_cpu except when to access config fields.
As the active_config is used for cfg-configfs, etmv4 doesn't need to set its lock for the cfg-configfs since the active_config is proceted by cs_mode otherwise it would make a possible cpu-stall when it get interrupt while setting the sysfs configuration.
Therefore, set the drv_spinlock for cfg-configfs as NULL and let the cfg-configfs disable irq without grap drv_spinlock when it is NULL.
Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-config.c | 18 ++-- drivers/hwtracing/coresight/coresight-config.h | 22 ++++ drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 13 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 118 ++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- 6 files changed, 113 insertions(+), 68 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.c b/drivers/hwtracing/coresight/coresight-config.c index 4f72ae71b696e..0e296289f286d 100644 --- a/drivers/hwtracing/coresight/coresight-config.c +++ b/drivers/hwtracing/coresight/coresight-config.c @@ -73,13 +73,12 @@ static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev, /* set values into the driver locations referenced in cscfg_reg_csdev */ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) {
- unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags);
- for (i = 0; i < feat_csdev->nr_regs; i++)
cscfg_set_reg(&feat_csdev->regs_csdev[i]);- raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags);
- scoped_guard(feat_csdev_lock, feat_csdev) {
for (i = 0; i < feat_csdev->nr_regs; i++)cscfg_set_reg(&feat_csdev->regs_csdev[i]);- } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "set on enable"); return 0;
@@ -88,13 +87,12 @@ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) /* copy back values from the driver locations referenced in cscfg_reg_csdev */ static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev) {
- unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags);
- for (i = 0; i < feat_csdev->nr_regs; i++)
cscfg_save_reg(&feat_csdev->regs_csdev[i]);- raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags);
- scoped_guard(feat_csdev_lock, feat_csdev) {
for (i = 0; i < feat_csdev->nr_regs; i++)cscfg_save_reg(&feat_csdev->regs_csdev[i]);- } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "save on disable"); }
diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 90fd937d3bd83..ae6295e308131 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_CORESIGHT_CONFIG_H #define _CORESIGHT_CORESIGHT_CONFIG_H +#include <linux/cleanup.h> #include <linux/coresight.h> #include <linux/types.h> @@ -259,4 +260,25 @@ void cscfg_csdev_disable_config(struct cscfg_config_csdev *config_csdev); /* reset a feature to default values */ void cscfg_reset_feat(struct cscfg_feature_csdev *feat_csdev); +#define feat_csdev_lock(feat_csdev, flags) \
- do { \
raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \typecheck(unsigned long, flags); \if (__lock) \raw_spin_lock_irqsave(__lock, flags); \- } while (0)
+#define feat_csdev_unlock(feat_csdev, flags) \
- do { \
raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \typecheck(unsigned long, flags); \if (__lock) \raw_spin_unlock_irqrestore(__lock, flags); \- } while (0)
+DEFINE_LOCK_GUARD_1(feat_csdev_lock, struct cscfg_feature_csdev,
feat_csdev_lock(_T->lock, _T->flags),feat_csdev_unlock(_T->lock, _T->flags),unsigned long flags)- #endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index e1a59b4345052..d24f533c623d0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, struct cscfg_regval_csdev *reg_csdev, u32 offset) { int err = -EINVAL, idx;
- struct etmv4_config *drvcfg = &drvdata->config;
- struct etmv4_config *drvcfg = &drvdata->active_config; u32 off_mask;
if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || @@ -154,11 +154,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, int i = 0, err = 0; /*
* essential we set the device spinlock - this is used in the generic* programming routines when copying values into the drvdata structures* via the pointers setup in etm4_cfg_map_reg_offset().
* drvdata structure of etm4 for configfs is active_config and* this active_config is protected with csdev->mode by restricting* access to active_config after mode changed to PERF or SYSFS.** Therefore, it doesn't need to protected with etmv4_drvdata->spinlock* to feature applying and set the NULL.
- feat_csdev->drv_spinlock = &drvdata->spinlock;
- feat_csdev->drv_spinlock = NULL;
/* process the register descriptions */ for (i = 0; i < feat_csdev->nr_regs && !err; i++) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2247ad55d4442..2df7f592bb5cf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -239,6 +239,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata) struct etm4_enable_arg { struct etmv4_drvdata *drvdata; struct coresight_path *path;
- struct etmv4_config config;
drvdata contains both active_config and config - why the extra copy here?
int rc; }; @@ -264,10 +265,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) { u64 trfcr = drvdata->trfcr;
- struct etmv4_config *config = &drvdata->active_config;
- if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
- if (config->mode & ETM_MODE_EXCL_KERN) trfcr &= ~TRFCR_EL1_ExTRE;
- if (drvdata->config.mode & ETM_MODE_EXCL_USER)
- if (config->mode & ETM_MODE_EXCL_USER) trfcr &= ~TRFCR_EL1_E0TRE;
return trfcr; @@ -275,7 +277,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) /*
- etm4x_allow_trace - Allow CPU tracing in the respective ELs,
- as configured by the drvdata->config.mode for the current
- as configured by the drvdata->active_config.mode for the current
- session. Even though we have TRCVICTLR bits to filter the
- trace in the ELs, it doesn't prevent the ETM from generating
- a packet (e.g, TraceInfo) that might contain the addresses from
@@ -286,12 +288,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) { u64 trfcr, guest_trfcr;
- struct etmv4_config *config = &drvdata->active_config;
/* If the CPU doesn't support FEAT_TRF, nothing to do */ if (!drvdata->trfcr) return;
- if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
- if (config->mode & ETM_MODE_EXCL_HOST) trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -299,7 +302,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) write_trfcr(trfcr); /* Set filters for guests and pass to KVM */
- if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
- if (config->mode & ETM_MODE_EXCL_GUEST) guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else guest_trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -492,7 +495,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access;
@@ -612,27 +615,44 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) static void etm4_enable_sysfs_smp_call(void *info) { struct etm4_enable_arg *arg = info;
- struct etmv4_drvdata *drvdata; struct coresight_device *csdev;
- unsigned long cfg_hash;
- int preset;
if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */arg->rc = -EBUSY;return;
- drvdata = arg->drvdata;
- csdev = drvdata->csdev;
- drvdata->active_config = arg->config;
This can happen before the smp call removing the need for arg->config?
- /* enable any config activated by configfs */
- cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- if (cfg_hash) {
arg->rc = cscfg_csdev_enable_active_config(csdev,cfg_hash,preset);if (arg->rc)return;
- arg->rc = etm4_enable_hw(arg->drvdata);
- drvdata->trcid = arg->path->trace_id;
- /* The tracer didn't start */
- /* Tracer will never be paused in sysfs mode */
- drvdata->paused = false;
- arg->rc = etm4_enable_hw(drvdata); if (arg->rc) {
coresight_set_mode(csdev, CS_MODE_DISABLED);
cscfg_csdev_disable_active_config(csdev);
- drvdata->sticky_enable = true; csdev->path = arg->path;
- return; }
/* @@ -669,7 +689,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, { int ctridx; int rselector;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config;
/* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) @@ -752,7 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, { int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct perf_event_attr max_timestamp = { .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, };
@@ -919,46 +939,36 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etm4_enable_arg arg = { };
- unsigned long cfg_hash;
- int ret, preset;
- int ret;
- /* enable any config activated by configfs */
- cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- if (cfg_hash) {
ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);if (ret) {etm4_release_trace_id(drvdata);return ret;}
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */return -EBUSY;
- raw_spin_lock(&drvdata->spinlock);
- drvdata->trcid = path->trace_id;
- /* Tracer will never be paused in sysfs mode */
- drvdata->paused = false;
- /*
*/ arg.drvdata = drvdata; arg.path = path;
- Executing etm4_enable_hw on the cpu whose ETM is being enabled
- ensures that register writes occur when cpu is powered.
- scoped_guard(raw_spinlock, &drvdata->spinlock) {
arg.config = drvdata->config;
Given as mentioned above that once a mode is set then active_config is protected, this should simply be drvdata->active_config = drvdata->config; ??
- }
- ret = smp_call_function_single(drvdata->cpu, etm4_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc;
- if (!ret)
drvdata->sticky_enable = true;- if (ret)
- if (!ret) {
dev_dbg(&csdev->dev, "ETM tracing enabled\n");- } else { etm4_release_trace_id(drvdata);
/* The tracer didn't start */coresight_set_mode(csdev, CS_MODE_DISABLED);- }
- raw_spin_unlock(&drvdata->spinlock);
- if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");@@ -1044,7 +1054,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; int i;
@@ -1086,8 +1096,9 @@ static void etm4_disable_sysfs_smp_call(void *info) etm4_disable_hw(drvdata);
- cscfg_csdev_disable_active_config(drvdata->csdev);
- drvdata->csdev->path = NULL;
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); }
static int etm4_disable_perf(struct coresight_device *csdev, @@ -1130,8 +1141,9 @@ static int etm4_disable_perf(struct coresight_device *csdev, static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- raw_spin_lock(&drvdata->spinlock);
- struct etmv4_config *config = &drvdata->config;
- const struct etmv4_config *active_config = &drvdata->active_config;
- int i;
/* * Executing etm4_disable_hw on the cpu whose ETM is being disabled @@ -1140,9 +1152,17 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, drvdata, 1);
- raw_spin_unlock(&drvdata->spinlock);
- /*
* Userspace may read ss_status and cntr_val through sysfs after* the sysfs-session has been disabled.*/- for (i = 0; i < drvdata->nr_ss_cmp; i++)
config->ss_status[i] = active_config->ss_status[i];
- cscfg_csdev_disable_active_config(csdev);
- for (i = 0; i < drvdata->nr_cntr; i++)
config->cntr_val[i] = active_config->cntr_val[i];
Readback of TRCSEQSTR needed here too.
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
/* * we only release trace IDs when resetting sysfs. @@ -1690,7 +1710,7 @@ static void etm4_set_default(struct etmv4_config *config) static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) { int nr_comparator, index = 0;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config;
/* * nr_addr_cmp holds the number of comparator _pair_, so time 2 @@ -1731,7 +1751,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, { int i, comparator, ret = 0; u64 address;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct etm_filters *filters = event->hw.addr_filters;
if (!filters) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 8d73248b840a6..f64c0acebc701 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,7 +1613,7 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); @@ -1799,7 +1799,7 @@ static ssize_t sshot_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); @@ -1851,7 +1851,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
raw_spin_lock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index df9e0748d71ec..c33700711154d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1019,7 +1019,8 @@ struct etmv4_save_state {
allows tracing at all ELs. We don't want to compute thisat runtime, due to the additional setting of TRFCR_CX whenin EL2. Otherwise, 0.
- @config: structure holding configuration parameters.
- @active_config: structure holding current applied configuration.
- @config: structure holding sysfs mode configuration.
- @save_state: State to be preserved across power loss
- @skip_power_up: Indicates if an implementation can skip powering up
the trace unit.@@ -1077,6 +1078,7 @@ struct etmv4_drvdata { bool skip_power_up : 1; bool paused : 1; u64 trfcr;
- struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
Regards
Mike
On Fri, Sep 18, 2026 at 02:49:09PM +0100, Mike Leach wrote:
Hi,
On 9/15/26 12:34, Yeoreum Yun wrote:
The current ETM4x configuration via sysfs can lead to several inconsistencies:
If the configuration is modified via sysfs while a perf session is active, the running configuration may differ before a sched-out and after a subsequent sched-in.
If a perf session and a sysfs session enable tracing concurrently, the configuration from configfs may become corrupted.
There is a risk of corrupting drvdata->config if a perf session enables tracing while cscfg_csdev_disable_active_config() is being handled in etm4_disable_sysfs().
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
I'll add a comment about naming here - active_config is a bit overloaded in the code as it is also used by the csconfig code to represent a loaded and active configuration - which may at some point be applied to the active_config above.
If active_config is for the current session then curr_config would work.
Additionally config also appears as a local pointer in many of the functions. If this is the sysfs config then sysfs_config would work better.
This should make all the code a lot more readable, and easier to spot exactly which config we are dealing with.
Okay. then I'll change the each name with curr_config and sysfs_config and rename all.
Thanks ;)
Additionally:
Apply the configuration from configfs after taking the appropriate mode.
Since active_config and related fields are accessed only by the local CPU in etm4_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and startup/dying_cpu except when to access config fields.
As the active_config is used for cfg-configfs, etmv4 doesn't need to set its lock for the cfg-configfs since the active_config is proceted by cs_mode otherwise it would make a possible cpu-stall when it get interrupt while setting the sysfs configuration.
Therefore, set the drv_spinlock for cfg-configfs as NULL and let the cfg-configfs disable irq without grap drv_spinlock when it is NULL.
Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-config.c | 18 ++-- drivers/hwtracing/coresight/coresight-config.h | 22 ++++ drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 13 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 118 ++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- 6 files changed, 113 insertions(+), 68 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.c b/drivers/hwtracing/coresight/coresight-config.c index 4f72ae71b696e..0e296289f286d 100644 --- a/drivers/hwtracing/coresight/coresight-config.c +++ b/drivers/hwtracing/coresight/coresight-config.c @@ -73,13 +73,12 @@ static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev, /* set values into the driver locations referenced in cscfg_reg_csdev */ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) {
- unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags);
- for (i = 0; i < feat_csdev->nr_regs; i++)
cscfg_set_reg(&feat_csdev->regs_csdev[i]);- raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags);
- scoped_guard(feat_csdev_lock, feat_csdev) {
for (i = 0; i < feat_csdev->nr_regs; i++)cscfg_set_reg(&feat_csdev->regs_csdev[i]);- } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "set on enable"); return 0;
@@ -88,13 +87,12 @@ static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) /* copy back values from the driver locations referenced in cscfg_reg_csdev */ static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev) {
- unsigned long flags; int i;
- raw_spin_lock_irqsave(feat_csdev->drv_spinlock, flags);
- for (i = 0; i < feat_csdev->nr_regs; i++)
cscfg_save_reg(&feat_csdev->regs_csdev[i]);- raw_spin_unlock_irqrestore(feat_csdev->drv_spinlock, flags);
- scoped_guard(feat_csdev_lock, feat_csdev) {
for (i = 0; i < feat_csdev->nr_regs; i++)cscfg_save_reg(&feat_csdev->regs_csdev[i]);- } dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", feat_csdev->feat_desc->name, "save on disable"); }
diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 90fd937d3bd83..ae6295e308131 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_CORESIGHT_CONFIG_H #define _CORESIGHT_CORESIGHT_CONFIG_H +#include <linux/cleanup.h> #include <linux/coresight.h> #include <linux/types.h> @@ -259,4 +260,25 @@ void cscfg_csdev_disable_config(struct cscfg_config_csdev *config_csdev); /* reset a feature to default values */ void cscfg_reset_feat(struct cscfg_feature_csdev *feat_csdev); +#define feat_csdev_lock(feat_csdev, flags) \
- do { \
raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \typecheck(unsigned long, flags); \if (__lock) \raw_spin_lock_irqsave(__lock, flags); \- } while (0)
+#define feat_csdev_unlock(feat_csdev, flags) \
- do { \
raw_spinlock_t *__lock = feat_csdev->drv_spinlock; \typecheck(unsigned long, flags); \if (__lock) \raw_spin_unlock_irqrestore(__lock, flags); \- } while (0)
+DEFINE_LOCK_GUARD_1(feat_csdev_lock, struct cscfg_feature_csdev,
feat_csdev_lock(_T->lock, _T->flags),feat_csdev_unlock(_T->lock, _T->flags),unsigned long flags)- #endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index e1a59b4345052..d24f533c623d0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, struct cscfg_regval_csdev *reg_csdev, u32 offset) { int err = -EINVAL, idx;
- struct etmv4_config *drvcfg = &drvdata->config;
- struct etmv4_config *drvcfg = &drvdata->active_config; u32 off_mask; if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
@@ -154,11 +154,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, int i = 0, err = 0; /*
* essential we set the device spinlock - this is used in the generic* programming routines when copying values into the drvdata structures* via the pointers setup in etm4_cfg_map_reg_offset().
* drvdata structure of etm4 for configfs is active_config and* this active_config is protected with csdev->mode by restricting* access to active_config after mode changed to PERF or SYSFS.** Therefore, it doesn't need to protected with etmv4_drvdata->spinlock* to feature applying and set the NULL.
- feat_csdev->drv_spinlock = &drvdata->spinlock;
- feat_csdev->drv_spinlock = NULL; /* process the register descriptions */ for (i = 0; i < feat_csdev->nr_regs && !err; i++) {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2247ad55d4442..2df7f592bb5cf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -239,6 +239,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata) struct etm4_enable_arg { struct etmv4_drvdata *drvdata; struct coresight_path *path;
- struct etmv4_config config;
drvdata contains both active_config and config - why the extra copy here?
This is because of a minor consistency before applying the configuration to hardware. Since drvdata->sysfs_config could be modified while copying the contents into the active_config as a purpose of snapshot at the time of enable, add this argument.
For example, while enabling, sysfs could modify the ctxid_mask0 and ctxid_mask1 and this could be teared when active_config is copied from drvdata->config directly.
Therefore, make a config as a *snapshot* while holding a drvdata->lock. otherwise, we need to change all spinlock usage in sysfs should be irqsave but it seems much awful.
But I think we can remove it if we move the copy config to active_config into etm4_enable_sysfs() since there, sysfs_mode is taken. so active_config could be accessed safely.
I'll move the drvdata->active_config = drvdata->config into etm4_enable_sysfs() and will remove this arg.
Thanks!
int rc; }; @@ -264,10 +265,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) { u64 trfcr = drvdata->trfcr;
- struct etmv4_config *config = &drvdata->active_config;
- if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
- if (config->mode & ETM_MODE_EXCL_KERN) trfcr &= ~TRFCR_EL1_ExTRE;
- if (drvdata->config.mode & ETM_MODE_EXCL_USER)
- if (config->mode & ETM_MODE_EXCL_USER) trfcr &= ~TRFCR_EL1_E0TRE; return trfcr;
@@ -275,7 +277,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) /*
- etm4x_allow_trace - Allow CPU tracing in the respective ELs,
- as configured by the drvdata->config.mode for the current
- as configured by the drvdata->active_config.mode for the current
- session. Even though we have TRCVICTLR bits to filter the
- trace in the ELs, it doesn't prevent the ETM from generating
- a packet (e.g, TraceInfo) that might contain the addresses from
@@ -286,12 +288,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) { u64 trfcr, guest_trfcr;
- struct etmv4_config *config = &drvdata->active_config; /* If the CPU doesn't support FEAT_TRF, nothing to do */ if (!drvdata->trfcr) return;
- if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
- if (config->mode & ETM_MODE_EXCL_HOST) trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -299,7 +302,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) write_trfcr(trfcr); /* Set filters for guests and pass to KVM */
- if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
- if (config->mode & ETM_MODE_EXCL_GUEST) guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else guest_trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -492,7 +495,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access;
@@ -612,27 +615,44 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) static void etm4_enable_sysfs_smp_call(void *info) { struct etm4_enable_arg *arg = info;
- struct etmv4_drvdata *drvdata; struct coresight_device *csdev;
- unsigned long cfg_hash;
- int preset; if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */arg->rc = -EBUSY;return;
- drvdata = arg->drvdata;
- csdev = drvdata->csdev;
- drvdata->active_config = arg->config;
This can happen before the smp call removing the need for arg->config?
Yes! That's fair enough :)
- /* enable any config activated by configfs */
- cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- if (cfg_hash) {
arg->rc = cscfg_csdev_enable_active_config(csdev,cfg_hash,preset);if (arg->rc)return;
- arg->rc = etm4_enable_hw(arg->drvdata);
- drvdata->trcid = arg->path->trace_id;
- /* The tracer didn't start */
- /* Tracer will never be paused in sysfs mode */
- drvdata->paused = false;
- arg->rc = etm4_enable_hw(drvdata); if (arg->rc) {
coresight_set_mode(csdev, CS_MODE_DISABLED);
cscfg_csdev_disable_active_config(csdev);- drvdata->sticky_enable = true; csdev->path = arg->path;
- return; } /*
@@ -669,7 +689,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, { int ctridx; int rselector;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; /* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr)
@@ -752,7 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, { int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct perf_event_attr max_timestamp = { .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, };
@@ -919,46 +939,36 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etm4_enable_arg arg = { };
- unsigned long cfg_hash;
- int ret, preset;
- int ret;
- /* enable any config activated by configfs */
- cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- if (cfg_hash) {
ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);if (ret) {etm4_release_trace_id(drvdata);return ret;}
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */return -EBUSY;
- raw_spin_lock(&drvdata->spinlock);
- drvdata->trcid = path->trace_id;
- /* Tracer will never be paused in sysfs mode */
- drvdata->paused = false;
- /*
*/ arg.drvdata = drvdata; arg.path = path;
- Executing etm4_enable_hw on the cpu whose ETM is being enabled
- ensures that register writes occur when cpu is powered.
- scoped_guard(raw_spinlock, &drvdata->spinlock) {
arg.config = drvdata->config;Given as mentioned above that once a mode is set then active_config is protected, this should simply be drvdata->active_config = drvdata->config; ??
Right. Here is much better!
- }
- ret = smp_call_function_single(drvdata->cpu, etm4_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc;
- if (!ret)
drvdata->sticky_enable = true;- if (ret)
- if (!ret) {
dev_dbg(&csdev->dev, "ETM tracing enabled\n");- } else { etm4_release_trace_id(drvdata);
/* The tracer didn't start */coresight_set_mode(csdev, CS_MODE_DISABLED);- }
- raw_spin_unlock(&drvdata->spinlock);
- if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");@@ -1044,7 +1054,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; int i;
@@ -1086,8 +1096,9 @@ static void etm4_disable_sysfs_smp_call(void *info) etm4_disable_hw(drvdata);
- cscfg_csdev_disable_active_config(drvdata->csdev);
- drvdata->csdev->path = NULL;
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); } static int etm4_disable_perf(struct coresight_device *csdev,
@@ -1130,8 +1141,9 @@ static int etm4_disable_perf(struct coresight_device *csdev, static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- raw_spin_lock(&drvdata->spinlock);
- struct etmv4_config *config = &drvdata->config;
- const struct etmv4_config *active_config = &drvdata->active_config;
- int i; /*
- Executing etm4_disable_hw on the cpu whose ETM is being disabled
@@ -1140,9 +1152,17 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, drvdata, 1);
- raw_spin_unlock(&drvdata->spinlock);
- /*
* Userspace may read ss_status and cntr_val through sysfs after* the sysfs-session has been disabled.*/- for (i = 0; i < drvdata->nr_ss_cmp; i++)
config->ss_status[i] = active_config->ss_status[i];
- cscfg_csdev_disable_active_config(csdev);
- for (i = 0; i < drvdata->nr_cntr; i++)
config->cntr_val[i] = active_config->cntr_val[i];Readback of TRCSEQSTR needed here too.
Right. I've noticted after I post this patch. I'll fix in the next version. Thanks!
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); /*
- we only release trace IDs when resetting sysfs.
@@ -1690,7 +1710,7 @@ static void etm4_set_default(struct etmv4_config *config) static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) { int nr_comparator, index = 0;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; /*
- nr_addr_cmp holds the number of comparator _pair_, so time 2
@@ -1731,7 +1751,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, { int i, comparator, ret = 0; u64 address;
- struct etmv4_config *config = &drvdata->config;
- struct etmv4_config *config = &drvdata->active_config; struct etm_filters *filters = event->hw.addr_filters; if (!filters)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 8d73248b840a6..f64c0acebc701 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1613,7 +1613,7 @@ static ssize_t cntr_val_store(struct device *dev, return -EINVAL; if (val > ETM_CNTR_MAX_VAL) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY; raw_spin_lock(&drvdata->spinlock);
@@ -1799,7 +1799,7 @@ static ssize_t sshot_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY; raw_spin_lock(&drvdata->spinlock);
@@ -1851,7 +1851,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY; raw_spin_lock(&drvdata->spinlock);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index df9e0748d71ec..c33700711154d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1019,7 +1019,8 @@ struct etmv4_save_state {
allows tracing at all ELs. We don't want to compute thisat runtime, due to the additional setting of TRFCR_CX whenin EL2. Otherwise, 0.
- @config: structure holding configuration parameters.
- @active_config: structure holding current applied configuration.
- @config: structure holding sysfs mode configuration.
- @save_state: State to be preserved across power loss
- @skip_power_up: Indicates if an implementation can skip powering up
the trace unit.@@ -1077,6 +1078,7 @@ struct etmv4_drvdata { bool skip_power_up : 1; bool paused : 1; u64 trfcr;
- struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
Regards
Mike
Thanks!
The current ETM3x configuration via sysfs can lead to the following inconsistencies:
- If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in.
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session - config: the configuration set via sysfs
Additionally:
- Since active_config and related fields are accessed only by the local CPU in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and starting/dying_cpu path except when to access config fields only.
- Some of sysfs interface read etm register directly. To reduce lock scope while the etm_enable_hw()/etm_disable_hw(), handle it via IPI so that registers could be read from on proper CPU.
Fixes: 1925a470ce69 ("coresight: etm3x: splitting struct etm_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm.h | 4 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 68 ++++++++++-------- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 80 +++++++++++++++------- 3 files changed, 100 insertions(+), 52 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 1d753cca29439..f3796162168d4 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -226,7 +226,8 @@ struct etm_config { * @etmccr: value of register ETMCCR. * @etmccer: value of register ETMCCER. * @traceid: value of the current ID for this component. - * @config: structure holding configuration parameters. + * @active_config: structure holding current running configuration. + * @config: structure holding sysfs mode configuration. */ struct etm_drvdata { struct csdev_access csa; @@ -248,6 +249,7 @@ struct etm_drvdata { u32 etmccr; u32 etmccer; u32 traceid; + struct etm_config active_config; struct etm_config config; };
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 862ad0786699c..fd76a57e5f861 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,7 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) { - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level;
@@ -367,7 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr; - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base); @@ -442,32 +442,30 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) struct etm_enable_arg { struct etm_drvdata *drvdata; struct coresight_path *path; + struct etm_config config; int rc; };
static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg = info; + struct etm_drvdata *drvdata; struct coresight_device *csdev;
if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev; - if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { - /* Someone is already using the tracer */ - arg->rc = -EBUSY; - return; - } + drvdata = arg->drvdata; + csdev = drvdata->csdev;
- arg->rc = etm_enable_hw(arg->drvdata); + drvdata->active_config = arg->config; + drvdata->traceid = arg->path->trace_id;
- /* The tracer didn't start */ - if (arg->rc) { - coresight_set_mode(csdev, CS_MODE_DISABLED); + arg->rc = etm_enable_hw(arg->drvdata); + if (arg->rc) return; - }
+ drvdata->sticky_enable = true; csdev->path = arg->path; }
@@ -512,9 +510,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat struct etm_enable_arg arg = { }; int ret;
- spin_lock(&drvdata->spinlock); - - drvdata->traceid = path->trace_id; + if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { + /* Someone is already using the tracer */ + return -EBUSY; + }
/* * Configure the ETM only if the CPU is online. If it isn't online @@ -523,23 +522,27 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat if (cpu_online(drvdata->cpu)) { arg.drvdata = drvdata; arg.path = path; + + scoped_guard(spinlock, &drvdata->spinlock) { + arg.config = drvdata->config; + } + ret = smp_call_function_single(drvdata->cpu, etm_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc; - if (!ret) - drvdata->sticky_enable = true; } else { ret = -ENODEV; }
- if (ret) + if (!ret) { + dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + } else { etm_release_trace_id(drvdata); + /* The tracer didn't start */ + coresight_set_mode(csdev, CS_MODE_DISABLED); + }
- spin_unlock(&drvdata->spinlock); - - if (!ret) - dev_dbg(&csdev->dev, "ETM tracing enabled\n"); return ret; }
@@ -565,7 +568,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base); @@ -593,7 +596,6 @@ static void etm_disable_sysfs_smp_call(void *info) etm_disable_hw(drvdata);
drvdata->csdev->path = NULL; - coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); }
static void etm_disable_perf(struct coresight_device *csdev) @@ -630,8 +632,9 @@ static void etm_disable_perf(struct coresight_device *csdev) static void etm_disable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - spin_lock(&drvdata->spinlock); + struct etm_config *config = &drvdata->config; + const struct etm_config *active_config = &drvdata->active_config; + int i;
/* * Executing etm_disable_hw on the cpu whose ETM is being disabled @@ -640,7 +643,14 @@ static void etm_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, drvdata, 1);
- spin_unlock(&drvdata->spinlock); + /* + * Userspace may read seq_curr_state and cntr_val through sysfs + * after the sysfs-session has been disabled. + */ + for (i = 0; i < drvdata->nr_cntr; i++) + config->cntr_val[i] = active_config->cntr_val[i]; + + config->seq_curr_state = active_config->seq_curr_state;
/* * we only release trace IDs when resetting sysfs. @@ -649,6 +659,8 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * prior trace id allocation method */
+ coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); }
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index d4846d6364945..2c8c129228589 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -6,10 +6,48 @@
#include <linux/pid_namespace.h> #include <linux/pm_runtime.h> +#include <linux/smp.h> #include <linux/sysfs.h> #include "coresight-etm.h" #include "coresight-priv.h"
+struct etm_readl_cslocked_arg { + struct etm_drvdata *drvdata; + u32 off; + unsigned long *val; +}; + +static void etm_readl_cslocked_smp_call(void *info) +{ + struct etm_readl_cslocked_arg *arg = info; + + CS_UNLOCK(arg->drvdata->csa.base); + *arg->val = etm_readl(arg->drvdata, arg->off); + CS_LOCK(arg->drvdata->csa.base); +} + +static int etm_readl_cslocked(struct etm_drvdata *drvdata, u32 off, + unsigned long *val) +{ + int ret; + struct etm_readl_cslocked_arg arg; + + ret = pm_runtime_get_sync(drvdata->csdev->dev.parent); + if (ret < 0) + goto out; + + arg.drvdata = drvdata; + arg.off = off; + arg.val = val; + + ret = smp_call_function_single(drvdata->cpu, + etm_readl_cslocked_smp_call, + (void *)&arg, 1); +out: + pm_runtime_put(drvdata->csdev->dev.parent); + return ret; +} + static ssize_t nr_addr_cmp_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -45,18 +83,13 @@ static DEVICE_ATTR_RO(nr_ctxid_cmp); static ssize_t etmsr_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long flags, val; + int ret; + unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- pm_runtime_get_sync(dev->parent); - spin_lock_irqsave(&drvdata->spinlock, flags); - CS_UNLOCK(drvdata->csa.base); - - val = etm_readl(drvdata, ETMSR); - - CS_LOCK(drvdata->csa.base); - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(dev->parent); + ret = etm_readl_cslocked(drvdata, ETMSR, &val); + if (ret) + return ret;
return sprintf(buf, "%#lx\n", val); } @@ -74,7 +107,7 @@ static ssize_t reset_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret; - if (coresight_get_mode(drvdata->csdev)) + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
if (val) { @@ -719,7 +752,9 @@ static DEVICE_ATTR_RW(cntr_rld_event); static ssize_t cntr_val_show(struct device *dev, struct device_attribute *attr, char *buf) { + int ret; u32 val; + unsigned long val2; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config;
@@ -728,7 +763,10 @@ static ssize_t cntr_val_show(struct device *dev, val = config->cntr_val[config->cntr_idx]; spin_unlock(&drvdata->spinlock); } else { - val = etm_readl(drvdata, ETMCNTVRn(config->cntr_idx)); + ret = etm_readl_cslocked(drvdata, ETMCNTVRn(config->cntr_idx), &val2); + if (ret) + return ret; + val = val2; }
return sysfs_emit(buf, "%#x\n", val); @@ -746,7 +784,7 @@ static ssize_t cntr_val_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret; - if (coresight_get_mode(drvdata->csdev)) + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
spin_lock(&drvdata->spinlock); @@ -934,7 +972,8 @@ static DEVICE_ATTR_RW(seq_13_event); static ssize_t seq_curr_state_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val, flags; + int ret; + unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config;
@@ -943,15 +982,10 @@ static ssize_t seq_curr_state_show(struct device *dev, goto out; }
- pm_runtime_get_sync(dev->parent); - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->csa.base); - val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); - CS_LOCK(drvdata->csa.base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(dev->parent); + ret = etm_readl_cslocked(drvdata, ETMSQR, &val); + if (ret) + return ret; + val &= ETM_SQR_MASK; out: return sprintf(buf, "%#lx\n", val); }
Hi,
On 9/15/26 12:34, Yeoreum Yun wrote:
The current ETM3x configuration via sysfs can lead to the following inconsistencies:
- If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in.
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
Same comment as for the etm4 config naming
Additionally:
Since active_config and related fields are accessed only by the local CPU in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and starting/dying_cpu path except when to access config fields only.
Some of sysfs interface read etm register directly. To reduce lock scope while the etm_enable_hw()/etm_disable_hw(), handle it via IPI so that registers could be read from on proper CPU.
Fixes: 1925a470ce69 ("coresight: etm3x: splitting struct etm_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm.h | 4 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 68 ++++++++++-------- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 80 +++++++++++++++------- 3 files changed, 100 insertions(+), 52 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 1d753cca29439..f3796162168d4 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -226,7 +226,8 @@ struct etm_config {
- @etmccr: value of register ETMCCR.
- @etmccer: value of register ETMCCER.
- @traceid: value of the current ID for this component.
- @config: structure holding configuration parameters.
- @active_config: structure holding current running configuration.
*/ struct etm_drvdata { struct csdev_access csa;
- @config: structure holding sysfs mode configuration.
@@ -248,6 +249,7 @@ struct etm_drvdata { u32 etmccr; u32 etmccer; u32 traceid;
- struct etm_config active_config; struct etm_config config; };
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 862ad0786699c..fd76a57e5f861 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,7 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) {
- struct etm_config *config = &drvdata->config;
- struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level;
@@ -367,7 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr;
- struct etm_config *config = &drvdata->config;
- struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base); @@ -442,32 +442,30 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) struct etm_enable_arg { struct etm_drvdata *drvdata; struct coresight_path *path;
- struct etm_config config; int rc; };
static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg = info;
- struct etm_drvdata *drvdata; struct coresight_device *csdev;
if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */arg->rc = -EBUSY;return;- }
- drvdata = arg->drvdata;
- csdev = drvdata->csdev;
- arg->rc = etm_enable_hw(arg->drvdata);
- drvdata->active_config = arg->config;
- drvdata->traceid = arg->path->trace_id;
- /* The tracer didn't start */
- if (arg->rc) {
coresight_set_mode(csdev, CS_MODE_DISABLED);
- arg->rc = etm_enable_hw(arg->drvdata);
- if (arg->rc) return;
- }
- drvdata->sticky_enable = true; csdev->path = arg->path; }
@@ -512,9 +510,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat struct etm_enable_arg arg = { }; int ret;
- spin_lock(&drvdata->spinlock);
- drvdata->traceid = path->trace_id;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */return -EBUSY;- }
/* * Configure the ETM only if the CPU is online. If it isn't online @@ -523,23 +522,27 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat if (cpu_online(drvdata->cpu)) { arg.drvdata = drvdata; arg.path = path;
scoped_guard(spinlock, &drvdata->spinlock) {arg.config = drvdata->config;}
Again I think the arg.config is unnecessary
Regards
Mike
ret = smp_call_function_single(drvdata->cpu, etm_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc;
if (!ret)drvdata->sticky_enable = true;
- if (ret)
- if (!ret) {
dev_dbg(&csdev->dev, "ETM tracing enabled\n");- } else { etm_release_trace_id(drvdata);
/* The tracer didn't start */coresight_set_mode(csdev, CS_MODE_DISABLED);- }
- spin_unlock(&drvdata->spinlock);
- if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");@@ -565,7 +568,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i;
- struct etm_config *config = &drvdata->config;
- struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base); @@ -593,7 +596,6 @@ static void etm_disable_sysfs_smp_call(void *info) etm_disable_hw(drvdata); drvdata->csdev->path = NULL;
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); }
static void etm_disable_perf(struct coresight_device *csdev) @@ -630,8 +632,9 @@ static void etm_disable_perf(struct coresight_device *csdev) static void etm_disable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- spin_lock(&drvdata->spinlock);
- struct etm_config *config = &drvdata->config;
- const struct etm_config *active_config = &drvdata->active_config;
- int i;
/* * Executing etm_disable_hw on the cpu whose ETM is being disabled @@ -640,7 +643,14 @@ static void etm_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, drvdata, 1);
- spin_unlock(&drvdata->spinlock);
- /*
* Userspace may read seq_curr_state and cntr_val through sysfs* after the sysfs-session has been disabled.*/- for (i = 0; i < drvdata->nr_cntr; i++)
config->cntr_val[i] = active_config->cntr_val[i];- config->seq_curr_state = active_config->seq_curr_state;
/* * we only release trace IDs when resetting sysfs. @@ -649,6 +659,8 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * prior trace id allocation method */
- coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
- dev_dbg(&csdev->dev, "ETM tracing disabled\n"); }
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index d4846d6364945..2c8c129228589 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -6,10 +6,48 @@ #include <linux/pid_namespace.h> #include <linux/pm_runtime.h> +#include <linux/smp.h> #include <linux/sysfs.h> #include "coresight-etm.h" #include "coresight-priv.h" +struct etm_readl_cslocked_arg {
- struct etm_drvdata *drvdata;
- u32 off;
- unsigned long *val;
+};
+static void etm_readl_cslocked_smp_call(void *info) +{
- struct etm_readl_cslocked_arg *arg = info;
- CS_UNLOCK(arg->drvdata->csa.base);
- *arg->val = etm_readl(arg->drvdata, arg->off);
- CS_LOCK(arg->drvdata->csa.base);
+}
+static int etm_readl_cslocked(struct etm_drvdata *drvdata, u32 off,
unsigned long *val)+{
- int ret;
- struct etm_readl_cslocked_arg arg;
- ret = pm_runtime_get_sync(drvdata->csdev->dev.parent);
- if (ret < 0)
goto out;- arg.drvdata = drvdata;
- arg.off = off;
- arg.val = val;
- ret = smp_call_function_single(drvdata->cpu,
etm_readl_cslocked_smp_call,(void *)&arg, 1);+out:
- pm_runtime_put(drvdata->csdev->dev.parent);
- return ret;
+}
- static ssize_t nr_addr_cmp_show(struct device *dev, struct device_attribute *attr, char *buf) {
@@ -45,18 +83,13 @@ static DEVICE_ATTR_RO(nr_ctxid_cmp); static ssize_t etmsr_show(struct device *dev, struct device_attribute *attr, char *buf) {
- unsigned long flags, val;
- int ret;
- unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- pm_runtime_get_sync(dev->parent);
- spin_lock_irqsave(&drvdata->spinlock, flags);
- CS_UNLOCK(drvdata->csa.base);
- val = etm_readl(drvdata, ETMSR);
- CS_LOCK(drvdata->csa.base);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(dev->parent);
- ret = etm_readl_cslocked(drvdata, ETMSR, &val);
- if (ret)
return ret;return sprintf(buf, "%#lx\n", val); } @@ -74,7 +107,7 @@ static ssize_t reset_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
if (val) { @@ -719,7 +752,9 @@ static DEVICE_ATTR_RW(cntr_rld_event); static ssize_t cntr_val_show(struct device *dev, struct device_attribute *attr, char *buf) {
- int ret; u32 val;
- unsigned long val2; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config;
@@ -728,7 +763,10 @@ static ssize_t cntr_val_show(struct device *dev, val = config->cntr_val[config->cntr_idx]; spin_unlock(&drvdata->spinlock); } else {
val = etm_readl(drvdata, ETMCNTVRn(config->cntr_idx));
ret = etm_readl_cslocked(drvdata, ETMCNTVRn(config->cntr_idx), &val2);if (ret)return ret;val = val2;return sysfs_emit(buf, "%#x\n", val); @@ -746,7 +784,7 @@ static ssize_t cntr_val_store(struct device *dev, ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (coresight_get_mode(drvdata->csdev))
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) return -EBUSY;
spin_lock(&drvdata->spinlock); @@ -934,7 +972,8 @@ static DEVICE_ATTR_RW(seq_13_event); static ssize_t seq_curr_state_show(struct device *dev, struct device_attribute *attr, char *buf) {
- unsigned long val, flags;
- int ret;
- unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config;
@@ -943,15 +982,10 @@ static ssize_t seq_curr_state_show(struct device *dev, goto out; }
- pm_runtime_get_sync(dev->parent);
- spin_lock_irqsave(&drvdata->spinlock, flags);
- CS_UNLOCK(drvdata->csa.base);
- val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
- CS_LOCK(drvdata->csa.base);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(dev->parent);
- ret = etm_readl_cslocked(drvdata, ETMSQR, &val);
- if (ret)
return ret;- val &= ETM_SQR_MASK; out: return sprintf(buf, "%#lx\n", val); }
Hi,
On 9/15/26 12:34, Yeoreum Yun wrote:
The current ETM3x configuration via sysfs can lead to the following inconsistencies:
- If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in.
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
Same comment as for the etm4 config naming
Acked.
Additionally:
Since active_config and related fields are accessed only by the local CPU in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and starting/dying_cpu path except when to access config fields only.
Some of sysfs interface read etm register directly. To reduce lock scope while the etm_enable_hw()/etm_disable_hw(), handle it via IPI so that registers could be read from on proper CPU.
Fixes: 1925a470ce69 ("coresight: etm3x: splitting struct etm_drvdata") Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm.h | 4 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 68 ++++++++++-------- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 80 +++++++++++++++------- 3 files changed, 100 insertions(+), 52 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 1d753cca29439..f3796162168d4 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -226,7 +226,8 @@ struct etm_config {
- @etmccr: value of register ETMCCR.
- @etmccer: value of register ETMCCER.
- @traceid: value of the current ID for this component.
- @config: structure holding configuration parameters.
- @active_config: structure holding current running configuration.
*/ struct etm_drvdata { struct csdev_access csa;
- @config: structure holding sysfs mode configuration.
@@ -248,6 +249,7 @@ struct etm_drvdata { u32 etmccr; u32 etmccer; u32 traceid;
- struct etm_config active_config; struct etm_config config; };
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 862ad0786699c..fd76a57e5f861 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,7 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) {
- struct etm_config *config = &drvdata->config;
- struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level;
@@ -367,7 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr;
- struct etm_config *config = &drvdata->config;
- struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->csa.base);
@@ -442,32 +442,30 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) struct etm_enable_arg { struct etm_drvdata *drvdata; struct coresight_path *path;
- struct etm_config config; int rc; }; static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg = info;
- struct etm_drvdata *drvdata; struct coresight_device *csdev; if (WARN_ON(!arg)) return;
- csdev = arg->drvdata->csdev;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */arg->rc = -EBUSY;return;- }
- drvdata = arg->drvdata;
- csdev = drvdata->csdev;
- arg->rc = etm_enable_hw(arg->drvdata);
- drvdata->active_config = arg->config;
- drvdata->traceid = arg->path->trace_id;
- /* The tracer didn't start */
- if (arg->rc) {
coresight_set_mode(csdev, CS_MODE_DISABLED);
- arg->rc = etm_enable_hw(arg->drvdata);
- if (arg->rc) return;
- }
- drvdata->sticky_enable = true; csdev->path = arg->path; }
@@ -512,9 +510,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat struct etm_enable_arg arg = { }; int ret;
- spin_lock(&drvdata->spinlock);
- drvdata->traceid = path->trace_id;
- if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */return -EBUSY;- } /*
- Configure the ETM only if the CPU is online. If it isn't online
@@ -523,23 +522,27 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat if (cpu_online(drvdata->cpu)) { arg.drvdata = drvdata; arg.path = path;
scoped_guard(spinlock, &drvdata->spinlock) {arg.config = drvdata->config;}Again I think the arg.config is unnecessary
Agree. I'll change as etm4's comment!
Thanks!
[...]
cpu online() check is done in coresight_validate_source_sysfs() already. and smp_call_function_single() will fail when cpu is offline.
Therefore, remove redundant check in etm_enable_sysfs().
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 26 +++++++++------------- 1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index fd76a57e5f861..12bb38dc596e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -515,25 +515,19 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat return -EBUSY; }
- /* - * Configure the ETM only if the CPU is online. If it isn't online - * hw configuration will take place on the local CPU during bring up. - */ - if (cpu_online(drvdata->cpu)) { - arg.drvdata = drvdata; - arg.path = path; + arg.drvdata = drvdata; + arg.path = path;
- scoped_guard(spinlock, &drvdata->spinlock) { - arg.config = drvdata->config; - } + scoped_guard(spinlock, &drvdata->spinlock) { + arg.config = drvdata->config; + }
- ret = smp_call_function_single(drvdata->cpu, - etm_enable_sysfs_smp_call, &arg, 1); - if (!ret) - ret = arg.rc; - } else { + ret = smp_call_function_single(drvdata->cpu, + etm_enable_sysfs_smp_call, &arg, 1); + if (!ret) + ret = arg.rc; + else ret = -ENODEV; - }
if (!ret) { dev_dbg(&csdev->dev, "ETM tracing enabled\n");
Reviewed-by: Mike Leach mike.leach@arm.com
On 9/15/26 12:34, Yeoreum Yun wrote:
cpu online() check is done in coresight_validate_source_sysfs() already. and smp_call_function_single() will fail when cpu is offline.
Therefore, remove redundant check in etm_enable_sysfs().
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm3x-core.c | 26 +++++++++------------- 1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index fd76a57e5f861..12bb38dc596e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -515,25 +515,19 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat return -EBUSY; }
- /*
* Configure the ETM only if the CPU is online. If it isn't online* hw configuration will take place on the local CPU during bring up.*/- if (cpu_online(drvdata->cpu)) {
arg.drvdata = drvdata;arg.path = path;
- arg.drvdata = drvdata;
- arg.path = path;
scoped_guard(spinlock, &drvdata->spinlock) {arg.config = drvdata->config;}
- scoped_guard(spinlock, &drvdata->spinlock) {
arg.config = drvdata->config;- }
ret = smp_call_function_single(drvdata->cpu,etm_enable_sysfs_smp_call, &arg, 1);if (!ret)ret = arg.rc;- } else {
- ret = smp_call_function_single(drvdata->cpu,
etm_enable_sysfs_smp_call, &arg, 1);- if (!ret)
ret = arg.rc;- else ret = -ENODEV;
- }
if (!ret) { dev_dbg(&csdev->dev, "ETM tracing enabled\n");
Introduce struct etm4_caps to describe ETMv4 capabilities and move capabilities information into it.
Reviewed-by: Leo Yan leo.yan@arm.com Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 244 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 192 +++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 180 ++++++++------- 3 files changed, 336 insertions(+), 280 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2df7f592bb5cf..70a5c0b4fad1c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -92,8 +92,9 @@ static int etm4_probe_cpu(unsigned int cpu); */ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) { - return (n < drvdata->nr_ss_cmp) && - drvdata->nr_pe_cmp && + const struct etmv4_caps *caps = &drvdata->caps; + + return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && (drvdata->config.ss_status[n] & TRCSSCSRn_PC); }
@@ -164,17 +165,20 @@ static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { + struct etmv4_caps *caps = &drvdata->caps; u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
- drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); + caps->os_lock_model = ETM_OSLSR_OSLM(oslsr); }
static void etm_write_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa, u32 val) { + const struct etmv4_caps *caps = &drvdata->caps; + val = !!val;
- switch (drvdata->os_lock_model) { + switch (caps->os_lock_model) { case ETM_OSLOCK_PRESENT: etm4x_relaxed_write32(csa, val, TRCOSLAR); break; @@ -183,7 +187,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drvdata, break; default: pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", - smp_processor_id(), drvdata->os_lock_model); + smp_processor_id(), caps->os_lock_model); fallthrough; case ETM_OSLOCK_NI: return; @@ -495,6 +499,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct device *etm_dev = &csdev->dev; @@ -526,14 +531,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); - if (drvdata->nr_pe) + if (caps->nr_pe) etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); /* nothing specific implemented */ etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); @@ -543,18 +548,18 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++) + for (i = 0; i < caps->nr_seq_ctrls; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - if (drvdata->nrseqstate) { + if (caps->nrseqstate) { etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); } - if (drvdata->numextinsel) + if (caps->numextinsel) etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); - for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); @@ -564,10 +569,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) * Resource selector pair 0 is always implemented and reserved. As * such start at 2. */ - for (i = 2; i < drvdata->nr_resource * 2; i++) + for (i = 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < caps->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) config->ss_status[i] &= ~TRCSSCSRn_STATUS; @@ -576,23 +581,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i = 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); } - for (i = 0; i < drvdata->numcidc; i++) + for (i = 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
- for (i = 0; i < drvdata->numvmidc; i++) + for (i = 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
- if (!drvdata->skip_power_up) { + if (!caps->skip_power_up) { u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
/* @@ -689,19 +694,20 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, { int ctridx; int rselector; + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config;
/* No point in trying if we don't have at least one counter */ - if (!drvdata->nr_cntr) + if (!caps->nr_cntr) return -EINVAL;
/* Find a counter that hasn't been initialised */ - for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) + for (ctridx = 0; ctridx < caps->nr_cntr; ctridx++) if (config->cntr_val[ctridx] == 0) break;
/* All the counters have been configured already, bail out */ - if (ctridx == drvdata->nr_cntr) { + if (ctridx == caps->nr_cntr) { pr_debug("%s: no available counter found\n", __func__); return -ENOSPC; } @@ -717,11 +723,11 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, * ETMIDR4 gives the number of resource selector _pairs_, hence multiply * by 2. */ - for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) + for (rselector = 2; rselector < caps->nr_resource * 2; rselector++) if (!config->res_ctrl[rselector]) break;
- if (rselector == drvdata->nr_resource * 2) { + if (rselector == caps->nr_resource * 2) { pr_debug("%s: no available resource selector found\n", __func__); return -ENOSPC; @@ -772,6 +778,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, { int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct perf_event_attr max_timestamp = { .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, @@ -810,8 +817,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev, cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; - if (cc_threshold < drvdata->ccitmin) - cc_threshold = drvdata->ccitmin; + if (cc_threshold < caps->ccitmin) + cc_threshold = caps->ccitmin; config->ccctlr = cc_threshold; }
@@ -859,13 +866,13 @@ static int etm4_parse_event_config(struct coresight_device *csdev, }
/* return stack - enable if selected and supported */ - if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack) + if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack) /* bit[12], Return stack enable bit */ config->cfg |= TRCCONFIGR_RS;
/* branch broadcast - enable if selected and supported */ if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { - if (!drvdata->trcbb) { + if (!caps->trcbb) { /* * Missing BB support could cause silent decode errors * so fail to open if it's not supported. @@ -1054,6 +1061,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control; + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; @@ -1062,7 +1070,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata);
- if (!drvdata->skip_power_up) { + if (!caps->skip_power_up) { /* power can be removed from the trace unit now */ control = etm4x_relaxed_read32(csa, TRCPDCR); control &= ~TRCPDCR_PU; @@ -1072,13 +1080,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) etm4_disable_trace_unit(drvdata);
/* read the status of the single shot comparators */ - for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < caps->nr_ss_cmp; i++) { config->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); }
/* read back the current counter values */ - for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { config->cntr_val[i] = etm4x_relaxed_read32(csa, TRCCNTVRn(i)); } @@ -1141,6 +1149,7 @@ static int etm4_disable_perf(struct coresight_device *csdev, static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; const struct etmv4_config *active_config = &drvdata->active_config; int i; @@ -1156,10 +1165,10 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) * Userspace may read ss_status and cntr_val through sysfs after * the sysfs-session has been disabled. */ - for (i = 0; i < drvdata->nr_ss_cmp; i++) + for (i = 0; i < caps->nr_ss_cmp; i++) config->ss_status[i] = active_config->ss_status[i];
- for (i = 0; i < drvdata->nr_cntr; i++) + for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); @@ -1373,7 +1382,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] = { {}, };
-static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) +static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps) { /* * Erratum affected cpus will read 256 as the minimum @@ -1383,8 +1392,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) * this problem. */ if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) { - if (drvdata->ccitmin == 256) - drvdata->ccitmin = 4; + if (caps->ccitmin == 256) + caps->ccitmin = 4; } }
@@ -1397,11 +1406,13 @@ static void etm4_init_arch_data(void *info) u32 etmidr5; struct etm4_init_arg *init_arg = info; struct etmv4_drvdata *drvdata; + struct etmv4_caps *caps; struct csdev_access *csa; struct device *dev = init_arg->dev; int i;
drvdata = dev_get_drvdata(init_arg->dev); + caps = &drvdata->caps; csa = init_arg->csa;
/* @@ -1414,7 +1425,7 @@ static void etm4_init_arch_data(void *info)
if (!csa->io_mem || fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) - drvdata->skip_power_up = true; + caps->skip_power_up = true;
/* Detect the support for OS Lock before we actually use it */ etm_detect_os_lock(drvdata, csa); @@ -1429,71 +1440,71 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */ - drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); + caps->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); /* TRCBB, bit[5] Branch broadcast tracing support bit */ - drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); + caps->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); /* TRCCOND, bit[6] Conditional instruction tracing support bit */ - drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); + caps->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); /* TRCCCI, bit[7] Cycle counting instruction bit */ - drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); + caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */ - drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); + caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); /* NUMEVENT, bits[11:10] Number of events field */ - drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); + caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); /* QSUPP, bits[16:15] Q element support field */ - drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); - if (drvdata->q_support) - drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT); + caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); + if (caps->q_support) + caps->q_filt = !!(etmidr0 & TRCIDR0_QFILT); /* TSSIZE, bits[28:24] Global timestamp size field */ - drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); + caps->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
/* maximum size of resources */ etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ - drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); + caps->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); /* VMIDSIZE, bits[14:10] Indicates the VMID size */ - drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); + caps->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ - drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); + caps->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ - drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); - etm4_fixup_wrong_ccitmin(drvdata); + caps->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); + etm4_fixup_wrong_ccitmin(caps);
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ - drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); - drvdata->config.s_ex_level = drvdata->s_ex_level; + caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); + drvdata->config.s_ex_level = caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ - drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); + caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /* * TRCERR, bit[24] whether a trace unit can trace a * system error exception. */ - drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); + caps->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ - drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); + caps->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); /* STALLCTL, bit[26] is stall control implemented? */ - drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); + caps->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); /* SYSSTALL, bit[27] implementation can support stall control? */ - drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); + caps->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); /* * NUMPROC - the number of PEs available for tracing, 5bits * = TRCIDR3.bits[13:12]bits[30:28] * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) * bits[3:0] = TRCIDR3.bits[30:28] */ - drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | - FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); + caps->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | + FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ - drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW); + caps->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
/* number of resources trace unit supports */ etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ - drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); + caps->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ - drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); + caps->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); /* * NUMRSPAIR, bits[19:16] * The number of resource pairs conveyed by the HW starts at 0, i.e a @@ -1504,43 +1515,43 @@ static void etm4_init_arch_data(void *info) * the default TRUE and FALSE resource selectors are omitted. * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ - drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); - if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) - drvdata->nr_resource += 1; + caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); + if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0)) + caps->nr_resource += 1; /* * NUMSSCC, bits[23:20] the number of single-shot * comparator control for tracing. Read any status regs as these * also contain RO capability data. */ - drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); - for (i = 0; i < drvdata->nr_ss_cmp; i++) { + caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); + for (i = 0; i < caps->nr_ss_cmp; i++) { drvdata->config.ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ - drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); + caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ - drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); + caps->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ - drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); - drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); + caps->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); + caps->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ - drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); + caps->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); /* ATBTRIG, bit[22] implementation can support ATB triggers? */ - drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); + caps->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); /* * LPOVERRIDE, bit[23] implementation supports * low-power state override */ - drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); + caps->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power_up); /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ - drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); - if (drvdata->nrseqstate) - drvdata->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS; + caps->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); + if (caps->nrseqstate) + caps->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS; /* NUMCNTR, bits[30:28] number of counters available for tracing */ - drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); + caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
coresight_clear_self_claim_tag_unlocked(csa); etm4_cs_lock(drvdata, csa); @@ -1716,7 +1727,7 @@ static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) * nr_addr_cmp holds the number of comparator _pair_, so time 2 * for the total number of comparators. */ - nr_comparator = drvdata->nr_addr_cmp * 2; + nr_comparator = drvdata->caps.nr_addr_cmp * 2;
/* Go through the tally of comparators looking for a free one. */ while (index < nr_comparator) { @@ -1873,6 +1884,7 @@ static int etm4_cpu_save(struct coresight_device *csdev) { int i, ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_save_state *state; struct csdev_access *csa; struct device *etm_dev; @@ -1905,57 +1917,56 @@ static int etm4_cpu_save(struct coresight_device *csdev)
state = drvdata->save_state;
- if (drvdata->nr_pe) + if (caps->nr_pe) state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); - if (drvdata->q_filt) + if (caps->q_filt) state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
state->trcvictlr = etm4x_read32(csa, TRCVICTLR); state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++) + for (i = 0; i < caps->nr_seq_ctrls; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - - if (drvdata->nrseqstate) { + if (caps->nrseqstate) { state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); }
- if (drvdata->numextinsel) + if (caps->numextinsel) state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); }
/* Resource selector pair 0 is reserved */ - for (i = 2; i < drvdata->nr_resource * 2; i++) + for (i = 2; i < caps->nr_resource * 2; i++) state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < caps->nr_ss_cmp; i++) { state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); }
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i = 0; i < caps->nr_addr_cmp * 2; i++) { state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); } @@ -1967,23 +1978,23 @@ static int etm4_cpu_save(struct coresight_device *csdev) * unit") of ARM IHI 0064D. */
- for (i = 0; i < drvdata->numcidc; i++) + for (i = 0; i < caps->numcidc; i++) state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++) + for (i = 0; i < caps->numvmidc; i++) state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) state->trcvmidcctlr1 = etm4x_read32(csa, TRCVMIDCCTLR1);
state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
- if (!drvdata->skip_power_up) + if (!caps->skip_power_up) state->trcpdcr = etm4x_read32(csa, TRCPDCR);
/* wait for TRCSTATR.IDLE to go up */ @@ -2000,7 +2011,7 @@ static int etm4_cpu_save(struct coresight_device *csdev) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */ - if (!drvdata->skip_power_up) + if (!caps->skip_power_up) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: @@ -2012,83 +2023,84 @@ static void etm4_cpu_restore(struct coresight_device *csdev) { int i; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_save_state *state = drvdata->save_state; struct csdev_access *csa = &drvdata->csdev->access;
etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (drvdata->nr_pe) + if (caps->nr_pe) etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); - if (drvdata->q_filt) + if (caps->q_filt) etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++) + for (i = 0; i < caps->nr_seq_ctrls; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
- if (drvdata->nrseqstate) { + if (caps->nrseqstate) { etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); } - if (drvdata->numextinsel) + if (caps->numextinsel) etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); }
/* Resource selector pair 0 is reserved */ - for (i = 2; i < drvdata->nr_resource * 2; i++) + for (i = 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < caps->nr_ss_cmp; i++) { etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); }
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i = 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); }
- for (i = 0; i < drvdata->numcidc; i++) + for (i = 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++) + for (i = 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, state->trcvmidcctlr1, TRCVMIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (!drvdata->skip_power_up) + if (!caps->skip_power_up) etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
/* diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index f64c0acebc701..f6d053f73264c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_pe_cmp; + val = caps->nr_pe_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_pe_cmp); @@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp; + val = caps->nr_addr_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp); @@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr; + val = caps->nr_cntr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr); @@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ext_inp; + val = caps->nr_ext_inp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ext_inp); @@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numcidc; + val = caps->numcidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numcidc); @@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numvmidc; + val = caps->numvmidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numvmidc); @@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nrseqstate; + val = caps->nrseqstate; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nrseqstate); @@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_resource; + val = caps->nr_resource; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_resource); @@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ss_cmp; + val = caps->nr_ss_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ss_cmp); @@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev, int i; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev, config->stall_ctrl = 0x0;
/* Reset trace synchronization period to 2^8 = 256 bytes*/ - if (drvdata->syncpr == false) + if (!caps->syncpr) config->syncfreq = 0x8;
/* @@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev, * each trace run. */ config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); - if (drvdata->nr_addr_cmp > 0) { + if (caps->nr_addr_cmp > 0) { config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ config->vinst_ctrl |= TRCVICTLR_SSSTATUS; @@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev, config->vipcssctlr = 0x0;
/* Disable seq events */ - for (i = 0; i < drvdata->nr_seq_ctrls; i++) + for (i = 0; i < caps->nr_seq_ctrls; i++) config->seq_ctrl[i] = 0x0; config->seq_rst = 0x0; config->seq_state = 0x0; @@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev, config->ext_inp = 0x0;
config->cntr_idx = 0x0; - for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { config->cntrldvr[i] = 0x0; config->cntr_ctrl[i] = 0x0; config->cntr_val[i] = 0x0; }
config->res_idx = 0x0; - for (i = 2; i < 2 * drvdata->nr_resource; i++) + for (i = 2; i < 2 * caps->nr_resource; i++) config->res_ctrl[i] = 0x0;
config->ss_idx = 0x0; - for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < caps->nr_ss_cmp; i++) { config->ss_ctrl[i] = 0x0; config->ss_pe_cmp[i] = 0x0; }
config->addr_idx = 0x0; - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i = 0; i < caps->nr_addr_cmp * 2; i++) { config->addr_val[i] = 0x0; config->addr_acc[i] = 0x0; config->addr_type[i] = ETM_ADDR_TYPE_NONE; }
config->ctxid_idx = 0x0; - for (i = 0; i < drvdata->numcidc; i++) + for (i = 0; i < caps->numcidc; i++) config->ctxid_pid[i] = 0x0;
config->ctxid_mask0 = 0x0; config->ctxid_mask1 = 0x0;
config->vmid_idx = 0x0; - for (i = 0; i < drvdata->numvmidc; i++) + for (i = 0; i < caps->numvmidc; i++) config->vmid_val[i] = 0x0; config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0; @@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev, { unsigned long val, mode; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); config->mode = val & ETMv4_MODE_ALL;
- if (drvdata->instrp0 == true) { + if (caps->instrp0) { /* start by clearing instruction P0 field */ config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE; if (config->mode & ETM_MODE_LOAD) @@ -323,45 +334,44 @@ static ssize_t mode_store(struct device *dev, }
/* bit[3], Branch broadcast mode */ - if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true)) + if ((config->mode & ETM_MODE_BB) && (caps->trcbb)) config->cfg |= TRCCONFIGR_BB; else config->cfg &= ~TRCCONFIGR_BB;
/* bit[4], Cycle counting instruction trace bit */ if ((config->mode & ETMv4_MODE_CYCACC) && - (drvdata->trccci == true)) + (caps->trccci == true)) config->cfg |= TRCCONFIGR_CCI; else config->cfg &= ~TRCCONFIGR_CCI;
/* bit[6], Context ID tracing bit */ - if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size)) + if ((config->mode & ETMv4_MODE_CTXID) && (caps->ctxid_size)) config->cfg |= TRCCONFIGR_CID; else config->cfg &= ~TRCCONFIGR_CID;
- if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size)) + if ((config->mode & ETM_MODE_VMID) && (caps->vmid_size)) config->cfg |= TRCCONFIGR_VMID; else config->cfg &= ~TRCCONFIGR_VMID;
/* bits[10:8], Conditional instruction tracing bit */ mode = ETM_MODE_COND(config->mode); - if (drvdata->trccond == true) { + if (caps->trccond) { config->cfg &= ~TRCCONFIGR_COND_MASK; config->cfg |= mode << __bf_shf(TRCCONFIGR_COND_MASK); }
/* bit[11], Global timestamp tracing bit */ - if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size)) + if ((config->mode & ETMv4_MODE_TIMESTAMP) && (caps->ts_size)) config->cfg |= TRCCONFIGR_TS; else config->cfg &= ~TRCCONFIGR_TS;
/* bit[12], Return stack enable bit */ - if ((config->mode & ETM_MODE_RETURNSTACK) && - (drvdata->retstack == true)) + if ((config->mode & ETM_MODE_RETURNSTACK) && (caps->retstack)) config->cfg |= TRCCONFIGR_RS; else config->cfg &= ~TRCCONFIGR_RS; @@ -375,31 +385,29 @@ static ssize_t mode_store(struct device *dev, * Always set the low bit for any requested mode. Valid combos are * 0b00, 0b01 and 0b11. */ - if (mode && drvdata->q_support) + if (mode && caps->q_support) config->cfg |= TRCCONFIGR_QE_W_COUNTS; /* * if supported, Q elements with and without instruction * counts are enabled */ - if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) + if ((mode & BIT(1)) && (caps->q_support & BIT(1))) config->cfg |= TRCCONFIGR_QE_WO_COUNTS;
/* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ - if ((config->mode & ETM_MODE_ATB_TRIGGER) && - (drvdata->atbtrig == true)) + if ((config->mode & ETM_MODE_ATB_TRIGGER) && (caps->atbtrig)) config->eventctrl1 |= TRCEVENTCTL1R_ATB; else config->eventctrl1 &= ~TRCEVENTCTL1R_ATB;
/* bit[12], Low-power state behavior override bit */ - if ((config->mode & ETM_MODE_LPOVERRIDE) && - (drvdata->lpoverride == true)) + if ((config->mode & ETM_MODE_LPOVERRIDE) && (caps->lpoverride)) config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE; else config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE;
/* bit[8], Instruction stall bit */ - if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) + if ((config->mode & ETM_MODE_ISTALL_EN) && (caps->stallctl)) config->stall_ctrl |= TRCSTALLCTLR_ISTALL; else config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL; @@ -411,8 +419,7 @@ static ssize_t mode_store(struct device *dev, config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY;
/* bit[13], Trace overflow prevention bit */ - if ((config->mode & ETM_MODE_NOOVERFLOW) && - (drvdata->nooverflow == true)) + if ((config->mode & ETM_MODE_NOOVERFLOW) && (caps->nooverflow)) config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW; else config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW; @@ -430,8 +437,7 @@ static ssize_t mode_store(struct device *dev, config->vinst_ctrl &= ~TRCVICTLR_TRCRESET;
/* bit[11], Whether a trace unit must trace a system error exception */ - if ((config->mode & ETM_MODE_TRACE_ERR) && - (drvdata->trc_error == true)) + if ((config->mode & ETM_MODE_TRACE_ERR) && (caps->trc_error)) config->vinst_ctrl |= TRCVICTLR_TRCERR; else config->vinst_ctrl &= ~TRCVICTLR_TRCERR; @@ -463,13 +469,14 @@ static ssize_t pe_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); - if (val > drvdata->nr_pe) { + if (val > caps->nr_pe) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -498,13 +505,14 @@ static ssize_t event_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); - switch (drvdata->nr_event) { + switch (caps->nr_event) { case 0x0: /* EVENT0, bits[7:0] */ config->eventctrl0 = val & 0xFF; @@ -547,6 +555,7 @@ static ssize_t event_instren_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -555,7 +564,7 @@ static ssize_t event_instren_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); /* start by clearing all instruction event enable bits */ config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; - switch (drvdata->nr_event) { + switch (caps->nr_event) { case 0x0: /* generate Event element for event 1 */ config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; @@ -603,11 +612,12 @@ static ssize_t event_ts_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!drvdata->ts_size) + if (!caps->ts_size) return -EINVAL;
config->ts_ctrl = val & ETMv4_EVENT_MASK; @@ -633,11 +643,12 @@ static ssize_t syncfreq_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (drvdata->syncpr == true) + if (caps->syncpr) return -EINVAL;
config->syncfreq = val & ETMv4_SYNC_MASK; @@ -663,6 +674,7 @@ static ssize_t cyc_threshold_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -670,7 +682,7 @@ static ssize_t cyc_threshold_store(struct device *dev,
/* mask off max threshold before checking min value */ val &= ETM_CYC_THRESHOLD_MASK; - if (val < drvdata->ccitmin) + if (val < caps->ccitmin) return -EINVAL;
config->ccctlr = val; @@ -696,13 +708,14 @@ static ssize_t bb_ctrl_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (drvdata->trcbb == false) + if (!caps->trcbb) return -EINVAL; - if (!drvdata->nr_addr_cmp) + if (!caps->nr_addr_cmp) return -EINVAL;
/* @@ -768,6 +781,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -777,7 +791,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, /* clear all EXLEVEL_S bits */ config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_S_MASK; /* enable instruction tracing for corresponding exception level */ - val &= drvdata->s_ex_level; + val &= caps->s_ex_level; config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK); raw_spin_unlock(&drvdata->spinlock); return size; @@ -803,6 +817,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -812,7 +827,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, /* clear EXLEVEL_NS bits */ config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_NS_MASK; /* enable instruction tracing for corresponding exception level */ - val &= drvdata->ns_ex_level; + val &= caps->ns_ex_level; config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK); raw_spin_unlock(&drvdata->spinlock); return size; @@ -837,11 +852,12 @@ static ssize_t addr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->nr_addr_cmp * 2) + if (val >= caps->nr_addr_cmp * 2) return -EINVAL;
/* @@ -1060,6 +1076,7 @@ static ssize_t addr_start_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1067,7 +1084,7 @@ static ssize_t addr_start_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock); idx = config->addr_idx; - if (!drvdata->nr_addr_cmp) { + if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -1115,6 +1132,7 @@ static ssize_t addr_stop_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1122,7 +1140,7 @@ static ssize_t addr_stop_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock); idx = config->addr_idx; - if (!drvdata->nr_addr_cmp) { + if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -1167,6 +1185,7 @@ static ssize_t addr_ctxtype_store(struct device *dev, u8 idx; char str[10] = ""; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (strlen(buf) >= 10) @@ -1181,13 +1200,13 @@ static ssize_t addr_ctxtype_store(struct device *dev, config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_MASK; else if (!strcmp(str, "ctxid")) { /* 0b01 The trace unit performs a Context ID */ - if (drvdata->numcidc) { + if (caps->numcidc) { config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "vmid")) { /* 0b10 The trace unit performs a VMID */ - if (drvdata->numvmidc) { + if (caps->numvmidc) { config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID; } @@ -1196,9 +1215,9 @@ static ssize_t addr_ctxtype_store(struct device *dev, * 0b11 The trace unit performs a Context ID * comparison and a VMID */ - if (drvdata->numcidc) + if (caps->numcidc) config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID; - if (drvdata->numvmidc) + if (caps->numvmidc) config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID; } raw_spin_unlock(&drvdata->spinlock); @@ -1230,14 +1249,15 @@ static ssize_t addr_context_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1)) + if ((caps->numcidc <= 1) && (caps->numvmidc <= 1)) return -EINVAL; - if (val >= (drvdata->numcidc >= drvdata->numvmidc ? - drvdata->numcidc : drvdata->numvmidc)) + if (val >= (caps->numcidc >= caps->numvmidc ? + caps->numcidc : caps->numvmidc)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -1348,9 +1368,10 @@ static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nr_pe_cmp) + if (!caps->nr_pe_cmp) return -EINVAL; val = config->vipcssctlr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); @@ -1361,11 +1382,12 @@ static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!drvdata->nr_pe_cmp) + if (!caps->nr_pe_cmp) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -1393,13 +1415,14 @@ static ssize_t seq_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nr_seq_ctrls) + if (!caps->nr_seq_ctrls) return -ENOTSUPP; if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->nr_seq_ctrls) + if (val >= caps->nr_seq_ctrls) return -EINVAL;
/* @@ -1431,11 +1454,12 @@ static ssize_t seq_state_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->nrseqstate) + if (val >= caps->nrseqstate) return -EINVAL;
config->seq_state = val; @@ -1498,11 +1522,12 @@ static ssize_t seq_reset_event_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!(drvdata->nrseqstate)) + if (!(caps->nrseqstate)) return -EINVAL;
config->seq_rst = val & ETMv4_EVENT_MASK; @@ -1528,11 +1553,12 @@ static ssize_t cntr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->nr_cntr) + if (val >= caps->nr_cntr) return -EINVAL;
/* @@ -1678,6 +1704,7 @@ static ssize_t res_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1686,7 +1713,7 @@ static ssize_t res_idx_store(struct device *dev, * Resource selector pair 0 is always implemented and reserved, * namely an idx with 0 and 1 is illegal. */ - if ((val < 2) || (val >= 2 * drvdata->nr_resource)) + if ((val < 2) || (val >= 2 * caps->nr_resource)) return -EINVAL;
/* @@ -1760,11 +1787,12 @@ static ssize_t sshot_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->nr_ss_cmp) + if (val >= caps->nr_ss_cmp) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -1882,11 +1910,12 @@ static ssize_t ctxid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->numcidc) + if (val >= caps->numcidc) return -EINVAL;
/* @@ -1930,6 +1959,7 @@ static ssize_t ctxid_pid_store(struct device *dev, u8 idx; unsigned long pid; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
/* @@ -1949,7 +1979,7 @@ static ssize_t ctxid_pid_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */ - if (!drvdata->ctxid_size || !drvdata->numcidc) + if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; if (kstrtoul(buf, 16, &pid)) return -EINVAL; @@ -1991,6 +2021,7 @@ static ssize_t ctxid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; int nr_inputs;
@@ -2006,11 +2037,11 @@ static ssize_t ctxid_masks_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */ - if (!drvdata->ctxid_size || !drvdata->numcidc) + if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; /* one mask if <= 4 comparators, two for up to 8 */ nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); - if ((drvdata->numcidc > 4) && (nr_inputs != 2)) + if ((caps->numcidc > 4) && (nr_inputs != 2)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -2018,7 +2049,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to ctxid * comparator[0..3] */ - switch (drvdata->numcidc) { + switch (caps->numcidc) { case 0x1: /* COMP0, bits[7:0] */ config->ctxid_mask0 = val1 & 0xFF; @@ -2065,7 +2096,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * of ctxid comparator0 value (corresponding to byte 0) register. */ mask = config->ctxid_mask0; - for (i = 0; i < drvdata->numcidc; i++) { + for (i = 0; i < caps->numcidc; i++) { /* mask value of corresponding ctxid comparator */ maskbyte = mask & ETMv4_EVENT_MASK; /* @@ -2108,11 +2139,12 @@ static ssize_t vmid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >= drvdata->numvmidc) + if (val >= caps->numvmidc) return -EINVAL;
/* @@ -2153,6 +2185,7 @@ static ssize_t vmid_val_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
/* @@ -2166,7 +2199,7 @@ static ssize_t vmid_val_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */ - if (!drvdata->vmid_size || !drvdata->numvmidc) + if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL; @@ -2206,6 +2239,7 @@ static ssize_t vmid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; int nr_inputs;
@@ -2220,11 +2254,11 @@ static ssize_t vmid_masks_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */ - if (!drvdata->vmid_size || !drvdata->numvmidc) + if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; /* one mask if <= 4 comparators, two for up to 8 */ nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); - if ((drvdata->numvmidc > 4) && (nr_inputs != 2)) + if ((caps->numvmidc > 4) && (nr_inputs != 2)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -2233,7 +2267,7 @@ static ssize_t vmid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to vmid * comparator[0..3] */ - switch (drvdata->numvmidc) { + switch (caps->numvmidc) { case 0x1: /* COMP0, bits[7:0] */ config->vmid_mask0 = val1 & 0xFF; @@ -2281,7 +2315,7 @@ static ssize_t vmid_masks_store(struct device *dev, * of vmid comparator0 value (corresponding to byte 0) register. */ mask = config->vmid_mask0; - for (i = 0; i < drvdata->numvmidc; i++) { + for (i = 0; i < caps->numvmidc; i++) { /* mask value of corresponding vmid comparator */ maskbyte = mask & ETMv4_EVENT_MASK; /* diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index c33700711154d..ffde48b6b41b2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -813,6 +813,97 @@ enum etm_impdef_type { ETM4_IMPDEF_FEATURE_MAX, };
+/** + * struct etmv4_caps - specifics ETM capabilities + * @nr_pe: The number of processing entity available for tracing. + * @nr_pe_cmp: The number of processing entity comparator inputs that are + * available for tracing. + * @nr_addr_cmp:Number of pairs of address comparators available + * as found in ETMIDR4 0-3. + * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. + * @nr_ext_inp: Number of external input. + * @numcidc: Number of contextID comparators. + * @numextinsel: Number of external input selector resources. + * @numvmidc: Number of VMID comparators. + * @nrseqstate: The number of sequencer states that are implemented. + * @nr_seq_ctrls: The number of sequence state transition control registers. + * @nr_event: Indicates how many events the trace unit support. + * @nr_resource:The number of resource selection pairs available for tracing. + * @nr_ss_cmp: Number of single-shot comparator controls that are available. + * @trcid_size: Indicates the trace ID width. + * @ts_size: Global timestamp size field. + * @ctxid_size: Size of the context ID field to consider. + * @vmid_size: Size of the VM ID comparator to consider. + * @ccsize: Indicates the size of the cycle counter in bits. + * @ccitmin: minimum value that can be programmed in + * @s_ex_level: In secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ns_ex_level:In non-secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @q_support: Q element support characteristics. + * @os_lock_model: OSLock model. + * @instrp0: Tracing of load and store instructions + * as P0 elements is supported. + * @q_filt: Q element filtering support, if Q elements are supported. + * @trcbb: Indicates if the trace unit supports branch broadcast tracing. + * @trccond: If the trace unit supports conditional + * instruction tracing. + * @retstack: Indicates if the implementation supports a return stack. + * @trccci: Indicates if the trace unit supports cycle counting + * for instruction. + * @trc_error: Whether a trace unit can trace a system + * error exception. + * @syncpr: Indicates if an implementation has a fixed + * synchronization period. + * @stallctl: If functionality that prevents trace unit buffer overflows + * is available. + * @sysstall: Does the system support stall control of the PE? + * @nooverflow: Indicate if overflow prevention is supported. + * @atbtrig: If the implementation can support ATB triggers + * @lpoverride: If the implementation can support low-power state over. + * @skip_power_up: Indicates if an implementation can skip powering up + * the trace unit. + */ +struct etmv4_caps { + u8 nr_pe; + u8 nr_pe_cmp; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 numcidc; + u8 numextinsel; + u8 numvmidc; + u8 nrseqstate; + u8 nr_seq_ctrls; + u8 nr_event; + u8 nr_resource; + u8 nr_ss_cmp; + u8 trcid_size; + u8 ts_size; + u8 ctxid_size; + u8 vmid_size; + u8 ccsize; + u16 ccitmin; + u8 s_ex_level; + u8 ns_ex_level; + u8 q_support; + u8 os_lock_model; + bool instrp0 : 1; + bool q_filt : 1; + bool trcbb : 1; + bool trccond : 1; + bool retstack : 1; + bool trccci : 1; + bool trc_error : 1; + bool syncpr : 1; + bool stallctl : 1; + bool sysstall : 1; + bool nooverflow : 1; + bool atbtrig : 1; + bool lpoverride : 1; + bool skip_power_up : 1; +}; + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -820,8 +911,8 @@ enum etm_impdef_type { * @cfg: Controls the tracing options. * @eventctrl0: Controls the tracing of arbitrary events. * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. - * @stallctl: If functionality that prevents trace unit buffer overflows - * is available. + * @stall_ctrl: Enables trace unit functionality that prevents trace + * unit buffer overflows. * @ts_ctrl: Controls the insertion of global timestamps in the * trace streams. * @syncfreq: Controls how often trace synchronization requests occur. @@ -967,54 +1058,11 @@ struct etmv4_save_state { * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. * @arch: ETM architecture version. - * @nr_pe: The number of processing entity available for tracing. - * @nr_pe_cmp: The number of processing entity comparator inputs that are - * available for tracing. - * @nr_addr_cmp:Number of pairs of address comparators available - * as found in ETMIDR4 0-3. - * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. - * @nr_ext_inp: Number of external input. - * @numcidc: Number of contextID comparators. - * @numvmidc: Number of VMID comparators. - * @nrseqstate: The number of sequencer states that are implemented. - * @nr_seq_ctrls: The number of sequence state transition control registers. - * @nr_event: Indicates how many events the trace unit support. - * @nr_resource:The number of resource selection pairs available for tracing. - * @nr_ss_cmp: Number of single-shot comparator controls that are available. + * @caps: ETM capabilities. * @trcid: value of the current ID for this component. - * @trcid_size: Indicates the trace ID width. - * @ts_size: Global timestamp size field. - * @ctxid_size: Size of the context ID field to consider. - * @vmid_size: Size of the VM ID comparator to consider. - * @ccsize: Indicates the size of the cycle counter in bits. - * @ccitmin: minimum value that can be programmed in - * @s_ex_level: In secure state, indicates whether instruction tracing is - * supported for the corresponding Exception level. - * @ns_ex_level:In non-secure state, indicates whether instruction tracing is - * supported for the corresponding Exception level. * @sticky_enable: true if ETM base configuration has been done. * @boot_enable:True if we should start tracing at boot time. * @os_unlock: True if access to management registers is allowed. - * @instrp0: Tracing of load and store instructions - * as P0 elements is supported. - * @q_filt: Q element filtering support, if Q elements are supported. - * @trcbb: Indicates if the trace unit supports branch broadcast tracing. - * @trccond: If the trace unit supports conditional - * instruction tracing. - * @retstack: Indicates if the implementation supports a return stack. - * @trccci: Indicates if the trace unit supports cycle counting - * for instruction. - * @q_support: Q element support characteristics. - * @trc_error: Whether a trace unit can trace a system - * error exception. - * @syncpr: Indicates if an implementation has a fixed - * synchronization period. - * @stall_ctrl: Enables trace unit functionality that prevents trace - * unit buffer overflows. - * @sysstall: Does the system support stall control of the PE? - * @nooverflow: Indicate if overflow prevention is supported. - * @atbtrig: If the implementation can support ATB triggers - * @lpoverride: If the implementation can support low-power state over. * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that * allows tracing at all ELs. We don't want to compute this * at runtime, due to the additional setting of TRFCR_CX when @@ -1022,8 +1070,6 @@ struct etmv4_save_state { * @active_config: structure holding current applied configuration. * @config: structure holding sysfs mode configuration. * @save_state: State to be preserved across power loss - * @skip_power_up: Indicates if an implementation can skip powering up - * the trace unit. * @paused: Indicates if the trace unit is paused. * @arch_features: Bitmap of arch features of etmv4 devices. */ @@ -1035,47 +1081,11 @@ struct etmv4_drvdata { raw_spinlock_t spinlock; int cpu; u8 arch; - u8 nr_pe; - u8 nr_pe_cmp; - u8 nr_addr_cmp; - u8 nr_cntr; - u8 nr_ext_inp; - u8 numcidc; - u8 numextinsel; - u8 numvmidc; - u8 nrseqstate; - u8 nr_seq_ctrls; - u8 nr_event; - u8 nr_resource; - u8 nr_ss_cmp; + struct etmv4_caps caps; u8 trcid; - u8 trcid_size; - u8 ts_size; - u8 ctxid_size; - u8 vmid_size; - u8 ccsize; - u16 ccitmin; - u8 s_ex_level; - u8 ns_ex_level; - u8 q_support; - u8 os_lock_model; bool sticky_enable : 1; bool boot_enable : 1; bool os_unlock : 1; - bool instrp0 : 1; - bool q_filt : 1; - bool trcbb : 1; - bool trccond : 1; - bool retstack : 1; - bool trccci : 1; - bool trc_error : 1; - bool syncpr : 1; - bool stallctl : 1; - bool sysstall : 1; - bool nooverflow : 1; - bool atbtrig : 1; - bool lpoverride : 1; - bool skip_power_up : 1; bool paused : 1; u64 trfcr; struct etmv4_config active_config;
Reviewed-bY: Mike LEach mike.leach@arm.com
On 9/15/26 12:34, Yeoreum Yun wrote:
Introduce struct etm4_caps to describe ETMv4 capabilities and move capabilities information into it.
Reviewed-by: Leo Yan leo.yan@arm.com Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-core.c | 244 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 192 +++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 180 ++++++++------- 3 files changed, 336 insertions(+), 280 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2df7f592bb5cf..70a5c0b4fad1c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -92,8 +92,9 @@ static int etm4_probe_cpu(unsigned int cpu); */ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) {
- return (n < drvdata->nr_ss_cmp) &&
drvdata->nr_pe_cmp &&
- const struct etmv4_caps *caps = &drvdata->caps;
- return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && (drvdata->config.ss_status[n] & TRCSSCSRn_PC); }
@@ -164,17 +165,20 @@ static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa) {
- struct etmv4_caps *caps = &drvdata->caps; u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
- drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
- caps->os_lock_model = ETM_OSLSR_OSLM(oslsr); }
static void etm_write_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa, u32 val) {
- const struct etmv4_caps *caps = &drvdata->caps;
- val = !!val;
- switch (drvdata->os_lock_model) {
- switch (caps->os_lock_model) { case ETM_OSLOCK_PRESENT: etm4x_relaxed_write32(csa, val, TRCOSLAR); break;
@@ -183,7 +187,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drvdata, break; default: pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
smp_processor_id(), drvdata->os_lock_model);
smp_processor_id(), caps->os_lock_model);@@ -495,6 +499,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc;
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct device *etm_dev = &csdev->dev;
@@ -526,14 +531,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n");
- if (drvdata->nr_pe)
- if (caps->nr_pe) etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); /* nothing specific implemented */ etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- if (drvdata->stallctl)
- if (caps->stallctl) etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
@@ -543,18 +548,18 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
- if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++)
- for (i = 0; i < caps->nr_seq_ctrls; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
- if (drvdata->nrseqstate) {
- if (caps->nrseqstate) { etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); }
- if (drvdata->numextinsel)
- if (caps->numextinsel) etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
@@ -564,10 +569,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) * Resource selector pair 0 is always implemented and reserved. As * such start at 2. */
- for (i = 2; i < drvdata->nr_resource * 2; i++)
- for (i = 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- for (i = 0; i < caps->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) config->ss_status[i] &= ~TRCSSCSRn_STATUS;
@@ -576,23 +581,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); }
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- for (i = 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); }
- for (i = 0; i < drvdata->numcidc; i++)
- for (i = 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
- if (caps->numcidc > 4) etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
- for (i = 0; i < drvdata->numvmidc; i++)
- for (i = 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
- if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
- if (!drvdata->skip_power_up) {
- if (!caps->skip_power_up) { u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
/* @@ -689,19 +694,20 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, { int ctridx; int rselector;
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config;
/* No point in trying if we don't have at least one counter */
- if (!drvdata->nr_cntr)
- if (!caps->nr_cntr) return -EINVAL;
/* Find a counter that hasn't been initialised */
- for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
- for (ctridx = 0; ctridx < caps->nr_cntr; ctridx++) if (config->cntr_val[ctridx] == 0) break;
/* All the counters have been configured already, bail out */
- if (ctridx == drvdata->nr_cntr) {
- if (ctridx == caps->nr_cntr) { pr_debug("%s: no available counter found\n", __func__); return -ENOSPC; }
@@ -717,11 +723,11 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, * ETMIDR4 gives the number of resource selector _pairs_, hence multiply * by 2. */
- for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
- for (rselector = 2; rselector < caps->nr_resource * 2; rselector++) if (!config->res_ctrl[rselector]) break;
- if (rselector == drvdata->nr_resource * 2) {
- if (rselector == caps->nr_resource * 2) { pr_debug("%s: no available resource selector found\n", __func__); return -ENOSPC;
@@ -772,6 +778,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, { int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct perf_event_attr max_timestamp = { .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
@@ -810,8 +817,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev, cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
if (cc_threshold < drvdata->ccitmin)cc_threshold = drvdata->ccitmin;
if (cc_threshold < caps->ccitmin)cc_threshold = caps->ccitmin;@@ -859,13 +866,13 @@ static int etm4_parse_event_config(struct coresight_device *csdev, } /* return stack - enable if selected and supported */
- if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
- if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack) /* bit[12], Return stack enable bit */ config->cfg |= TRCCONFIGR_RS;
/* branch broadcast - enable if selected and supported */ if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
if (!drvdata->trcbb) {
if (!caps->trcbb) { /* * Missing BB support could cause silent decode errors * so fail to open if it's not supported.@@ -1054,6 +1061,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control;
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access;
@@ -1062,7 +1070,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata);
- if (!drvdata->skip_power_up) {
- if (!caps->skip_power_up) { /* power can be removed from the trace unit now */ control = etm4x_relaxed_read32(csa, TRCPDCR); control &= ~TRCPDCR_PU;
@@ -1072,13 +1080,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) etm4_disable_trace_unit(drvdata); /* read the status of the single shot comparators */
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- for (i = 0; i < caps->nr_ss_cmp; i++) { config->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); }
/* read back the current counter values */
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { config->cntr_val[i] = etm4x_relaxed_read32(csa, TRCCNTVRn(i)); }
@@ -1141,6 +1149,7 @@ static int etm4_disable_perf(struct coresight_device *csdev, static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; const struct etmv4_config *active_config = &drvdata->active_config; int i;
@@ -1156,10 +1165,10 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) * Userspace may read ss_status and cntr_val through sysfs after * the sysfs-session has been disabled. */
- for (i = 0; i < drvdata->nr_ss_cmp; i++)
- for (i = 0; i < caps->nr_ss_cmp; i++) config->ss_status[i] = active_config->ss_status[i];
- for (i = 0; i < drvdata->nr_cntr; i++)
- for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); @@ -1373,7 +1382,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] = { {}, }; -static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) +static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps) { /* * Erratum affected cpus will read 256 as the minimum @@ -1383,8 +1392,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) * this problem. */ if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) {
if (drvdata->ccitmin == 256)drvdata->ccitmin = 4;
if (caps->ccitmin == 256)caps->ccitmin = 4;@@ -1397,11 +1406,13 @@ static void etm4_init_arch_data(void *info) u32 etmidr5; struct etm4_init_arg *init_arg = info; struct etmv4_drvdata *drvdata;
- struct etmv4_caps *caps; struct csdev_access *csa; struct device *dev = init_arg->dev; int i;
drvdata = dev_get_drvdata(init_arg->dev);
- caps = &drvdata->caps; csa = init_arg->csa;
/* @@ -1414,7 +1425,7 @@ static void etm4_init_arch_data(void *info) if (!csa->io_mem || fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
drvdata->skip_power_up = true;
caps->skip_power_up = true;/* Detect the support for OS Lock before we actually use it */ etm_detect_os_lock(drvdata, csa); @@ -1429,71 +1440,71 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */
- drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
- caps->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); /* TRCBB, bit[5] Branch broadcast tracing support bit */
- drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
- caps->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); /* TRCCOND, bit[6] Conditional instruction tracing support bit */
- drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
- caps->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); /* TRCCCI, bit[7] Cycle counting instruction bit */
- drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
- caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */
- drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
- caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); /* NUMEVENT, bits[11:10] Number of events field */
- drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
- caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); /* QSUPP, bits[16:15] Q element support field */
- drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
- if (drvdata->q_support)
drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
- caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
- if (caps->q_support)
caps->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
- drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
- caps->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
/* maximum size of resources */ etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */
- drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
- caps->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); /* VMIDSIZE, bits[14:10] Indicates the VMID size */
- drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
- caps->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
- drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
- caps->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
- drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
- etm4_fixup_wrong_ccitmin(drvdata);
- caps->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
- etm4_fixup_wrong_ccitmin(caps);
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
- drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = drvdata->s_ex_level;
- caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
- drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
- caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /*
*/
- TRCERR, bit[24] whether a trace unit can trace a
- system error exception.
- drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
- caps->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
- drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
- caps->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); /* STALLCTL, bit[26] is stall control implemented? */
- drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
- caps->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); /* SYSSTALL, bit[27] implementation can support stall control? */
- drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
- caps->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); /*
*/
- NUMPROC - the number of PEs available for tracing, 5bits
= TRCIDR3.bits[13:12]bits[30:28]- bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
- bits[3:0] = TRCIDR3.bits[30:28]
- drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
- caps->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
- drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
- caps->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
/* number of resources trace unit supports */ etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
- drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
- caps->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
- drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
- caps->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); /*
- NUMRSPAIR, bits[19:16]
- The number of resource pairs conveyed by the HW starts at 0, i.e a
@@ -1504,43 +1515,43 @@ static void etm4_init_arch_data(void *info) * the default TRUE and FALSE resource selectors are omitted. * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */
- drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
- if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
drvdata->nr_resource += 1;
- caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
- if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0))
caps->nr_resource += 1;*/
- NUMSSCC, bits[23:20] the number of single-shot
- comparator control for tracing. Read any status regs as these
- also contain RO capability data.
- drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
- for (i = 0; i < caps->nr_ss_cmp; i++) { drvdata->config.ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
- drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
- caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
- drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
- caps->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */
- drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
- drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
- caps->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
- caps->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
- drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
- caps->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); /* ATBTRIG, bit[22] implementation can support ATB triggers? */
- drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
- caps->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); /*
*/
- LPOVERRIDE, bit[23] implementation supports
- low-power state override
- drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
- caps->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power_up); /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
- drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
- if (drvdata->nrseqstate)
drvdata->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS;
- caps->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
- if (caps->nrseqstate)
caps->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS;
- drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
- caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
coresight_clear_self_claim_tag_unlocked(csa); etm4_cs_lock(drvdata, csa); @@ -1716,7 +1727,7 @@ static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) * nr_addr_cmp holds the number of comparator _pair_, so time 2 * for the total number of comparators. */
- nr_comparator = drvdata->nr_addr_cmp * 2;
- nr_comparator = drvdata->caps.nr_addr_cmp * 2;
/* Go through the tally of comparators looking for a free one. */ while (index < nr_comparator) { @@ -1873,6 +1884,7 @@ static int etm4_cpu_save(struct coresight_device *csdev) { int i, ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_save_state *state; struct csdev_access *csa; struct device *etm_dev;
@@ -1905,57 +1917,56 @@ static int etm4_cpu_save(struct coresight_device *csdev) state = drvdata->save_state;
- if (drvdata->nr_pe)
- if (caps->nr_pe) state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- if (drvdata->stallctl)
- if (caps->stallctl) state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
- if (drvdata->q_filt)
- if (caps->q_filt) state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
state->trcvictlr = etm4x_read32(csa, TRCVICTLR); state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
- if (caps->nr_pe_cmp) state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++)
- for (i = 0; i < caps->nr_seq_ctrls; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
- if (drvdata->nrseqstate) {
- if (caps->nrseqstate) { state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); }
- if (drvdata->numextinsel)
- if (caps->numextinsel) state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); }
/* Resource selector pair 0 is reserved */
- for (i = 2; i < drvdata->nr_resource * 2; i++)
- for (i = 2; i < caps->nr_resource * 2; i++) state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- for (i = 0; i < caps->nr_ss_cmp; i++) { state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); }
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- for (i = 0; i < caps->nr_addr_cmp * 2; i++) { state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); }
@@ -1967,23 +1978,23 @@ static int etm4_cpu_save(struct coresight_device *csdev) * unit") of ARM IHI 0064D. */
- for (i = 0; i < drvdata->numcidc; i++)
- for (i = 0; i < caps->numcidc; i++) state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++)
- for (i = 0; i < caps->numvmidc; i++) state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
- if (caps->numcidc > 4) state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
- if (caps->numvmidc > 4) state->trcvmidcctlr1 = etm4x_read32(csa, TRCVMIDCCTLR1);
state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
- if (!drvdata->skip_power_up)
- if (!caps->skip_power_up) state->trcpdcr = etm4x_read32(csa, TRCPDCR);
/* wait for TRCSTATR.IDLE to go up */ @@ -2000,7 +2011,7 @@ static int etm4_cpu_save(struct coresight_device *csdev) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */
- if (!drvdata->skip_power_up)
- if (!caps->skip_power_up) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out:
@@ -2012,83 +2023,84 @@ static void etm4_cpu_restore(struct coresight_device *csdev) { int i; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_save_state *state = drvdata->save_state; struct csdev_access *csa = &drvdata->csdev->access;
etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (drvdata->nr_pe)
- if (caps->nr_pe) etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- if (drvdata->stallctl)
- if (caps->stallctl) etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
- if (drvdata->q_filt)
- if (caps->q_filt) etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
- if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nr_seq_ctrls; i++)
- for (i = 0; i < caps->nr_seq_ctrls; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
- if (drvdata->nrseqstate) {
- if (caps->nrseqstate) { etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); }
- if (drvdata->numextinsel)
- if (caps->numextinsel) etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); }
/* Resource selector pair 0 is reserved */
- for (i = 2; i < drvdata->nr_resource * 2; i++)
- for (i = 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- for (i = 0; i < caps->nr_ss_cmp; i++) { etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); }
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- for (i = 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); }
- for (i = 0; i < drvdata->numcidc; i++)
- for (i = 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++)
- for (i = 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
- if (caps->numcidc > 4) etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
- if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, state->trcvmidcctlr1, TRCVMIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (!drvdata->skip_power_up)
- if (!caps->skip_power_up) etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
/* diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index f64c0acebc701..f6d053f73264c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_pe_cmp;
- val = caps->nr_pe_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_pe_cmp);
@@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp;
- val = caps->nr_addr_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp);
@@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr;
- val = caps->nr_cntr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr);
@@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ext_inp;
- val = caps->nr_ext_inp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ext_inp);
@@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numcidc;
- val = caps->numcidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numcidc);
@@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numvmidc;
- val = caps->numvmidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numvmidc);
@@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nrseqstate;
- val = caps->nrseqstate; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nrseqstate);
@@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_resource;
- val = caps->nr_resource; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_resource);
@@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ss_cmp;
- val = caps->nr_ss_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ss_cmp);
@@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev, int i; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev, config->stall_ctrl = 0x0; /* Reset trace synchronization period to 2^8 = 256 bytes*/
- if (drvdata->syncpr == false)
- if (!caps->syncpr) config->syncfreq = 0x8;
/* @@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev, * each trace run. */ config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
- if (drvdata->nr_addr_cmp > 0) {
- if (caps->nr_addr_cmp > 0) { config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
@@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev, config->vipcssctlr = 0x0; /* Disable seq events */
- for (i = 0; i < drvdata->nr_seq_ctrls; i++)
- for (i = 0; i < caps->nr_seq_ctrls; i++) config->seq_ctrl[i] = 0x0; config->seq_rst = 0x0; config->seq_state = 0x0;
@@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev, config->ext_inp = 0x0; config->cntr_idx = 0x0;
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { config->cntrldvr[i] = 0x0; config->cntr_ctrl[i] = 0x0; config->cntr_val[i] = 0x0; }
config->res_idx = 0x0;
- for (i = 2; i < 2 * drvdata->nr_resource; i++)
- for (i = 2; i < 2 * caps->nr_resource; i++) config->res_ctrl[i] = 0x0;
config->ss_idx = 0x0;
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
- for (i = 0; i < caps->nr_ss_cmp; i++) { config->ss_ctrl[i] = 0x0; config->ss_pe_cmp[i] = 0x0; }
config->addr_idx = 0x0;
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
- for (i = 0; i < caps->nr_addr_cmp * 2; i++) { config->addr_val[i] = 0x0; config->addr_acc[i] = 0x0; config->addr_type[i] = ETM_ADDR_TYPE_NONE; }
config->ctxid_idx = 0x0;
- for (i = 0; i < drvdata->numcidc; i++)
- for (i = 0; i < caps->numcidc; i++) config->ctxid_pid[i] = 0x0;
config->ctxid_mask0 = 0x0; config->ctxid_mask1 = 0x0; config->vmid_idx = 0x0;
- for (i = 0; i < drvdata->numvmidc; i++)
- for (i = 0; i < caps->numvmidc; i++) config->vmid_val[i] = 0x0; config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0;
@@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev, { unsigned long val, mode; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); config->mode = val & ETMv4_MODE_ALL;
- if (drvdata->instrp0 == true) {
- if (caps->instrp0) { /* start by clearing instruction P0 field */ config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE; if (config->mode & ETM_MODE_LOAD)
@@ -323,45 +334,44 @@ static ssize_t mode_store(struct device *dev, } /* bit[3], Branch broadcast mode */
- if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
- if ((config->mode & ETM_MODE_BB) && (caps->trcbb)) config->cfg |= TRCCONFIGR_BB; else config->cfg &= ~TRCCONFIGR_BB;
/* bit[4], Cycle counting instruction trace bit */ if ((config->mode & ETMv4_MODE_CYCACC) &&
(drvdata->trccci == true))
(caps->trccci == true))/* bit[6], Context ID tracing bit */
- if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
- if ((config->mode & ETMv4_MODE_CTXID) && (caps->ctxid_size)) config->cfg |= TRCCONFIGR_CID; else config->cfg &= ~TRCCONFIGR_CID;
- if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
- if ((config->mode & ETM_MODE_VMID) && (caps->vmid_size)) config->cfg |= TRCCONFIGR_VMID; else config->cfg &= ~TRCCONFIGR_VMID;
/* bits[10:8], Conditional instruction tracing bit */ mode = ETM_MODE_COND(config->mode);
- if (drvdata->trccond == true) {
- if (caps->trccond) { config->cfg &= ~TRCCONFIGR_COND_MASK; config->cfg |= mode << __bf_shf(TRCCONFIGR_COND_MASK); }
/* bit[11], Global timestamp tracing bit */
- if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
- if ((config->mode & ETMv4_MODE_TIMESTAMP) && (caps->ts_size)) config->cfg |= TRCCONFIGR_TS; else config->cfg &= ~TRCCONFIGR_TS;
/* bit[12], Return stack enable bit */
- if ((config->mode & ETM_MODE_RETURNSTACK) &&
(drvdata->retstack == true))
- if ((config->mode & ETM_MODE_RETURNSTACK) && (caps->retstack)) config->cfg |= TRCCONFIGR_RS; else config->cfg &= ~TRCCONFIGR_RS;
@@ -375,31 +385,29 @@ static ssize_t mode_store(struct device *dev, * Always set the low bit for any requested mode. Valid combos are * 0b00, 0b01 and 0b11. */
- if (mode && drvdata->q_support)
- if (mode && caps->q_support) config->cfg |= TRCCONFIGR_QE_W_COUNTS; /*
*/
- if supported, Q elements with and without instruction
- counts are enabled
- if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
- if ((mode & BIT(1)) && (caps->q_support & BIT(1))) config->cfg |= TRCCONFIGR_QE_WO_COUNTS;
/* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
- if ((config->mode & ETM_MODE_ATB_TRIGGER) &&
(drvdata->atbtrig == true))
- if ((config->mode & ETM_MODE_ATB_TRIGGER) && (caps->atbtrig)) config->eventctrl1 |= TRCEVENTCTL1R_ATB; else config->eventctrl1 &= ~TRCEVENTCTL1R_ATB;
/* bit[12], Low-power state behavior override bit */
- if ((config->mode & ETM_MODE_LPOVERRIDE) &&
(drvdata->lpoverride == true))
- if ((config->mode & ETM_MODE_LPOVERRIDE) && (caps->lpoverride)) config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE; else config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE;
/* bit[8], Instruction stall bit */
- if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
- if ((config->mode & ETM_MODE_ISTALL_EN) && (caps->stallctl)) config->stall_ctrl |= TRCSTALLCTLR_ISTALL; else config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL;
@@ -411,8 +419,7 @@ static ssize_t mode_store(struct device *dev, config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY; /* bit[13], Trace overflow prevention bit */
- if ((config->mode & ETM_MODE_NOOVERFLOW) &&
(drvdata->nooverflow == true))
- if ((config->mode & ETM_MODE_NOOVERFLOW) && (caps->nooverflow)) config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW; else config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW;
@@ -430,8 +437,7 @@ static ssize_t mode_store(struct device *dev, config->vinst_ctrl &= ~TRCVICTLR_TRCRESET; /* bit[11], Whether a trace unit must trace a system error exception */
- if ((config->mode & ETM_MODE_TRACE_ERR) &&
(drvdata->trc_error == true))
- if ((config->mode & ETM_MODE_TRACE_ERR) && (caps->trc_error)) config->vinst_ctrl |= TRCVICTLR_TRCERR; else config->vinst_ctrl &= ~TRCVICTLR_TRCERR;
@@ -463,13 +469,14 @@ static ssize_t pe_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; raw_spin_lock(&drvdata->spinlock);
- if (val > drvdata->nr_pe) {
- if (val > caps->nr_pe) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; }
@@ -498,13 +505,14 @@ static ssize_t event_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL; raw_spin_lock(&drvdata->spinlock);
- switch (drvdata->nr_event) {
- switch (caps->nr_event) { case 0x0: /* EVENT0, bits[7:0] */ config->eventctrl0 = val & 0xFF;
@@ -547,6 +555,7 @@ static ssize_t event_instren_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -555,7 +564,7 @@ static ssize_t event_instren_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); /* start by clearing all instruction event enable bits */ config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK;
- switch (drvdata->nr_event) {
- switch (caps->nr_event) { case 0x0: /* generate Event element for event 1 */ config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1;
@@ -603,11 +612,12 @@ static ssize_t event_ts_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (!drvdata->ts_size)
- if (!caps->ts_size) return -EINVAL;
config->ts_ctrl = val & ETMv4_EVENT_MASK; @@ -633,11 +643,12 @@ static ssize_t syncfreq_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (drvdata->syncpr == true)
- if (caps->syncpr) return -EINVAL;
config->syncfreq = val & ETMv4_SYNC_MASK; @@ -663,6 +674,7 @@ static ssize_t cyc_threshold_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -670,7 +682,7 @@ static ssize_t cyc_threshold_store(struct device *dev, /* mask off max threshold before checking min value */ val &= ETM_CYC_THRESHOLD_MASK;
- if (val < drvdata->ccitmin)
- if (val < caps->ccitmin) return -EINVAL;
config->ccctlr = val; @@ -696,13 +708,14 @@ static ssize_t bb_ctrl_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (drvdata->trcbb == false)
- if (!caps->trcbb) return -EINVAL;
- if (!drvdata->nr_addr_cmp)
- if (!caps->nr_addr_cmp) return -EINVAL;
/* @@ -768,6 +781,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -777,7 +791,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, /* clear all EXLEVEL_S bits */ config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_S_MASK; /* enable instruction tracing for corresponding exception level */
- val &= drvdata->s_ex_level;
- val &= caps->s_ex_level; config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK); raw_spin_unlock(&drvdata->spinlock); return size;
@@ -803,6 +817,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -812,7 +827,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, /* clear EXLEVEL_NS bits */ config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_NS_MASK; /* enable instruction tracing for corresponding exception level */
- val &= drvdata->ns_ex_level;
- val &= caps->ns_ex_level; config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK); raw_spin_unlock(&drvdata->spinlock); return size;
@@ -837,11 +852,12 @@ static ssize_t addr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->nr_addr_cmp * 2)
- if (val >= caps->nr_addr_cmp * 2) return -EINVAL;
/* @@ -1060,6 +1076,7 @@ static ssize_t addr_start_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1067,7 +1084,7 @@ static ssize_t addr_start_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->addr_idx;
- if (!drvdata->nr_addr_cmp) {
- if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; }
@@ -1115,6 +1132,7 @@ static ssize_t addr_stop_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1122,7 +1140,7 @@ static ssize_t addr_stop_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->addr_idx;
- if (!drvdata->nr_addr_cmp) {
- if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; }
@@ -1167,6 +1185,7 @@ static ssize_t addr_ctxtype_store(struct device *dev, u8 idx; char str[10] = ""; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (strlen(buf) >= 10) @@ -1181,13 +1200,13 @@ static ssize_t addr_ctxtype_store(struct device *dev, config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_MASK; else if (!strcmp(str, "ctxid")) { /* 0b01 The trace unit performs a Context ID */
if (drvdata->numcidc) {
if (caps->numcidc) { config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_VMID;
if (drvdata->numvmidc) {
if (caps->numvmidc) { config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;@@ -1196,9 +1215,9 @@ static ssize_t addr_ctxtype_store(struct device *dev, * 0b11 The trace unit performs a Context ID * comparison and a VMID */
if (drvdata->numcidc)
if (caps->numcidc) config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID;
if (drvdata->numvmidc)
if (caps->numvmidc) config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;@@ -1230,14 +1249,15 @@ static ssize_t addr_context_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1))
- if ((caps->numcidc <= 1) && (caps->numvmidc <= 1)) return -EINVAL;
- if (val >= (drvdata->numcidc >= drvdata->numvmidc ?
drvdata->numcidc : drvdata->numvmidc))
- if (val >= (caps->numcidc >= caps->numvmidc ?
caps->numcidc : caps->numvmidc))raw_spin_lock(&drvdata->spinlock); @@ -1348,9 +1368,10 @@ static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nr_pe_cmp)
- if (!caps->nr_pe_cmp) return -EINVAL; val = config->vipcssctlr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
@@ -1361,11 +1382,12 @@ static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (!drvdata->nr_pe_cmp)
- if (!caps->nr_pe_cmp) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -1393,13 +1415,14 @@ static ssize_t seq_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nr_seq_ctrls)
- if (!caps->nr_seq_ctrls) return -ENOTSUPP; if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->nr_seq_ctrls)
- if (val >= caps->nr_seq_ctrls) return -EINVAL;
/* @@ -1431,11 +1454,12 @@ static ssize_t seq_state_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->nrseqstate)
- if (val >= caps->nrseqstate) return -EINVAL;
config->seq_state = val; @@ -1498,11 +1522,12 @@ static ssize_t seq_reset_event_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (!(drvdata->nrseqstate))
- if (!(caps->nrseqstate)) return -EINVAL;
config->seq_rst = val & ETMv4_EVENT_MASK; @@ -1528,11 +1553,12 @@ static ssize_t cntr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->nr_cntr)
- if (val >= caps->nr_cntr) return -EINVAL;
/* @@ -1678,6 +1704,7 @@ static ssize_t res_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) @@ -1686,7 +1713,7 @@ static ssize_t res_idx_store(struct device *dev, * Resource selector pair 0 is always implemented and reserved, * namely an idx with 0 and 1 is illegal. */
- if ((val < 2) || (val >= 2 * drvdata->nr_resource))
- if ((val < 2) || (val >= 2 * caps->nr_resource)) return -EINVAL;
/* @@ -1760,11 +1787,12 @@ static ssize_t sshot_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->nr_ss_cmp)
- if (val >= caps->nr_ss_cmp) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -1882,11 +1910,12 @@ static ssize_t ctxid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->numcidc)
- if (val >= caps->numcidc) return -EINVAL;
/* @@ -1930,6 +1959,7 @@ static ssize_t ctxid_pid_store(struct device *dev, u8 idx; unsigned long pid; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
/* @@ -1949,7 +1979,7 @@ static ssize_t ctxid_pid_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */
- if (!drvdata->ctxid_size || !drvdata->numcidc)
- if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; if (kstrtoul(buf, 16, &pid)) return -EINVAL;
@@ -1991,6 +2021,7 @@ static ssize_t ctxid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; int nr_inputs;
@@ -2006,11 +2037,11 @@ static ssize_t ctxid_masks_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */
- if (!drvdata->ctxid_size || !drvdata->numcidc)
- if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; /* one mask if <= 4 comparators, two for up to 8 */ nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
- if ((drvdata->numcidc > 4) && (nr_inputs != 2))
- if ((caps->numcidc > 4) && (nr_inputs != 2)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -2018,7 +2049,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to ctxid * comparator[0..3] */
- switch (drvdata->numcidc) {
- switch (caps->numcidc) { case 0x1: /* COMP0, bits[7:0] */ config->ctxid_mask0 = val1 & 0xFF;
@@ -2065,7 +2096,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * of ctxid comparator0 value (corresponding to byte 0) register. */ mask = config->ctxid_mask0;
- for (i = 0; i < drvdata->numcidc; i++) {
- for (i = 0; i < caps->numcidc; i++) { /* mask value of corresponding ctxid comparator */ maskbyte = mask & ETMv4_EVENT_MASK; /*
@@ -2108,11 +2139,12 @@ static ssize_t vmid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val)) return -EINVAL;
- if (val >= drvdata->numvmidc)
- if (val >= caps->numvmidc) return -EINVAL;
/* @@ -2153,6 +2185,7 @@ static ssize_t vmid_val_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config;
/* @@ -2166,7 +2199,7 @@ static ssize_t vmid_val_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */
- if (!drvdata->vmid_size || !drvdata->numvmidc)
- if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL;
@@ -2206,6 +2239,7 @@ static ssize_t vmid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->config; int nr_inputs;
@@ -2220,11 +2254,11 @@ static ssize_t vmid_masks_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */
- if (!drvdata->vmid_size || !drvdata->numvmidc)
- if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; /* one mask if <= 4 comparators, two for up to 8 */ nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
- if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
- if ((caps->numvmidc > 4) && (nr_inputs != 2)) return -EINVAL;
raw_spin_lock(&drvdata->spinlock); @@ -2233,7 +2267,7 @@ static ssize_t vmid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to vmid * comparator[0..3] */
- switch (drvdata->numvmidc) {
- switch (caps->numvmidc) { case 0x1: /* COMP0, bits[7:0] */ config->vmid_mask0 = val1 & 0xFF;
@@ -2281,7 +2315,7 @@ static ssize_t vmid_masks_store(struct device *dev, * of vmid comparator0 value (corresponding to byte 0) register. */ mask = config->vmid_mask0;
- for (i = 0; i < drvdata->numvmidc; i++) {
- for (i = 0; i < caps->numvmidc; i++) { /* mask value of corresponding vmid comparator */ maskbyte = mask & ETMv4_EVENT_MASK; /*
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index c33700711154d..ffde48b6b41b2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -813,6 +813,97 @@ enum etm_impdef_type { ETM4_IMPDEF_FEATURE_MAX, }; +/**
- struct etmv4_caps - specifics ETM capabilities
- @nr_pe: The number of processing entity available for tracing.
- @nr_pe_cmp: The number of processing entity comparator inputs that are
available for tracing.
- @nr_addr_cmp:Number of pairs of address comparators available
as found in ETMIDR4 0-3.
- @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
- @nr_ext_inp: Number of external input.
- @numcidc: Number of contextID comparators.
- @numextinsel: Number of external input selector resources.
- @numvmidc: Number of VMID comparators.
- @nrseqstate: The number of sequencer states that are implemented.
- @nr_seq_ctrls: The number of sequence state transition control registers.
- @nr_event: Indicates how many events the trace unit support.
- @nr_resource:The number of resource selection pairs available for tracing.
- @nr_ss_cmp: Number of single-shot comparator controls that are available.
- @trcid_size: Indicates the trace ID width.
- @ts_size: Global timestamp size field.
- @ctxid_size: Size of the context ID field to consider.
- @vmid_size: Size of the VM ID comparator to consider.
- @ccsize: Indicates the size of the cycle counter in bits.
- @ccitmin: minimum value that can be programmed in
- @s_ex_level: In secure state, indicates whether instruction tracing is
supported for the corresponding Exception level.
- @ns_ex_level:In non-secure state, indicates whether instruction tracing is
supported for the corresponding Exception level.
- @q_support: Q element support characteristics.
- @os_lock_model: OSLock model.
- @instrp0: Tracing of load and store instructions
as P0 elements is supported.
- @q_filt: Q element filtering support, if Q elements are supported.
- @trcbb: Indicates if the trace unit supports branch broadcast tracing.
- @trccond: If the trace unit supports conditional
instruction tracing.
- @retstack: Indicates if the implementation supports a return stack.
- @trccci: Indicates if the trace unit supports cycle counting
for instruction.
- @trc_error: Whether a trace unit can trace a system
error exception.
- @syncpr: Indicates if an implementation has a fixed
synchronization period.
- @stallctl: If functionality that prevents trace unit buffer overflows
is available.
- @sysstall: Does the system support stall control of the PE?
- @nooverflow: Indicate if overflow prevention is supported.
- @atbtrig: If the implementation can support ATB triggers
- @lpoverride: If the implementation can support low-power state over.
- @skip_power_up: Indicates if an implementation can skip powering up
the trace unit.- */
+struct etmv4_caps {
- u8 nr_pe;
- u8 nr_pe_cmp;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 numcidc;
- u8 numextinsel;
- u8 numvmidc;
- u8 nrseqstate;
- u8 nr_seq_ctrls;
- u8 nr_event;
- u8 nr_resource;
- u8 nr_ss_cmp;
- u8 trcid_size;
- u8 ts_size;
- u8 ctxid_size;
- u8 vmid_size;
- u8 ccsize;
- u16 ccitmin;
- u8 s_ex_level;
- u8 ns_ex_level;
- u8 q_support;
- u8 os_lock_model;
- bool instrp0 : 1;
- bool q_filt : 1;
- bool trcbb : 1;
- bool trccond : 1;
- bool retstack : 1;
- bool trccci : 1;
- bool trc_error : 1;
- bool syncpr : 1;
- bool stallctl : 1;
- bool sysstall : 1;
- bool nooverflow : 1;
- bool atbtrig : 1;
- bool lpoverride : 1;
- bool skip_power_up : 1;
+};
- /**
- struct etmv4_config - configuration information related to an ETMv4
- @mode: Controls various modes supported by this ETM.
@@ -820,8 +911,8 @@ enum etm_impdef_type {
- @cfg: Controls the tracing options.
- @eventctrl0: Controls the tracing of arbitrary events.
- @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
- @stallctl: If functionality that prevents trace unit buffer overflows
is available.
- @stall_ctrl: Enables trace unit functionality that prevents trace
unit buffer overflows.- @ts_ctrl: Controls the insertion of global timestamps in the
trace streams.- @syncfreq: Controls how often trace synchronization requests occur.
@@ -967,54 +1058,11 @@ struct etmv4_save_state {
- @mode: This tracer's mode, i.e sysFS, Perf or disabled.
- @cpu: The cpu this component is affined to.
- @arch: ETM architecture version.
- @nr_pe: The number of processing entity available for tracing.
- @nr_pe_cmp: The number of processing entity comparator inputs that are
available for tracing.
- @nr_addr_cmp:Number of pairs of address comparators available
as found in ETMIDR4 0-3.
- @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
- @nr_ext_inp: Number of external input.
- @numcidc: Number of contextID comparators.
- @numvmidc: Number of VMID comparators.
- @nrseqstate: The number of sequencer states that are implemented.
- @nr_seq_ctrls: The number of sequence state transition control registers.
- @nr_event: Indicates how many events the trace unit support.
- @nr_resource:The number of resource selection pairs available for tracing.
- @nr_ss_cmp: Number of single-shot comparator controls that are available.
- @caps: ETM capabilities.
- @trcid: value of the current ID for this component.
- @trcid_size: Indicates the trace ID width.
- @ts_size: Global timestamp size field.
- @ctxid_size: Size of the context ID field to consider.
- @vmid_size: Size of the VM ID comparator to consider.
- @ccsize: Indicates the size of the cycle counter in bits.
- @ccitmin: minimum value that can be programmed in
- @s_ex_level: In secure state, indicates whether instruction tracing is
supported for the corresponding Exception level.
- @ns_ex_level:In non-secure state, indicates whether instruction tracing is
supported for the corresponding Exception level.- @sticky_enable: true if ETM base configuration has been done.
- @boot_enable:True if we should start tracing at boot time.
- @os_unlock: True if access to management registers is allowed.
- @instrp0: Tracing of load and store instructions
as P0 elements is supported.
- @q_filt: Q element filtering support, if Q elements are supported.
- @trcbb: Indicates if the trace unit supports branch broadcast tracing.
- @trccond: If the trace unit supports conditional
instruction tracing.
- @retstack: Indicates if the implementation supports a return stack.
- @trccci: Indicates if the trace unit supports cycle counting
for instruction.
- @q_support: Q element support characteristics.
- @trc_error: Whether a trace unit can trace a system
error exception.
- @syncpr: Indicates if an implementation has a fixed
synchronization period.
- @stall_ctrl: Enables trace unit functionality that prevents trace
unit buffer overflows.
- @sysstall: Does the system support stall control of the PE?
- @nooverflow: Indicate if overflow prevention is supported.
- @atbtrig: If the implementation can support ATB triggers
- @lpoverride: If the implementation can support low-power state over.
- @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
allows tracing at all ELs. We don't want to compute thisat runtime, due to the additional setting of TRFCR_CX when@@ -1022,8 +1070,6 @@ struct etmv4_save_state {
- @active_config: structure holding current applied configuration.
- @config: structure holding sysfs mode configuration.
- @save_state: State to be preserved across power loss
- @skip_power_up: Indicates if an implementation can skip powering up
*/
the trace unit.- @paused: Indicates if the trace unit is paused.
- @arch_features: Bitmap of arch features of etmv4 devices.
@@ -1035,47 +1081,11 @@ struct etmv4_drvdata { raw_spinlock_t spinlock; int cpu; u8 arch;
- u8 nr_pe;
- u8 nr_pe_cmp;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 numcidc;
- u8 numextinsel;
- u8 numvmidc;
- u8 nrseqstate;
- u8 nr_seq_ctrls;
- u8 nr_event;
- u8 nr_resource;
- u8 nr_ss_cmp;
- struct etmv4_caps caps; u8 trcid;
- u8 trcid_size;
- u8 ts_size;
- u8 ctxid_size;
- u8 vmid_size;
- u8 ccsize;
- u16 ccitmin;
- u8 s_ex_level;
- u8 ns_ex_level;
- u8 q_support;
- u8 os_lock_model; bool sticky_enable : 1; bool boot_enable : 1; bool os_unlock : 1;
- bool instrp0 : 1;
- bool q_filt : 1;
- bool trcbb : 1;
- bool trccond : 1;
- bool retstack : 1;
- bool trccci : 1;
- bool trc_error : 1;
- bool syncpr : 1;
- bool stallctl : 1;
- bool sysstall : 1;
- bool nooverflow : 1;
- bool atbtrig : 1;
- bool lpoverride : 1;
- bool skip_power_up : 1; bool paused : 1; u64 trfcr; struct etmv4_config active_config;
The purpose of TRCSSCSRn register is to show status of the corresponding Single-shot Comparator Control and input supports. That means writable field's purpose for reset or restore from idle status not for configuration.
Therefore, exclude ss_status from drvdata->config and move it to drvdata.
Before this patch, clearing the PENDING and STATUS bits when enabling a perf session could trigger multiple single-shot events within the same session. This issue will be addressed in a future patch; this patch intentionally preserves the existing behavior.
Reviewed-by: Leo Yan leo.yan@arm.com Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 1 - drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +++++++++----------- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- 4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index d24f533c623d0..098aabd2b922c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, off_mask = (offset & GENMASK(11, 5)); do { CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); } while (0); } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 70a5c0b4fad1c..9de0c268ff954 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) const struct etmv4_caps *caps = &drvdata->caps;
return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); + (drvdata->ss_status[n] & TRCSSCSRn_PC); }
u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) @@ -573,11 +573,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
for (i = 0; i < caps->nr_ss_cmp; i++) { - /* always clear status bit on restart if using single-shot */ + /* always clear status and pending bits on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) - config->ss_status[i] &= ~TRCSSCSRn_STATUS; + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } @@ -1081,7 +1081,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
/* read the status of the single shot comparators */ for (i = 0; i < caps->nr_ss_cmp; i++) { - config->ss_status[i] = + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); }
@@ -1162,12 +1162,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) drvdata, 1);
/* - * Userspace may read ss_status and cntr_val through sysfs after + * Userspace may read cntr_val through sysfs after * the sysfs-session has been disabled. */ - for (i = 0; i < caps->nr_ss_cmp; i++) - config->ss_status[i] = active_config->ss_status[i]; - for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
@@ -1525,8 +1522,9 @@ static void etm4_init_arch_data(void *info) */ caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); for (i = 0; i < caps->nr_ss_cmp; i++) { - drvdata->config.ss_status[i] = - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | + TRCSSCSRn_DA | TRCSSCSRn_INST); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index f6d053f73264c..50ef2e957300f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1833,8 +1833,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); - /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; + /* must clear bit 31 and 30 in related status register on programming */ + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; } @@ -1848,7 +1848,7 @@ static ssize_t sshot_status_show(struct device *dev, struct etmv4_config *config = &drvdata->config;
raw_spin_lock(&drvdata->spinlock); - val = config->ss_status[config->ss_idx]; + val = drvdata->ss_status[config->ss_idx]; raw_spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1885,8 +1885,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val); - /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; + /* must clear bit 31 and 30 in related status register on programming */ + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ffde48b6b41b2..8c1c1364b1c44 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -213,6 +213,7 @@ #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
#define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCSRn_PENDING BIT(30) #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
#define TRCSSPCICRn_PC_MASK GENMASK(7, 0) @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) #define ETM_DEFAULT_ADDR_COMP 0
#define TRCSSCSRn_PC BIT(3) +#define TRCSSCSRn_DV BIT(2) +#define TRCSSCSRn_DA BIT(1) +#define TRCSSCSRn_INST BIT(0)
/* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) @@ -980,7 +984,6 @@ struct etmv4_config { u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */ u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; - u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; u8 addr_idx; u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; @@ -1071,6 +1074,7 @@ struct etmv4_save_state { * @config: structure holding sysfs mode configuration. * @save_state: State to be preserved across power loss * @paused: Indicates if the trace unit is paused. + * @ss_status: The status of the corresponding single-shot comparator. * @arch_features: Bitmap of arch features of etmv4 devices. */ struct etmv4_drvdata { @@ -1091,6 +1095,7 @@ struct etmv4_drvdata { struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; + u32 ss_status[ETM_MAX_SS_CMP]; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); };
Hi,
Actually replied to v10 of this patch before I spotted v11. I'll repeat the comments here to keep them together.
On 9/15/26 12:34, Yeoreum Yun wrote:
The purpose of TRCSSCSRn register is to show status of the corresponding Single-shot Comparator Control and input supports. That means writable field's purpose for reset or restore from idle status not for configuration.
Therefore, exclude ss_status from drvdata->config and move it to drvdata.
Before this patch, clearing the PENDING and STATUS bits when enabling a perf session could trigger multiple single-shot events within the same session. This issue will be addressed in a future patch;
The hardware is designed to have multiple single shot events - the reset bit in TRCSSCCRn specifically programs this behaviour.
But the basic point is correct there is no need to have the status register as part of the configurable set of registers.
this patch intentionally preserves the existing behavior.
Reviewed-by: Leo Yan leo.yan@arm.com Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 1 - drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +++++++++----------- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- 4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index d24f533c623d0..098aabd2b922c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, off_mask = (offset & GENMASK(11, 5)); do { CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 70a5c0b4fad1c..9de0c268ff954 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) const struct etmv4_caps *caps = &drvdata->caps; return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
(drvdata->ss_status[n] & TRCSSCSRn_PC);u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) @@ -573,11 +573,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); for (i = 0; i < caps->nr_ss_cmp; i++) {
/* always clear status bit on restart if using single-shot */
/* always clear status and pending bits on restart if using single-shot */
config->ss_status[i] &= ~TRCSSCSRn_STATUS;
drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));@@ -1081,7 +1081,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) /* read the status of the single shot comparators */ for (i = 0; i < caps->nr_ss_cmp; i++) {
config->ss_status[i] =
drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));@@ -1162,12 +1162,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) drvdata, 1); /*
* Userspace may read ss_status and cntr_val through sysfs after
* Userspace may read cntr_val through sysfs after*/
- the sysfs-session has been disabled.
- for (i = 0; i < caps->nr_ss_cmp; i++)
config->ss_status[i] = active_config->ss_status[i];- for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
@@ -1525,8 +1522,9 @@ static void etm4_init_arch_data(void *info) */ caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); for (i = 0; i < caps->nr_ss_cmp; i++) {
drvdata->config.ss_status[i] =etm4x_relaxed_read32(csa, TRCSSCSRn(i));
drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |TRCSSCSRn_DA | TRCSSCSRn_INST);
The unused bits in this register are RES0 - rendering this masking redundant.
} /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index f6d053f73264c..50ef2e957300f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1833,8 +1833,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; }
@@ -1848,7 +1848,7 @@ static ssize_t sshot_status_show(struct device *dev, struct etmv4_config *config = &drvdata->config; raw_spin_lock(&drvdata->spinlock);
- val = config->ss_status[config->ss_idx];
- val = drvdata->ss_status[config->ss_idx]; raw_spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); }
@@ -1885,8 +1885,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; }
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ffde48b6b41b2..8c1c1364b1c44 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -213,6 +213,7 @@ #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) #define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCSRn_PENDING BIT(30)
Minor nit - PENDING is ETE only - worth commenting in case a reader is looking at the ETMv4 spec.
#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) #define ETM_DEFAULT_ADDR_COMP 0 #define TRCSSCSRn_PC BIT(3) +#define TRCSSCSRn_DV BIT(2) +#define TRCSSCSRn_DA BIT(1) +#define TRCSSCSRn_INST BIT(0)
These new defs are redundant if the masking above is redundant
Regards
Mike
/* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) @@ -980,7 +984,6 @@ struct etmv4_config { u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */ u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP];
- u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; u8 addr_idx; u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
@@ -1071,6 +1074,7 @@ struct etmv4_save_state {
- @config: structure holding sysfs mode configuration.
- @save_state: State to be preserved across power loss
- @paused: Indicates if the trace unit is paused.
*/ struct etmv4_drvdata {
- @ss_status: The status of the corresponding single-shot comparator.
- @arch_features: Bitmap of arch features of etmv4 devices.
@@ -1091,6 +1095,7 @@ struct etmv4_drvdata { struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state;
- u32 ss_status[ETM_MAX_SS_CMP]; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); };
Hi,
Actually replied to v10 of this patch before I spotted v11. I'll repeat the comments here to keep them together.
Yeap. I confirmed but thanks again ;)
On 9/15/26 12:34, Yeoreum Yun wrote:
The purpose of TRCSSCSRn register is to show status of the corresponding Single-shot Comparator Control and input supports. That means writable field's purpose for reset or restore from idle status not for configuration.
Therefore, exclude ss_status from drvdata->config and move it to drvdata.
Before this patch, clearing the PENDING and STATUS bits when enabling a perf session could trigger multiple single-shot events within the same session. This issue will be addressed in a future patch;
The hardware is designed to have multiple single shot events - the reset bit in TRCSSCCRn specifically programs this behaviour.
But the basic point is correct there is no need to have the status register as part of the configurable set of registers.
Agree and Thanks for clarification!
this patch intentionally preserves the existing behavior.
Reviewed-by: Leo Yan leo.yan@arm.com Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 1 - drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +++++++++----------- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- 4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index d24f533c623d0..098aabd2b922c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, off_mask = (offset & GENMASK(11, 5)); do { CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 70a5c0b4fad1c..9de0c268ff954 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) const struct etmv4_caps *caps = &drvdata->caps; return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
(drvdata->ss_status[n] & TRCSSCSRn_PC);@@ -573,11 +573,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); for (i = 0; i < caps->nr_ss_cmp; i++) {
/* always clear status bit on restart if using single-shot */
/* always clear status and pending bits on restart if using single-shot */
config->ss_status[i] &= ~TRCSSCSRn_STATUS;
drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));@@ -1081,7 +1081,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) /* read the status of the single shot comparators */ for (i = 0; i < caps->nr_ss_cmp; i++) {
config->ss_status[i] =
drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));@@ -1162,12 +1162,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) drvdata, 1); /*
* Userspace may read ss_status and cntr_val through sysfs after
* Userspace may read cntr_val through sysfs after*/
- the sysfs-session has been disabled.
- for (i = 0; i < caps->nr_ss_cmp; i++)
config->ss_status[i] = active_config->ss_status[i];- for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
@@ -1525,8 +1522,9 @@ static void etm4_init_arch_data(void *info) */ caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); for (i = 0; i < caps->nr_ss_cmp; i++) {
drvdata->config.ss_status[i] =etm4x_relaxed_read32(csa, TRCSSCSRn(i));
drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |TRCSSCSRn_DA | TRCSSCSRn_INST);The unused bits in this register are RES0 - rendering this masking redundant.
There was some review for this whether RES0 versus clarifies the bit we see. TBH, I tend to agree it's redundant. So I'll restore it.
Thanks!
} /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index f6d053f73264c..50ef2e957300f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1833,8 +1833,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; }
@@ -1848,7 +1848,7 @@ static ssize_t sshot_status_show(struct device *dev, struct etmv4_config *config = &drvdata->config; raw_spin_lock(&drvdata->spinlock);
- val = config->ss_status[config->ss_idx];
- val = drvdata->ss_status[config->ss_idx]; raw_spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); }
@@ -1885,8 +1885,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); raw_spin_unlock(&drvdata->spinlock); return size; }
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ffde48b6b41b2..8c1c1364b1c44 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -213,6 +213,7 @@ #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) #define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCSRn_PENDING BIT(30)
Minor nit - PENDING is ETE only - worth commenting in case a reader is looking at the ETMv4 spec.
Thanks. I'll add a little bit of comment!
#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) #define ETM_DEFAULT_ADDR_COMP 0 #define TRCSSCSRn_PC BIT(3) +#define TRCSSCSRn_DV BIT(2) +#define TRCSSCSRn_DA BIT(1) +#define TRCSSCSRn_INST BIT(0)
These new defs are redundant if the masking above is redundant
+1
Thanks!
[...]
s_ex_level is a hardware capability rather than a configurable parameter. As such, it should not be stored in the configuration structure.
Remove s_ex_level from the config structure and pass etm4_caps to the functions that need to access this capability.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 58 +++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 5 +- 3 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9de0c268ff954..e484e12572732 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,12 @@ MODULE_PARM_DESC(pm_save_enable, "Save/restore state on power down: 1 = never, 2 = self-hosted. MMIO and DT only.");
static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; -static void etm4_set_default_config(struct etmv4_config *config); +static void etm4_set_default_config(struct etmv4_config *config, + const struct etmv4_caps *caps); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, struct perf_event *event); -static u64 etm4_get_access_type(struct etmv4_config *config); +static u64 etm4_get_access_type(struct etmv4_config *config, + const struct etmv4_caps *caps);
static enum cpuhp_state hp_online;
@@ -803,7 +805,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, config->mode |= ETM_MODE_EXCL_GUEST;
/* Always start from the default config */ - etm4_set_default_config(config); + etm4_set_default_config(config, caps);
/* Configure filters specified on the perf cmd line, if any. */ ret = etm4_set_event_filters(drvdata, event); @@ -1471,7 +1473,6 @@ static void etm4_init_arch_data(void *info)
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); - drvdata->config.s_ex_level = caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /* @@ -1556,19 +1557,22 @@ static void etm4_init_arch_data(void *info) cpu_detect_trace_filtering(drvdata); }
-static u32 etm4_get_victlr_access_type(struct etmv4_config *config) +static u32 etm4_get_victlr_access_type(struct etmv4_config *config, + const struct etmv4_caps *caps) { - return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); + return etm4_get_access_type(config, caps) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); }
/* Set ELx trace filter access in the TRCVICTLR register */ -static void etm4_set_victlr_access(struct etmv4_config *config) +static void etm4_set_victlr_access(struct etmv4_config *config, + const struct etmv4_caps *caps) { config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; - config->vinst_ctrl |= etm4_get_victlr_access_type(config); + config->vinst_ctrl |= etm4_get_victlr_access_type(config, caps); }
-static void etm4_set_default_config(struct etmv4_config *config) +static void etm4_set_default_config(struct etmv4_config *config, + const struct etmv4_caps *caps) { /* disable all events tracing */ config->eventctrl0 = 0x0; @@ -1587,7 +1591,7 @@ static void etm4_set_default_config(struct etmv4_config *config) config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
/* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ - etm4_set_victlr_access(config); + etm4_set_victlr_access(config, caps); }
static u64 etm4_get_ns_access_type(struct etmv4_config *config) @@ -1619,21 +1623,24 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) * This must be shifted to the corresponding register field * for usage. */ -static u64 etm4_get_access_type(struct etmv4_config *config) +static u64 etm4_get_access_type(struct etmv4_config *config, + const struct etmv4_caps *caps) { /* All Secure exception levels are excluded from the trace */ - return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; + return etm4_get_ns_access_type(config) | (u64)caps->s_ex_level; }
-static u64 etm4_get_comparator_access_type(struct etmv4_config *config) +static u64 etm4_get_comparator_access_type(struct etmv4_config *config, + const struct etmv4_caps *caps) { - return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; + return etm4_get_access_type(config, caps) << TRCACATR_EXLEVEL_SHIFT; }
static void etm4_set_comparator_filter(struct etmv4_config *config, + const struct etmv4_caps *caps, u64 start, u64 stop, int comparator) { - u64 access_type = etm4_get_comparator_access_type(config); + u64 access_type = etm4_get_comparator_access_type(config, caps);
/* First half of default address comparator */ config->addr_val[comparator] = start; @@ -1664,11 +1671,12 @@ static void etm4_set_comparator_filter(struct etmv4_config *config, }
static void etm4_set_start_stop_filter(struct etmv4_config *config, + const struct etmv4_caps *caps, u64 address, int comparator, enum etm_addr_type type) { int shift; - u64 access_type = etm4_get_comparator_access_type(config); + u64 access_type = etm4_get_comparator_access_type(config, caps);
/* Configure the comparator */ config->addr_val[comparator] = address; @@ -1700,7 +1708,8 @@ static void etm4_set_default_filter(struct etmv4_config *config) config->vissctlr = 0x0; }
-static void etm4_set_default(struct etmv4_config *config) +static void etm4_set_default(struct etmv4_config *config, + const struct etmv4_caps *caps) { if (WARN_ON_ONCE(!config)) return; @@ -1712,7 +1721,7 @@ static void etm4_set_default(struct etmv4_config *config) * full instruction trace - with a default filter for trace all * achieved by having no filtering. */ - etm4_set_default_config(config); + etm4_set_default_config(config, caps); etm4_set_default_filter(config); }
@@ -1760,6 +1769,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, { int i, comparator, ret = 0; u64 address; + const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct etm_filters *filters = event->hw.addr_filters;
@@ -1789,7 +1799,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
switch (type) { case ETM_ADDR_TYPE_RANGE: - etm4_set_comparator_filter(config, + etm4_set_comparator_filter(config, caps, filter->start_addr, filter->stop_addr, comparator); @@ -1810,7 +1820,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, filter->stop_addr);
/* Configure comparator */ - etm4_set_start_stop_filter(config, address, + etm4_set_start_stop_filter(config, caps, address, comparator, type);
/* @@ -1846,7 +1856,8 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, return ret; }
-void etm4_config_trace_mode(struct etmv4_config *config) +void etm4_config_trace_mode(struct etmv4_config *config, + const struct etmv4_caps *caps) { u32 mode;
@@ -1860,7 +1871,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) return;
- etm4_set_victlr_access(config); + etm4_set_victlr_access(config, caps); }
static int etm4_online_cpu(unsigned int cpu) @@ -2172,6 +2183,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) struct coresight_platform_data *pdata = NULL; struct device *dev = init_arg->dev; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); + const struct etmv4_caps *caps = &drvdata->caps; struct coresight_desc desc = { 0 }; u8 major, minor; char *type_name; @@ -2201,7 +2213,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) if (!desc.name) return -ENOMEM;
- etm4_set_default(&drvdata->config); + etm4_set_default(&drvdata->config, caps);
if (etm4x_always_pm_save(dev, init_arg->csa)) pm_save = true; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 50ef2e957300f..d826033d52e24 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -443,7 +443,7 @@ static ssize_t mode_store(struct device *dev, config->vinst_ctrl &= ~TRCVICTLR_TRCERR;
if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) - etm4_config_trace_mode(config); + etm4_config_trace_mode(config, caps);
raw_spin_unlock(&drvdata->spinlock);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 8c1c1364b1c44..f252da868b6de 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -955,7 +955,6 @@ struct etmv4_caps { * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. - * @s_ex_level: Secure ELs where tracing is supported. */ struct etmv4_config { u64 mode; @@ -998,7 +997,6 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; - u8 s_ex_level; };
/** @@ -1116,7 +1114,8 @@ enum etm_addr_ctxtype { };
extern const struct attribute_group *coresight_etmv4_groups[]; -void etm4_config_trace_mode(struct etmv4_config *config); +void etm4_config_trace_mode(struct etmv4_config *config, + const struct etmv4_caps *caps);
u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
Reviewed-by: Mike Leach mike.leach@arm.com
On 9/15/26 12:34, Yeoreum Yun wrote:
s_ex_level is a hardware capability rather than a configurable parameter. As such, it should not be stored in the configuration structure.
Remove s_ex_level from the config structure and pass etm4_caps to the functions that need to access this capability.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm4x-core.c | 58 +++++++++++++--------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 5 +- 3 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9de0c268ff954..e484e12572732 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,12 @@ MODULE_PARM_DESC(pm_save_enable, "Save/restore state on power down: 1 = never, 2 = self-hosted. MMIO and DT only."); static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; -static void etm4_set_default_config(struct etmv4_config *config); +static void etm4_set_default_config(struct etmv4_config *config,
const struct etmv4_caps *caps);-static u64 etm4_get_access_type(struct etmv4_config *config); +static u64 etm4_get_access_type(struct etmv4_config *config,
const struct etmv4_caps *caps);static enum cpuhp_state hp_online; @@ -803,7 +805,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, config->mode |= ETM_MODE_EXCL_GUEST; /* Always start from the default config */
- etm4_set_default_config(config);
- etm4_set_default_config(config, caps);
/* Configure filters specified on the perf cmd line, if any. */ ret = etm4_set_event_filters(drvdata, event); @@ -1471,7 +1473,6 @@ static void etm4_init_arch_data(void *info) /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /*
@@ -1556,19 +1557,22 @@ static void etm4_init_arch_data(void *info) cpu_detect_trace_filtering(drvdata); } -static u32 etm4_get_victlr_access_type(struct etmv4_config *config) +static u32 etm4_get_victlr_access_type(struct etmv4_config *config,
const struct etmv4_caps *caps)
- return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
- return etm4_get_access_type(config, caps) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); }
/* Set ELx trace filter access in the TRCVICTLR register */ -static void etm4_set_victlr_access(struct etmv4_config *config) +static void etm4_set_victlr_access(struct etmv4_config *config,
const struct etmv4_caps *caps)
- config->vinst_ctrl |= etm4_get_victlr_access_type(config);
- config->vinst_ctrl |= etm4_get_victlr_access_type(config, caps); }
-static void etm4_set_default_config(struct etmv4_config *config) +static void etm4_set_default_config(struct etmv4_config *config,
const struct etmv4_caps *caps)@@ -1587,7 +1591,7 @@ static void etm4_set_default_config(struct etmv4_config *config) config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
- etm4_set_victlr_access(config);
- etm4_set_victlr_access(config, caps); }
static u64 etm4_get_ns_access_type(struct etmv4_config *config) @@ -1619,21 +1623,24 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
- This must be shifted to the corresponding register field
- for usage.
*/ -static u64 etm4_get_access_type(struct etmv4_config *config) +static u64 etm4_get_access_type(struct etmv4_config *config,
const struct etmv4_caps *caps)
- return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
- return etm4_get_ns_access_type(config) | (u64)caps->s_ex_level; }
-static u64 etm4_get_comparator_access_type(struct etmv4_config *config) +static u64 etm4_get_comparator_access_type(struct etmv4_config *config,
const struct etmv4_caps *caps)
- return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
- return etm4_get_access_type(config, caps) << TRCACATR_EXLEVEL_SHIFT; }
static void etm4_set_comparator_filter(struct etmv4_config *config,
const struct etmv4_caps *caps, u64 start, u64 stop, int comparator)
- u64 access_type = etm4_get_comparator_access_type(config);
- u64 access_type = etm4_get_comparator_access_type(config, caps);
/* First half of default address comparator */ config->addr_val[comparator] = start; @@ -1664,11 +1671,12 @@ static void etm4_set_comparator_filter(struct etmv4_config *config, } static void etm4_set_start_stop_filter(struct etmv4_config *config,
const struct etmv4_caps *caps, u64 address, int comparator, enum etm_addr_type type)
- u64 access_type = etm4_get_comparator_access_type(config);
- u64 access_type = etm4_get_comparator_access_type(config, caps);
/* Configure the comparator */ config->addr_val[comparator] = address; @@ -1700,7 +1708,8 @@ static void etm4_set_default_filter(struct etmv4_config *config) config->vissctlr = 0x0; } -static void etm4_set_default(struct etmv4_config *config) +static void etm4_set_default(struct etmv4_config *config,
const struct etmv4_caps *caps)@@ -1712,7 +1721,7 @@ static void etm4_set_default(struct etmv4_config *config) * full instruction trace - with a default filter for trace all * achieved by having no filtering. */
- etm4_set_default_config(config);
- etm4_set_default_config(config, caps); etm4_set_default_filter(config); }
@@ -1760,6 +1769,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, { int i, comparator, ret = 0; u64 address;
- const struct etmv4_caps *caps = &drvdata->caps; struct etmv4_config *config = &drvdata->active_config; struct etm_filters *filters = event->hw.addr_filters;
@@ -1789,7 +1799,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, switch (type) { case ETM_ADDR_TYPE_RANGE:
etm4_set_comparator_filter(config,
etm4_set_comparator_filter(config, caps, filter->start_addr, filter->stop_addr, comparator);@@ -1810,7 +1820,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, filter->stop_addr); /* Configure comparator */
etm4_set_start_stop_filter(config, address,
etm4_set_start_stop_filter(config, caps, address, comparator, type);/* @@ -1846,7 +1856,8 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, return ret; } -void etm4_config_trace_mode(struct etmv4_config *config) +void etm4_config_trace_mode(struct etmv4_config *config,
const struct etmv4_caps *caps)@@ -1860,7 +1871,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) return;
- etm4_set_victlr_access(config);
- etm4_set_victlr_access(config, caps); }
static int etm4_online_cpu(unsigned int cpu) @@ -2172,6 +2183,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) struct coresight_platform_data *pdata = NULL; struct device *dev = init_arg->dev; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
- const struct etmv4_caps *caps = &drvdata->caps; struct coresight_desc desc = { 0 }; u8 major, minor; char *type_name;
@@ -2201,7 +2213,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) if (!desc.name) return -ENOMEM;
- etm4_set_default(&drvdata->config);
- etm4_set_default(&drvdata->config, caps);
if (etm4x_always_pm_save(dev, init_arg->csa)) pm_save = true; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 50ef2e957300f..d826033d52e24 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -443,7 +443,7 @@ static ssize_t mode_store(struct device *dev, config->vinst_ctrl &= ~TRCVICTLR_TRCERR; if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
etm4_config_trace_mode(config);
etm4_config_trace_mode(config, caps);raw_spin_unlock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 8c1c1364b1c44..f252da868b6de 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -955,7 +955,6 @@ struct etmv4_caps {
- @vmid_mask0: VM ID comparator mask for comparator 0-3.
- @vmid_mask1: VM ID comparator mask for comparator 4-7.
- @ext_inp: External input selection.
*/ struct etmv4_config { u64 mode;
- @s_ex_level: Secure ELs where tracing is supported.
@@ -998,7 +997,6 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp;
- u8 s_ex_level; };
/** @@ -1116,7 +1114,8 @@ enum etm_addr_ctxtype { }; extern const struct attribute_group *coresight_etmv4_groups[]; -void etm4_config_trace_mode(struct etmv4_config *config); +void etm4_config_trace_mode(struct etmv4_config *config,
const struct etmv4_caps *caps);u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
Introduce struct etm_caps to describe ETMv3 capabilities and move capabilities information into it.
Since drvdata->etmccr and drvdata->etmccer are used to check whether it supports fifofull logic and timestamping, remove etmccr and etmccer field from drvdata and add relevant fields in etm_caps structure.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com --- drivers/hwtracing/coresight/coresight-etm.h | 42 +++++++++++++--------- drivers/hwtracing/coresight/coresight-etm3x-core.c | 42 +++++++++++++--------- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 24 ++++++++----- 3 files changed, 66 insertions(+), 42 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3796162168d4..cb5f18dcdd974 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -140,6 +140,30 @@ ETM_ADD_COMP_0 | \ ETM_EVENT_NOT_A)
+/** + * struct etm_caps - specifics ETM capabilities + * @port_size: port size as reported by ETMCR bit 4-6 and 21. + * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. + * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. + * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25. + * @fifofull: FIFOFULL logic is present. + * @timestamp: Timestamping is implemented. + * @retstack: Return stack is implemented. + */ +struct etm_caps { + int port_size; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 nr_ext_out; + u8 nr_ctxid_cmp; + bool fifofull : 1; + bool timestamp : 1; + bool retstack : 1; +}; + /** * struct etm_config - configuration information related to an ETM * @mode: controls various modes supported by this ETM/PTM. @@ -212,19 +236,12 @@ struct etm_config { * @csdev: component vitals needed by the framework. * @spinlock: only one at a time pls. * @cpu: the cpu this component is affined to. - * @port_size: port size as reported by ETMCR bit 4-6 and 21. * @arch: ETM/PTM version number. + * @caps: ETM capabilities. * @use_cpu14: true if management registers need to be accessed via CP14. * @sticky_enable: true if ETM base configuration has been done. * @boot_enable:true if we should start tracing at boot time. * @os_unlock: true if access to management registers is allowed. - * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. - * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. - * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25. - * @etmccr: value of register ETMCCR. - * @etmccer: value of register ETMCCER. * @traceid: value of the current ID for this component. * @active_config: structure holding current running configuration. * @config: structure holding sysfs mode configuration. @@ -235,19 +252,12 @@ struct etm_drvdata { struct coresight_device *csdev; spinlock_t spinlock; int cpu; - int port_size; u8 arch; + struct etm_caps caps; bool use_cp14; bool sticky_enable; bool boot_enable; bool os_unlock; - u8 nr_addr_cmp; - u8 nr_cntr; - u8 nr_ext_inp; - u8 nr_ext_out; - u8 nr_ctxid_cmp; - u32 etmccr; - u32 etmccer; u32 traceid; struct etm_config active_config; struct etm_config config; diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 12bb38dc596e7..79c7cbe2084de 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,6 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) { + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level; @@ -356,8 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, * has ret stack) on the same SoC. So only enable when it can be honored * - trace will still continue normally otherwise. */ - if (ATTR_CFG_GET_FLD(attr, retstack) && - (drvdata->etmccer & ETMCCER_RETSTACK)) + if (ATTR_CFG_GET_FLD(attr, retstack) && (caps->retstack)) config->ctrl |= ETMCR_RETURN_STACK;
return 0; @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr; + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
@@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etmcr = etm_readl(drvdata, ETMCR); /* Clear setting from a previous run if need be */ etmcr &= ~ETM3X_SUPPORTED_OPTIONS; - etmcr |= drvdata->port_size; + etmcr |= caps->port_size; etmcr |= ETMCR_ETM_EN; etm_writel(drvdata, config->ctrl | etmcr, ETMCR); etm_writel(drvdata, config->trigger_event, ETMTRIGGER); @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->enable_event, ETMTEEVR); etm_writel(drvdata, config->enable_ctrl1, ETMTECR1); etm_writel(drvdata, config->fifofull_level, ETMFFLR); - for (i = 0; i < drvdata->nr_addr_cmp; i++) { + for (i = 0; i < caps->nr_addr_cmp; i++) { etm_writel(drvdata, config->addr_val[i], ETMACVRn(i)); etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i)); } - for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < caps->nr_cntr; i++) { etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i)); etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i)); etm_writel(drvdata, config->cntr_rld_event[i], @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR); etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR); etm_writel(drvdata, config->seq_curr_state, ETMSQR); - for (i = 0; i < drvdata->nr_ext_out; i++) + for (i = 0; i < caps->nr_ext_out; i++) etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i)); - for (i = 0; i < drvdata->nr_ctxid_cmp; i++) + for (i = 0; i < caps->nr_ctxid_cmp; i++) etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i)); etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR); etm_writel(drvdata, config->sync_freq, ETMSYNCFR); @@ -562,6 +563,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
@@ -571,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata) /* Read back sequencer and counters for post trace analysis */ config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
- for (i = 0; i < drvdata->nr_cntr; i++) + for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
etm_set_pwrdwn(drvdata); @@ -626,6 +628,7 @@ static void etm_disable_perf(struct coresight_device *csdev) static void etm_disable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config; const struct etm_config *active_config = &drvdata->active_config; int i; @@ -641,7 +644,7 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * Userspace may read seq_curr_state and cntr_val through sysfs * after the sysfs-session has been disabled. */ - for (i = 0; i < drvdata->nr_cntr; i++) + for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
config->seq_curr_state = active_config->seq_curr_state; @@ -726,7 +729,9 @@ static void etm_init_arch_data(void *info) { u32 etmidr; u32 etmccr; + u32 etmccer; struct etm_drvdata *drvdata = info; + struct etm_caps *caps = &drvdata->caps;
/* Make sure all registers are accessible */ etm_os_unlock(drvdata); @@ -751,16 +756,19 @@ static void etm_init_arch_data(void *info) /* Find all capabilities */ etmidr = etm_readl(drvdata, ETMIDR); drvdata->arch = BMVAL(etmidr, 4, 11); - drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; + caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; + + etmccer = etm_readl(drvdata, ETMCCER); + caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP); + caps->retstack = !!(etmccer & ETMCCER_RETSTACK);
- drvdata->etmccer = etm_readl(drvdata, ETMCCER); etmccr = etm_readl(drvdata, ETMCCR); - drvdata->etmccr = etmccr; - drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2; - drvdata->nr_cntr = BMVAL(etmccr, 13, 15); - drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19); - drvdata->nr_ext_out = BMVAL(etmccr, 20, 22); - drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25); + caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL); + caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2; + caps->nr_cntr = BMVAL(etmccr, 13, 15); + caps->nr_ext_inp = BMVAL(etmccr, 17, 19); + caps->nr_ext_out = BMVAL(etmccr, 20, 22); + caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
coresight_clear_self_claim_tag_unlocked(&drvdata->csa); etm_set_pwrdwn(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 2c8c129228589..36d4673537930 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -53,8 +53,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp; + val = caps->nr_addr_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp); @@ -63,8 +64,9 @@ static ssize_t nr_cntr_show(struct device *dev, struct device_attribute *attr, char *buf) { unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr; + val = caps->nr_cntr; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr); @@ -75,7 +77,7 @@ static ssize_t nr_ctxid_cmp_show(struct device *dev, unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- val = drvdata->nr_ctxid_cmp; + val = drvdata->caps.nr_ctxid_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ctxid_cmp); @@ -115,7 +117,7 @@ static ssize_t reset_store(struct device *dev, memset(config, 0, sizeof(struct etm_config)); config->mode = ETM_MODE_EXCLUDE; config->trigger_event = ETM_DEFAULT_EVENT_VAL; - for (i = 0; i < drvdata->nr_addr_cmp; i++) { + for (i = 0; i < drvdata->caps.nr_addr_cmp; i++) { config->addr_type[i] = ETM_ADDR_TYPE_NONE; }
@@ -146,6 +148,7 @@ static ssize_t mode_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); @@ -166,7 +169,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &= ~ETMCR_CYC_ACC;
if (config->mode & ETM_MODE_STALL) { - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) { + if (!caps->fifofull) { dev_warn(dev, "stall mode not supported\n"); ret = -EINVAL; goto err_unlock; @@ -176,7 +179,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &= ~ETMCR_STALL_MODE;
if (config->mode & ETM_MODE_TIMESTAMP) { - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) { + if (!caps->timestamp) { dev_warn(dev, "timestamp not supported\n"); ret = -EINVAL; goto err_unlock; @@ -321,13 +324,14 @@ static ssize_t addr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_addr_cmp) + if (val >= caps->nr_addr_cmp) return -EINVAL;
/* @@ -624,13 +628,14 @@ static ssize_t cntr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_cntr) + if (val >= caps->nr_cntr) return -EINVAL; /* * Use spinlock to ensure index doesn't change while it gets @@ -1030,13 +1035,14 @@ static ssize_t ctxid_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_ctxid_cmp) + if (val >= caps->nr_ctxid_cmp) return -EINVAL;
/*
Reviewed-by: Mike Leach mike.leach@arm.com
On 9/15/26 12:34, Yeoreum Yun wrote:
Introduce struct etm_caps to describe ETMv3 capabilities and move capabilities information into it.
Since drvdata->etmccr and drvdata->etmccer are used to check whether it supports fifofull logic and timestamping, remove etmccr and etmccer field from drvdata and add relevant fields in etm_caps structure.
Signed-off-by: Yeoreum Yun yeoreum.yun@arm.com
drivers/hwtracing/coresight/coresight-etm.h | 42 +++++++++++++--------- drivers/hwtracing/coresight/coresight-etm3x-core.c | 42 +++++++++++++--------- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 24 ++++++++----- 3 files changed, 66 insertions(+), 42 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3796162168d4..cb5f18dcdd974 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -140,6 +140,30 @@ ETM_ADD_COMP_0 | \ ETM_EVENT_NOT_A) +/**
- struct etm_caps - specifics ETM capabilities
- @port_size: port size as reported by ETMCR bit 4-6 and 21.
- @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
- @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
- @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
- @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
- @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
- @fifofull: FIFOFULL logic is present.
- @timestamp: Timestamping is implemented.
- @retstack: Return stack is implemented.
- */
+struct etm_caps {
- int port_size;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 nr_ext_out;
- u8 nr_ctxid_cmp;
- bool fifofull : 1;
- bool timestamp : 1;
- bool retstack : 1;
+};
- /**
- struct etm_config - configuration information related to an ETM
- @mode: controls various modes supported by this ETM/PTM.
@@ -212,19 +236,12 @@ struct etm_config {
- @csdev: component vitals needed by the framework.
- @spinlock: only one at a time pls.
- @cpu: the cpu this component is affined to.
- @port_size: port size as reported by ETMCR bit 4-6 and 21.
- @arch: ETM/PTM version number.
- @caps: ETM capabilities.
- @use_cpu14: true if management registers need to be accessed via CP14.
- @sticky_enable: true if ETM base configuration has been done.
- @boot_enable:true if we should start tracing at boot time.
- @os_unlock: true if access to management registers is allowed.
- @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
- @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
- @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
- @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
- @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
- @etmccr: value of register ETMCCR.
- @etmccer: value of register ETMCCER.
- @traceid: value of the current ID for this component.
- @active_config: structure holding current running configuration.
- @config: structure holding sysfs mode configuration.
@@ -235,19 +252,12 @@ struct etm_drvdata { struct coresight_device *csdev; spinlock_t spinlock; int cpu;
- int port_size; u8 arch;
- struct etm_caps caps; bool use_cp14; bool sticky_enable; bool boot_enable; bool os_unlock;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 nr_ext_out;
- u8 nr_ctxid_cmp;
- u32 etmccr;
- u32 etmccer; u32 traceid; struct etm_config active_config; struct etm_config config;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 12bb38dc596e7..79c7cbe2084de 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,6 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) {
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level;
@@ -356,8 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, * has ret stack) on the same SoC. So only enable when it can be honored * - trace will still continue normally otherwise. */
- if (ATTR_CFG_GET_FLD(attr, retstack) &&
(drvdata->etmccer & ETMCCER_RETSTACK))
- if (ATTR_CFG_GET_FLD(attr, retstack) && (caps->retstack)) config->ctrl |= ETMCR_RETURN_STACK;
return 0; @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr;
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
@@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etmcr = etm_readl(drvdata, ETMCR); /* Clear setting from a previous run if need be */ etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
- etmcr |= drvdata->port_size;
- etmcr |= caps->port_size; etmcr |= ETMCR_ETM_EN; etm_writel(drvdata, config->ctrl | etmcr, ETMCR); etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
@@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->enable_event, ETMTEEVR); etm_writel(drvdata, config->enable_ctrl1, ETMTECR1); etm_writel(drvdata, config->fifofull_level, ETMFFLR);
- for (i = 0; i < drvdata->nr_addr_cmp; i++) {
- for (i = 0; i < caps->nr_addr_cmp; i++) { etm_writel(drvdata, config->addr_val[i], ETMACVRn(i)); etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i)); }
- for (i = 0; i < drvdata->nr_cntr; i++) {
- for (i = 0; i < caps->nr_cntr; i++) { etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i)); etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i)); etm_writel(drvdata, config->cntr_rld_event[i],
@@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR); etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR); etm_writel(drvdata, config->seq_curr_state, ETMSQR);
- for (i = 0; i < drvdata->nr_ext_out; i++)
- for (i = 0; i < caps->nr_ext_out; i++) etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
- for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
- for (i = 0; i < caps->nr_ctxid_cmp; i++) etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i)); etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR); etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
@@ -562,6 +563,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i;
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev;
@@ -571,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata) /* Read back sequencer and counters for post trace analysis */ config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
- for (i = 0; i < drvdata->nr_cntr; i++)
- for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
etm_set_pwrdwn(drvdata); @@ -626,6 +628,7 @@ static void etm_disable_perf(struct coresight_device *csdev) static void etm_disable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config; const struct etm_config *active_config = &drvdata->active_config; int i;
@@ -641,7 +644,7 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * Userspace may read seq_curr_state and cntr_val through sysfs * after the sysfs-session has been disabled. */
- for (i = 0; i < drvdata->nr_cntr; i++)
- for (i = 0; i < caps->nr_cntr; i++) config->cntr_val[i] = active_config->cntr_val[i];
config->seq_curr_state = active_config->seq_curr_state; @@ -726,7 +729,9 @@ static void etm_init_arch_data(void *info) { u32 etmidr; u32 etmccr;
- u32 etmccer; struct etm_drvdata *drvdata = info;
- struct etm_caps *caps = &drvdata->caps;
/* Make sure all registers are accessible */ etm_os_unlock(drvdata); @@ -751,16 +756,19 @@ static void etm_init_arch_data(void *info) /* Find all capabilities */ etmidr = etm_readl(drvdata, ETMIDR); drvdata->arch = BMVAL(etmidr, 4, 11);
- drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
- caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
- etmccer = etm_readl(drvdata, ETMCCER);
- caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
- caps->retstack = !!(etmccer & ETMCCER_RETSTACK);
- drvdata->etmccer = etm_readl(drvdata, ETMCCER); etmccr = etm_readl(drvdata, ETMCCR);
- drvdata->etmccr = etmccr;
- drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
- drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
- drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
- drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
- drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
- caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
- caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
- caps->nr_cntr = BMVAL(etmccr, 13, 15);
- caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
- caps->nr_ext_out = BMVAL(etmccr, 20, 22);
- caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
coresight_clear_self_claim_tag_unlocked(&drvdata->csa); etm_set_pwrdwn(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 2c8c129228589..36d4673537930 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -53,8 +53,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp;
- val = caps->nr_addr_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp);
@@ -63,8 +64,9 @@ static ssize_t nr_cntr_show(struct device *dev, struct device_attribute *attr, char *buf) { unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr;
- val = caps->nr_cntr; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr);
@@ -75,7 +77,7 @@ static ssize_t nr_ctxid_cmp_show(struct device *dev, unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- val = drvdata->nr_ctxid_cmp;
- val = drvdata->caps.nr_ctxid_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ctxid_cmp);
@@ -115,7 +117,7 @@ static ssize_t reset_store(struct device *dev, memset(config, 0, sizeof(struct etm_config)); config->mode = ETM_MODE_EXCLUDE; config->trigger_event = ETM_DEFAULT_EVENT_VAL;
for (i = 0; i < drvdata->nr_addr_cmp; i++) {
for (i = 0; i < drvdata->caps.nr_addr_cmp; i++) { config->addr_type[i] = ETM_ADDR_TYPE_NONE;@@ -146,6 +148,7 @@ static ssize_t mode_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); @@ -166,7 +169,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &= ~ETMCR_CYC_ACC; if (config->mode & ETM_MODE_STALL) {
if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
if (!caps->fifofull) { dev_warn(dev, "stall mode not supported\n"); ret = -EINVAL; goto err_unlock;@@ -176,7 +179,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &= ~ETMCR_STALL_MODE; if (config->mode & ETM_MODE_TIMESTAMP) {
if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
if (!caps->timestamp) { dev_warn(dev, "timestamp not supported\n"); ret = -EINVAL; goto err_unlock;@@ -321,13 +324,14 @@ static ssize_t addr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_addr_cmp)
- if (val >= caps->nr_addr_cmp) return -EINVAL;
/* @@ -624,13 +628,14 @@ static ssize_t cntr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_cntr)
- if (val >= caps->nr_cntr) return -EINVAL; /*
- Use spinlock to ensure index doesn't change while it gets
@@ -1030,13 +1035,14 @@ static ssize_t ctxid_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- const struct etm_caps *caps = &drvdata->caps; struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val); if (ret) return ret;
- if (val >= drvdata->nr_ctxid_cmp)
- if (val >= caps->nr_ctxid_cmp) return -EINVAL;
/*
On Tue, Sep 15, 2026 at 12:34:35PM +0100, Yeoreum Yun wrote:
To resolve these inconsistencies, the configuration should be separated into:
- active_config, which is applied configuration for the current session
- config, which stores the settings configured via sysfs.
and apply configuration from configfs after taking a mode.
I did the following tests on this series:
1) Perf test on Orion6 board:
# ./perf test coresight 142: CoreSight synthesized callchain : Ok 143: CoreSight concurrent threads : Ok 144: CoreSight context switch thread attribution : Ok 145: CoreSight deterministic workload decode : Ok 146: CoreSight raw dump stress : Ok 147: Check Arm CoreSight trace data recording and synthesized samples : FAILED! 148: Check Arm CoreSight disassembly script completes without errors : Ok
Test 147 has a known issue with per-thread mode. The failure was already observed before this series.
2) Strobe mode test:
# echo 5000 > /sys/kernel/config/cs-syscfg/features/strobing/params/window/value
# echo 0 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 36.301 MB perf.data ]
# echo 1 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 18.361 MB perf.data ]
# echo 2 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 12.246 MB perf.data ]
# echo 3 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 9.197 MB perf.data ]
The captured trace sizes maintain the expected proportional relationship with the period values.
3) I verified the series on Juno-r2 baord with insmod and rmmod, and CPU PM, and did not see any regression.
Maybe it'd be good to send a new version addressing Mike's comments. Based on the test results, you can add my test tags:
Tested-by: Leo Yan leo.yan@arm.com
On Thu, Sep 24, 2026 at 04:25:43PM +0100, Leo Yan wrote:
On Tue, Sep 15, 2026 at 12:34:35PM +0100, Yeoreum Yun wrote:
To resolve these inconsistencies, the configuration should be separated into:
- active_config, which is applied configuration for the current session
- config, which stores the settings configured via sysfs.
and apply configuration from configfs after taking a mode.
I did the following tests on this series:
- Perf test on Orion6 board:
# ./perf test coresight 142: CoreSight synthesized callchain : Ok 143: CoreSight concurrent threads : Ok 144: CoreSight context switch thread attribution : Ok 145: CoreSight deterministic workload decode : Ok 146: CoreSight raw dump stress : Ok 147: Check Arm CoreSight trace data recording and synthesized samples : FAILED! 148: Check Arm CoreSight disassembly script completes without errors : Ok
Test 147 has a known issue with per-thread mode. The failure was already observed before this series.
- Strobe mode test:
# echo 5000 > /sys/kernel/config/cs-syscfg/features/strobing/params/window/value
# echo 0 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 36.301 MB perf.data ]
# echo 1 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 18.361 MB perf.data ]
# echo 2 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 12.246 MB perf.data ]
# echo 3 > /sys/kernel/config/cs-syscfg/features/strobing/params/period/value # perf record -e cs_etm/autofdo,timestamp=0/u -m,128M -- perf test -w brstack 3000000 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 9.197 MB perf.data ]
The captured trace sizes maintain the expected proportional relationship with the period values.
- I verified the series on Juno-r2 baord with insmod and rmmod, and CPU PM, and did not see any regression.
Maybe it'd be good to send a new version addressing Mike's comments. Based on the test results, you can add my test tags:
Tested-by: Leo Yan leo.yan@arm.com
Thanks! ;)
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Leo Yan -
Mike Leach -
Yeoreum Yun