CoreSight

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2620 discussions

[PATCH v2] stm class: Fix Kconfig symbols

by Leo Yan

Kconfig symbols must not include the CONFIG_ prefix. Remove the CONFIG_ prefix for default values to work. The STM_PROTO_SYS_T config is selected by default when STM is enabled. However, its description currently says "If you don't know what this is, say N," which contradicts the default behavior. Update the description to say "Y" to align with the default setting. Fixes: a02509f301c6 ("stm class: Factor out default framing protocol") Fixes: d69d5e83110f ("stm class: Add MIPI SyS-T protocol support") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Updated STM_PROTO_BASIC description to align with default selection (James). - Link to v1: https://lore.kernel.org/r/20251217-fix_stm_kconfig-v1-1-531fb3674549@arm.com --- drivers/hwtracing/stm/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/stm/Kconfig b/drivers/hwtracing/stm/Kconfig index eda6b11d40a1f9ab49a1ec1e6faae8ee178c5ed3..8ab079785189052945521e9b0a93a0d458de37e0 100644 --- a/drivers/hwtracing/stm/Kconfig +++ b/drivers/hwtracing/stm/Kconfig @@ -13,7 +13,7 @@ if STM config STM_PROTO_BASIC tristate "Basic STM framing protocol driver" - default CONFIG_STM + default STM help This is a simple framing protocol for sending data over STM devices. This was the protocol that the STM framework used @@ -28,7 +28,7 @@ config STM_PROTO_BASIC config STM_PROTO_SYS_T tristate "MIPI SyS-T STM framing protocol driver" - default CONFIG_STM + default STM help This is an implementation of MIPI SyS-T protocol to be used over the STP transport. In addition to the data payload, it @@ -38,7 +38,7 @@ config STM_PROTO_SYS_T The receiving side must be able to decode this protocol in addition to the MIPI STP, in order to extract the data. - If you don't know what this is, say N. + If you don't know what this is, say Y. config STM_DUMMY tristate "Dummy STM driver" --- base-commit: fcb70a56f4d81450114034b2c61f48ce7444a0e2 change-id: 20251216-fix_stm_kconfig-a72f40c7612c Best regards, -- Leo Yan <leo.yan(a)arm.com>

8 hours, 29 minutes

Re: [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Add an interrupt property to CTCU device. The interrupt will be triggered > when the data size in the ETR buffer exceeds the threshold of the > BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register > of CTCU device will enable the interrupt. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > index c969c16c21ef..ac27a8b89085 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > @@ -39,6 +39,11 @@ properties: > items: > - const: apb > > + interrupts: > + items: > + - description: Interrupt for the ETR device connected to in-port0. > + - description: Interrupt for the ETR device connected to in-port1. Is this all the hardware supports ? i.e., can it only have two ports ever ? If not, why restrict it to two ? Suzuki > + > label: > description: > Description of a coresight device. > @@ -60,6 +65,8 @@ additionalProperties: false > > examples: > - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > ctcu@1001000 { > compatible = "qcom,sa8775p-ctcu"; > reg = <0x1001000 0x1000>; > @@ -67,6 +74,9 @@ examples: > clocks = <&aoss_qmp>; > clock-names = "apb"; > > + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>; > + > in-ports { > #address-cells = <1>; > #size-cells = <0>; >

1 day, 9 hours

[PATCH v2 0/8] coresight: Fix device registration and unregistration

by Leo Yan

This series is to fix and refactor CoreSight device registration and unregistration, it can be divided into three small parts: Patches 01-03: Three fixes for memory leak, device reference and mutex protection. Patches 04-05: Move connection cleanup operations into coresight_remove_conns(). Patches 06-08: Refactor error handling in coresight_register(). This series is verified on Juno board with kmemleak detector. For kmemleak verifying: echo clear > /sys/kernel/debug/kmemleak insmod coresight modules rmmod coresight modules echo scan > /sys/kernel/debug/kmemleak The result shows no memory leak during a cycle of device registration and unregistration. --- Changes in v2: - Refined the commit log in patch 06 (Suzuki). - Unified to call coresight_unregister() for error handling (Suzuki). - Refactor connection and sysfs group release. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250512154108.23920-1-leo.yan@arm… To: Suzuki K Poulose <suzuki.poulose(a)arm.com> To: Mike Leach <mike.leach(a)linaro.org> To: James Clark <james.clark(a)linaro.org> To: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> To: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> To: Mathieu Poirier <mathieu.poirier(a)linaro.org> To: Mao Jinlong <quic_jinlmao(a)quicinc.com> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (8): coresight: Fix memory leak in coresight_alloc_device_name() coresight: Get parent device reference after sink ID map allocation coresight: Protect unregistration with mutex coresight: Refactor output connection sysfs link cleanup coresight: Refactor sysfs connection group cleanup coresight: Move sink validation into etm_perf_add_symlink_sink() coresight: Do not mix success path with failure handling coresight: Unify error handling in coresight_register() drivers/hwtracing/coresight/coresight-core.c | 105 +++++++++++------------ drivers/hwtracing/coresight/coresight-etm-perf.c | 5 +- drivers/hwtracing/coresight/coresight-platform.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 +- 4 files changed, 56 insertions(+), 59 deletions(-) --- base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d change-id: 20260120-arm_coresight_refactor_dev_register-f16c069db41d Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 day, 10 hours

Re: [PATCH v10 4/8] coresight: etr: refactor the tmc_etr_get_catu_device function

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Refactor tmc_etr_get_catu_device to retrieve the helper device connected > to the TMC ETR based on helper_subtype. Please could you leave this as it is and add : tmc_etr_get_ctcu_device() ? It doesn't make much sense to refactor something that is a wrapper for a generic function. Please avoid un-necessary abstraction Suzuki > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-catu.c | 3 ++- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 32 ++++++++++++++++--------- > drivers/hwtracing/coresight/coresight-tmc.h | 3 ++- > 3 files changed, 25 insertions(+), 13 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c > index 69b36bae97ab..d3972619cc96 100644 > --- a/drivers/hwtracing/coresight/coresight-catu.c > +++ b/drivers/hwtracing/coresight/coresight-catu.c > @@ -334,7 +334,8 @@ static int catu_alloc_etr_buf(struct tmc_drvdata *tmc_drvdata, > struct tmc_sg_table *catu_table; > struct catu_etr_buf *catu_buf; > > - csdev = tmc_etr_get_catu_device(tmc_drvdata); > + csdev = tmc_etr_get_helper_device(tmc_drvdata, > + CORESIGHT_DEV_SUBTYPE_HELPER_CATU); > if (!csdev) > return -ENODEV; > catu_buf = kzalloc(sizeof(*catu_buf), GFP_KERNEL); > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index cbbb15648fb7..16a4562533d5 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -844,28 +844,37 @@ static const struct etr_buf_operations etr_sg_buf_ops = { > }; > > /* > - * TMC ETR could be connected to a CATU device, which can provide address > - * translation service. This is represented by the Output port of the TMC > - * (ETR) connected to the input port of the CATU. > + * TMC ETR could be connected to the helper device, which can provide address > + * translation service(CATU) or data filter function(CTCU). This is represented > + * by the Output port of the TMC (ETR) connected to the input port of the helper. > * > - * Returns : coresight_device ptr for the CATU device if a CATU is found. > + * @drvdata : drvdata of the TMC device > + * @subtype : helper_subtype of the helper device > + * > + * Returns : coresight_device ptr for the helper device if a helper is found. > * : NULL otherwise. > */ > struct coresight_device * > -tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) > +tmc_etr_get_helper_device(struct tmc_drvdata *drvdata, > + enum coresight_dev_subtype_helper subtype) > { > struct coresight_device *etr = drvdata->csdev; > - union coresight_dev_subtype catu_subtype = { > - .helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU > + union coresight_dev_subtype helper_subtype = { > + .helper_subtype = subtype > }; > > - if (!IS_ENABLED(CONFIG_CORESIGHT_CATU)) > + > + if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CATU && > + !IS_ENABLED(CONFIG_CORESIGHT_CATU)) > + return NULL; > + else if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU && > + !IS_ENABLED(CONFIG_CORESIGHT_CTCU)) > return NULL; > > return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER, > - catu_subtype); > + helper_subtype); > } > -EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device); > +EXPORT_SYMBOL_GPL(tmc_etr_get_helper_device); > > static const struct etr_buf_operations *etr_buf_ops[] = { > [ETR_MODE_FLAT] = &etr_flat_buf_ops, > @@ -913,7 +922,8 @@ static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw) > > buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent); > buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); > - buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata); > + buf_hw->has_catu = !!tmc_etr_get_helper_device(drvdata, > + CORESIGHT_DEV_SUBTYPE_HELPER_CATU); > buf_hw->has_resrv = tmc_has_reserved_buffer(drvdata); > } > > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index c9a82ff6cd00..7690a70069da 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -471,7 +471,8 @@ static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata, > return crc32_le(0, (void *)drvdata->resrv_buf.vaddr, crc_size); > } > > -struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); > +struct coresight_device *tmc_etr_get_helper_device(struct tmc_drvdata *drvdata, > + enum coresight_dev_subtype_helper subtype); > > void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); > void tmc_etr_remove_catu_ops(void); >

1 day, 10 hours

[GIT PULL] coresight: Updates for Linux v7.0

by Suzuki K Poulose

Hi Greg Please find the coresight hwtracing subsystem changes for the next release. Kindly pull Suzuki The following changes since commit 8f0b4cce4481fb22653697cced8d0d04027cb1e8: Linux 6.19-rc1 (2025-12-14 16:05:07 +1200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v7.0 for you to fetch changes up to eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d: coresight: tmc: Decouple the perf buffer allocation from sysfs mode (2026-01-21 10:32:27 +0000) ---------------------------------------------------------------- coresight: Updates for Linux v6.20/v7.0 This batch of CoreSight hwtracing updates contains : - Fine grained control of Timestamp generation in ETM4 trace, retaining backward compatibility - Feature updates for Qualcomm TPDA driver - Support Qualcomm Interconnect TNOC - Miscellaneous fixes to TMC-ETR driver Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Antonio Borneo (1): coresight: etm3x: Fix cpulocked warning on cpuhp James Clark (13): coresight: Change syncfreq to be a u8 coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Hide unused ETMv3 format attributes coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() coresight: Don't reject unrecognized ETMv3 format attributes coresight: Interpret perf config with ATTR_CFG_GET_FLD() coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() coresight: Remove misleading definitions coresight: Prepare to allow setting the timestamp interval coresight: Extend width of timestamp format attribute coresight: docs: Document etm4x timestamp interval option Jie Gan (3): dt-binding: Update oss email address for Coresight documents dt-bindings: arm: add CTCU device for monaco coresight: tpda: add global_flush_req sysfs node Suzuki K Poulose (1): coresight: tpda: Fix intendation for sysfs interface documentation Tao Zhang (3): coresight: tpda: add sysfs nodes for tpda cross-trigger configuration coresight: tpda: add logic to configure TPDA_SYNCR register coresight: tpda: add sysfs node to flush specific port Yicong Yang (3): coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata coresight: tmc-etr: Fix race condition between sysfs and perf mode coresight: tmc: Decouple the perf buffer allocation from sysfs mode Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../sysfs-bus-coresight-devices-dummy-source | 4 +- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 69 +++++ .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 56 ++-- .../bindings/arm/arm,coresight-dummy-sink.yaml | 2 +- .../bindings/arm/arm,coresight-dummy-source.yaml | 2 +- .../bindings/arm/qcom,coresight-ctcu.yaml | 15 +- .../bindings/arm/qcom,coresight-itnoc.yaml | 90 +++++++ .../bindings/arm/qcom,coresight-remote-etm.yaml | 4 +- .../bindings/arm/qcom,coresight-tnoc.yaml | 2 +- .../bindings/arm/qcom,coresight-tpda.yaml | 4 +- .../bindings/arm/qcom,coresight-tpdm.yaml | 4 +- Documentation/trace/coresight/coresight.rst | 16 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 68 ++--- drivers/hwtracing/coresight/coresight-etm-perf.h | 38 +++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 51 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 175 +++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 92 +++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 43 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tnoc.c | 136 +++++++++- drivers/hwtracing/coresight/coresight-tpda.c | 284 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpda.h | 76 +++++- include/linux/coresight-pmu.h | 24 -- 23 files changed, 995 insertions(+), 262 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml

1 day, 15 hours

[PATCH v2 0/2] tools: Fix bitfield failure and minor polish

by Leo Yan

The first patch fixes an build failure issued caused by bitfield on the stable kernel, the second patch is a minor polish to avoid including redundant headers. Verified for Arm64 perf building. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (2): tools: Fix bitfield dependency failure perf: Remove redundant kernel.h include tools/include/linux/bitfield.h | 1 + tools/perf/arch/arm64/util/header.c | 1 - tools/perf/util/cs-etm.c | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) --- base-commit: 800af362d68945e589f73cda429d04bfe4287feb change-id: 20260123-perf_fix_bitfield-h-084902f55c35 Best regards, -- Leo Yan <leo.yan(a)arm.com>

4 days, 13 hours

Re: [PATCH v10 3/8] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Introduce sysfs_read_ops as a wrapper, wrap sysfs read operations, for reading > trace data from the TMC buffer. > > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 50 +++++++++++------------- > drivers/hwtracing/coresight/coresight-tmc.h | 17 ++++++++ > 2 files changed, 40 insertions(+), 27 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 1ea255ffa67c..8b0397a77e57 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) > { > int ret = 0; > > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - ret = tmc_read_prepare_etb(drvdata); > - break; > - case TMC_CONFIG_TYPE_ETR: > - ret = tmc_read_prepare_etr(drvdata); > - break; > - default: > + if (drvdata->sysfs_ops) > + ret = drvdata->sysfs_ops->read_prepare(drvdata); > + else > ret = -EINVAL; > - } > > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); > @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) > { > int ret = 0; > > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - ret = tmc_read_unprepare_etb(drvdata); > - break; > - case TMC_CONFIG_TYPE_ETR: > - ret = tmc_read_unprepare_etr(drvdata); > - break; > - default: > + if (drvdata->sysfs_ops) > + ret = drvdata->sysfs_ops->read_unprepare(drvdata); > + else > ret = -EINVAL; > - } > > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); > @@ -291,13 +277,8 @@ static int tmc_open(struct inode *inode, struct file *file) > static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, > char **bufpp) > { > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); > - case TMC_CONFIG_TYPE_ETR: > - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > - } > + if (drvdata->sysfs_ops) > + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); minor nit: Please could we bail out in tmc_open() if the drvdata->sysfs_ops is not set. That way, we don't have to sprinkle it everywhere. And also, we don't expect to see this case anyways. > > return -EINVAL; > } > @@ -769,6 +750,18 @@ static void register_crash_dev_interface(struct tmc_drvdata *drvdata, > "Valid crash tracedata found\n"); > } > > +static const struct sysfs_read_ops tmc_etb_sysfs_read_ops = { minor nit: please could we rename the struct type to : struct tmc_sysfs_ops and then use etb_sysfs_ops = {} etr_sysfs_ops = {} Rest looks fine to me Suzuki > + .read_prepare = tmc_read_prepare_etb, > + .read_unprepare = tmc_read_unprepare_etb, > + .get_trace_data = tmc_etb_get_sysfs_trace, > +}; > + > +static const struct sysfs_read_ops tmc_etr_sysfs_read_ops = { > + .read_prepare = tmc_read_prepare_etr, > + .read_unprepare = tmc_read_unprepare_etr, > + .get_trace_data = tmc_etr_get_sysfs_trace, > +}; > + > static int __tmc_probe(struct device *dev, struct resource *res) > { > int ret = 0; > @@ -828,6 +821,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; > desc.ops = &tmc_etb_cs_ops; > dev_list = &etb_devs; > + drvdata->sysfs_ops = &tmc_etb_sysfs_read_ops; > break; > case TMC_CONFIG_TYPE_ETR: > desc.groups = coresight_etr_groups; > @@ -841,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > mutex_init(&drvdata->idr_mutex); > dev_list = &etr_devs; > INIT_LIST_HEAD(&drvdata->etr_buf_list); > + drvdata->sysfs_ops = &tmc_etr_sysfs_read_ops; > break; > case TMC_CONFIG_TYPE_ETF: > desc.groups = coresight_etf_groups; > @@ -849,6 +844,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; > desc.ops = &tmc_etf_cs_ops; > dev_list = &etf_devs; > + drvdata->sysfs_ops = &tmc_etb_sysfs_read_ops; > break; > default: > pr_err("%s: Unsupported TMC config\n", desc.name); > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 9b3c4e6f0a5e..c9a82ff6cd00 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -221,6 +221,8 @@ struct etr_buf_node { > struct list_head node; > }; > > +struct sysfs_read_ops; > + > /** > * struct tmc_drvdata - specifics associated to an TMC component > * @atclk: optional clock for the core parts of the TMC. > @@ -258,6 +260,7 @@ struct etr_buf_node { > * Used by ETR/ETF. > * @etr_buf_list: List that is used to manage allocated etr_buf. > * @reading_node: Available buffer_node for byte-cntr reading. > + * @sysfs_ops: Read operations for sysfs mode. > */ > struct tmc_drvdata { > struct clk *atclk; > @@ -290,6 +293,20 @@ struct tmc_drvdata { > struct tmc_resrv_buf crash_mdata; > struct list_head etr_buf_list; > struct etr_buf_node *reading_node; > + const struct sysfs_read_ops *sysfs_ops; > +}; > + > +/** > + * struct sysfs_read_ops - read operations for TMC and its helper devices > + * @read_prepare: prepare operation. > + * @read_unprepare: unprepare operation. > + * @get_trace_data: read operation. > + */ > +struct sysfs_read_ops { > + int (*read_prepare)(struct tmc_drvdata *drvdata); > + int (*read_unprepare)(struct tmc_drvdata *drvdata); > + ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos, > + size_t len, char **bufpp); > }; > > struct etr_buf_operations { >

5 days, 16 hours

Re: [PATCH v10 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Remove ctcu_get_active_port from CTCU module and add it to the core > framework. > > The port number is crucial for the CTCU device to identify which ETR > it serves. With the port number we can correctly get required parameters > of the CTCU device in TMC module. > > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +----------------- > drivers/hwtracing/coresight/coresight-priv.h | 2 ++ > 3 files changed, 27 insertions(+), 18 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index c660cf8adb1c..0e8448784c62 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -585,6 +585,30 @@ struct coresight_device *coresight_get_sink(struct coresight_path *path) > } > EXPORT_SYMBOL_GPL(coresight_get_sink); > > +/** > + * coresight_get_in_port: Find the input port number at @csdev where a @remote > + * device is connected to. This doesn't match the code ? We are looking at the remote devices' in_connections ? > + * > + * @csdev: csdev of the device. > + * @remote: csdev of the remote device which is connected to @csdev. > + * > + * Return: port number upon success or -EINVAL for fail. > + */ > +int coresight_get_in_port(struct coresight_device *csdev, > + struct coresight_device *remote) > +{ > + struct coresight_platform_data *pdata = remote->pdata; > + int i; > + > + for (i = 0; i < pdata->nr_inconns; ++i) { > + if (pdata->in_conns[i]->src_dev == csdev) > + return pdata->in_conns[i]->dest_port; > + } Suzuki

5 days, 16 hours

Re: [PATCH v5 0/3] Coresight TMC-ETR: refactor the tmc-etr mode and some cleanups

by Suzuki K Poulose

On Wed, 21 Jan 2026 18:15:40 +0800, Yushan Wang wrote: > This patchset builds upon Yicong's previous patches [1]. > I rebase the patchset onto coresight for-next branch. > > Patch 2 introducing fix race issues found by using TMC-ETR. > Patch 1 & 3 introducing two cleanups found when debugging the issues. > > [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… > > [...] Applied, thanks! [1/3] coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata https://git.kernel.org/coresight/c/5da8c55dd879 [2/3] coresight: tmc-etr: Fix race condition between sysfs and perf mode https://git.kernel.org/coresight/c/e6e43e82c79c [3/3] coresight: tmc: Decouple the perf buffer allocation from sysfs mode https://git.kernel.org/coresight/c/eebe8dbd8630 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

6 days, 10 hours

[PATCH v2 0/2] perf cs-etm: Fix decoding for sparse CPU maps

by James Clark

Fix a regression caused by an incorrect assumption about auxtrace indices. Then add a test that would have caught it. --- Changes in v2: - Fix cover letter and subject - Link to v1: https://lore.kernel.org/r/20260119-james-perf-coresight-cpu-map-segfault-v1… --- James Clark (2): perf cs-etm: Fix decoding for sparse CPU maps perf cs-etm: Test sparse CPU maps tools/perf/tests/shell/test_arm_coresight.sh | 54 ++++++++++++++++++++++++++++ tools/perf/util/cs-etm.c | 3 +- 2 files changed, 56 insertions(+), 1 deletion(-) --- base-commit: 571d29baa07e83e637075239f379f91353c24ec9 change-id: 20260115-james-perf-coresight-cpu-map-segfault-e250af5aa778 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week

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