Hi Igor
On 13/11/2026 05:46, Igor Velkov wrote:
Hi,
Cortex-A55 (Amlogic S905X3) reports EDDEVID.PCSample = 0, so coresight-cpu-debug cannot use it. The PC is available through PMPCSR in the external PMU frame (debug frame + 0x20000, PMDEVID.PCSample = 1). A lab module reading PMPCSR caught the PC of a CPU stuck on a PCIe bus access with IRQs off; on this GICv2 SoC the stop IPI never reaches it.
Two observations:
- A panic notifier samples too late: the other CPUs are stopped by then, and on this SoC reading the PMU frame of a stopped CPU raises a synchronous external abort. Sampling on entry to smp_send_stop() works.
- Marvell has an out-of-tree patch, "coresight: cpu-debug: Add support to dump PMPCSR" (2023, carried in linux-yocto); I could not find it on the lists.
Is PMPCSR support in coresight-cpu-debug planned or welcome? And how
Patches are definitely welcome, as such I don't know of anyone working on it from within Arm. So, please go ahead and post it.
should such a PMU frame be described in DT: arm,coresight-cpu-debug or a new compatible?
If the support can be detected using the "standard" cpu-debug frame, via the DEVID registers, I don't think we need a new compatible.
But we can debate on it with the patch review.
Cheers Suzuki
Thanks, Igor