CoreSight

coresight@lists.linaro.org

4 participants
2725 discussions

by marekzmyslowski

RTFM to me :) Solution was easy: echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable Regards Marek W dniu 2017-10-02 19:16:12 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 2 October 2017 at 09:41, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mathieu, > > > > I'm trying to use CSAL for DragonBoard. The fisrt thing there is rom_init. According to the docs, the rom that needs to be mmaped is 0x800000. Is there any way to check if the power domain or clock turned om? > > There is no way to check from user space. When using the CSAL people > will typically connect to the board using a Dstream (or another Jtag > solution). That typically switch on the power domain and the required > clock, given the initialisation script for the board has done that > correctly. > > The dragonboard is popular and ubiquitous, it shouldn't be hard to > find a Jtag init script on the internet somewhere. If you don't have > a Jtag you can read the Jtag init script for that board and enact the > same operations by mmap'ing memory areas and flipping bits. > > > > > Regards > > Marek > > > > W dniu 2017-10-02 16:50:08 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > >> On 2 October 2017 at 02:15, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hello, > >> > > >> > I'm trying to get access to Qualcomm Debug Subsystem on my DragonBoard 410c by using the mmap. Just want to read data available in DQSS_DAPROM. However when I try to do that, the system is rebooting. Any idea why I can't do that? > >> > > >> > int size = 4096; > >> > off_t addr_to_map = 0x00800000; //according to docs this is an address of QDSS_DAPROM > >> > > >> > int mem_fd = open("/dev/mem", O_RDWR); > >> > localv = mmap(0, size, PROT_READ, MAP_SHARED, mem_fd, addr_to_map); > >> > printf ("mmap completed %p.\n", localv); > >> > tab = (unsigned int *)localv; > >> > printf ("%u\n", tab[0]); > >> > > >> > Result of my application execution: > >> > mmap completed 0x7fa29f0000.[ 484.585864] Synchronous External Abort: synchronous external abort (0x92000010) at 0x0000007fa29f0000 > >> > >> > >> This is usually an indication the memory area you are trying to reach > >> is not accessible - either the power domain hasn't been switched on or > >> the clock(s) aren't enabled. Is there a device driver specific to the > >> DQSS_DAPROM? > >> > >> > > >> > Regards > >> > Marek > >> > > >> > Linux linaro-developer 4.14.0-rc1+ #2 SMP PREEMPT Thu Sep 21 10:39:33 CEST 2017 aarch64 GNU/Linux > >> > > >> > _______________________________________________ > >> > CoreSight mailing list > >> > CoreSight(a)lists.linaro.org > >> > https://lists.linaro.org/mailman/listinfo/coresight > >> > > > > > > >

9 years, 1 month

Re: Re: Access to QDSS

by marekzmyslowski

Hello Mathieu, I'm trying to use CSAL for DragonBoard. The fisrt thing there is rom_init. According to the docs, the rom that needs to be mmaped is 0x800000. Is there any way to check if the power domain or clock turned om? Regards Marek W dniu 2017-10-02 16:50:08 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 2 October 2017 at 02:15, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello, > > > > I'm trying to get access to Qualcomm Debug Subsystem on my DragonBoard 410c by using the mmap. Just want to read data available in DQSS_DAPROM. However when I try to do that, the system is rebooting. Any idea why I can't do that? > > > > int size = 4096; > > off_t addr_to_map = 0x00800000; //according to docs this is an address of QDSS_DAPROM > > > > int mem_fd = open("/dev/mem", O_RDWR); > > localv = mmap(0, size, PROT_READ, MAP_SHARED, mem_fd, addr_to_map); > > printf ("mmap completed %p.\n", localv); > > tab = (unsigned int *)localv; > > printf ("%u\n", tab[0]); > > > > Result of my application execution: > > mmap completed 0x7fa29f0000.[ 484.585864] Synchronous External Abort: synchronous external abort (0x92000010) at 0x0000007fa29f0000 > > > This is usually an indication the memory area you are trying to reach > is not accessible - either the power domain hasn't been switched on or > the clock(s) aren't enabled. Is there a device driver specific to the > DQSS_DAPROM? > > > > > Regards > > Marek > > > > Linux linaro-developer 4.14.0-rc1+ #2 SMP PREEMPT Thu Sep 21 10:39:33 CEST 2017 aarch64 GNU/Linux > > > > _______________________________________________ > > CoreSight mailing list > > CoreSight(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/coresight >

9 years, 1 month

Access to QDSS

by marekzmyslowski

Hello, I'm trying to get access to Qualcomm Debug Subsystem on my DragonBoard 410c by using the mmap. Just want to read data available in DQSS_DAPROM. However when I try to do that, the system is rebooting. Any idea why I can't do that? int size = 4096; off_t addr_to_map = 0x00800000; //according to docs this is an address of QDSS_DAPROM int mem_fd = open("/dev/mem", O_RDWR); localv = mmap(0, size, PROT_READ, MAP_SHARED, mem_fd, addr_to_map); printf ("mmap completed %p.\n", localv); tab = (unsigned int *)localv; printf ("%u\n", tab[0]); Result of my application execution: mmap completed 0x7fa29f0000.[ 484.585864] Synchronous External Abort: synchronous external abort (0x92000010) at 0x0000007fa29f0000 Regards Marek Linux linaro-developer 4.14.0-rc1+ #2 SMP PREEMPT Thu Sep 21 10:39:33 CEST 2017 aarch64 GNU/Linux

9 years, 1 month

Re: Re: Access to QDSS

by marekzmyslowski

Hi Leo, Busybox gives the same results: root@linaro-developer:~# busybox devmem 0x00800000 [ 1713.501755] Synchronous External Abort: synchronous external abort (0x92000010) at 0x0000007fbb6eb000 How this clock can be enabled? I though it is already enabled. I used default configuration for db410c and it includes the msm8916.dtsi file. Regards Marek W dniu 2017-10-02 12:02:55 użytkownik Leo Yan <leo.yan(a)linaro.org> napisał: > On Mon, Oct 02, 2017 at 11:15:27AM +0200, marekzmyslowski wrote: > > Hello, > > > > I'm trying to get access to Qualcomm Debug Subsystem on my DragonBoard 410c by using the mmap. Just want to read data available in DQSS_DAPROM. However when I try to do that, the system is rebooting. Any idea why I can't do that? > > > > int size = 4096; > > off_t addr_to_map = 0x00800000; //according to docs this is an address of QDSS_DAPROM > > > > int mem_fd = open("/dev/mem", O_RDWR); > > localv = mmap(0, size, PROT_READ, MAP_SHARED, mem_fd, addr_to_map); > > printf ("mmap completed %p.\n", localv); > > tab = (unsigned int *)localv; > > printf ("%u\n", tab[0]); > > > > Result of my application execution: > > mmap completed 0x7fa29f0000.[ 484.585864] Synchronous External Abort: synchronous external abort (0x92000010) at 0x0000007fa29f0000 > > Seems this external exception relate with clock, so need enable > RPM_QDSS_CLK clock firstly? > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc… > > Thanks, > Leo Yan >

9 years, 1 month

New perf-opencsd repo on gitHub

by Mathieu Poirier

Good day all, As discussed in the meeting yesterday I have started a new gitHub repository [1] to host the perf-opencsd kernel. Right now it has all the same kernel branches as found on the openCSD repository. I have also added a small wiki that gives people a little bit of information on the repository itself. Note that the openCSD repository hasn't been modified yet and that *everything* in the perf-opencsd is currently considered experimental. I am sharing this early to give people a chance to comment on the structure, naming and whatever they want to see modified. Regards, Mathieu [1]. https://github.com/Linaro/perf-opencsd

9 years, 1 month

[PATCH 1/2] perf inject: correct recording of branch address and destination

by Sebastian Pop

ARM ETM traces contain packets of executed instructions. The addresses recorded in the trace correspond to the beginning and one instruction past the end of the block of executed instructions. In order to record the address and destination of executed branches, keep track of two packets: the jump occurs from the last executed instruction of the previous packet to the address of the first instruction in the current packet. Signed-off-by: Sebastian Pop <s.pop(a)samsung.com> Signed-off-by: Brian Rzycki <b.rzycki(a)samsung.com> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 ++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 91 +++++++++++++++++-------- 3 files changed, 75 insertions(+), 29 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index b4cbf4c..6164bfe 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -143,6 +143,18 @@ static int cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_buffer[et].sample_type = sample_type; decoder->packet_buffer[et].start_addr = elem->st_addr; decoder->packet_buffer[et].end_addr = elem->en_addr; + switch (elem->last_i_type) { + case OCSD_INSTR_BR: + case OCSD_INSTR_BR_INDIRECT: + decoder->packet_buffer[et].last_instruction_is_branch = true; + break; + case OCSD_INSTR_OTHER: + case OCSD_INSTR_ISB: + case OCSD_INSTR_DSB_DMB: + default: + decoder->packet_buffer[et].last_instruction_is_branch = false; + break; + } decoder->packet_buffer[et].exc = false; decoder->packet_buffer[et].exc_ret = false; decoder->packet_buffer[et].cpu = *((int*)inode->priv); diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index d15a288..4fd5a9b 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -49,6 +49,7 @@ struct cs_etm_packet { enum cs_etm_sample_type sample_type; uint64_t start_addr; uint64_t end_addr; + bool last_instruction_is_branch; bool exc; bool exc_ret; int cpu; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 8270203..c99b728 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -104,6 +104,10 @@ struct cs_etm_queue { * inserted. */ size_t last_branch_pos; + /* + * A pointer to the last and current decoded packets. + */ + struct cs_etm_packet *prev_packet, *packet; }; static int cs_etm__get_trace(struct cs_etm_buffer *buff, struct cs_etm_queue *etmq); @@ -226,6 +230,8 @@ static void cs_etm__free_queue(void *priv) zfree(&etmq->event_buf); zfree(&etmq->last_branch); zfree(&etmq->last_branch_rb); + zfree(&etmq->prev_packet); + zfree(&etmq->packet); zfree(&etmq->chain); free(etmq); } @@ -392,6 +398,7 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, if (etm->synth_opts.last_branch) { size_t sz = sizeof(struct branch_stack); + size_t szp = sizeof(struct cs_etm_packet); sz += etm->synth_opts.last_branch_sz * sizeof(struct branch_entry); @@ -401,6 +408,12 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, etmq->last_branch_rb = zalloc(sz); if (!etmq->last_branch_rb) goto out_free; + etmq->prev_packet = zalloc(szp); + if (!etmq->prev_packet) + goto out_free; + etmq->packet = zalloc(szp); + if (!etmq->packet) + goto out_free; } etmq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); @@ -451,6 +464,8 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm, zfree(&etmq->event_buf); zfree(&etmq->last_branch); zfree(&etmq->last_branch_rb); + zfree(&etmq->prev_packet); + zfree(&etmq->packet); zfree(&etmq->chain); free(etmq); return NULL; @@ -594,8 +609,7 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq) etmq->last_branch_rb->nr = 0; } -static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, - struct cs_etm_packet *packet) +static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq) { struct branch_stack *bs = etmq->last_branch_rb; struct branch_entry *be; @@ -611,10 +625,16 @@ static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, etmq->last_branch_pos -= 1; - be = &bs->entries[etmq->last_branch_pos]; - be->from = packet->start_addr; - be->to = packet->end_addr; - /* No support for mispredict */ + be = &bs->entries[etmq->last_branch_pos]; + + /* + * The FROM address needs to be the instruction before the end of the + * packet at END_ADDR: substract from END_ADDR the size of the last + * instruction: 4 bytes. + */ + be->from = etmq->prev_packet->end_addr - 4; + be->to = etmq->packet->start_addr; + /* No support for mispredict. */ be->flags.mispred = 0; be->flags.predicted = 1; @@ -721,13 +741,13 @@ static struct cs_etm_cache_entry *cs_etm__cache_lookup(struct dso *dso, } #endif -static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, - struct cs_etm_packet *packet) +static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq) { int ret = 0; struct cs_etm_auxtrace *etm = etmq->etm; union perf_event *event = etmq->event_buf; struct perf_sample sample = {.ip = 0,}; + struct cs_etm_packet *packet = etmq->packet; uint64_t start_addr = packet->start_addr; uint64_t end_addr = packet->end_addr; @@ -941,17 +961,18 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, static int cs_etm__sample(struct cs_etm_queue *etmq, int *cpu) { - //const struct cs_etm_state *state = etmq->state; - struct cs_etm_packet packet; - //struct cs_etm_auxtrace *etm = etmq->etm; - int err; + struct cs_etm_auxtrace *etm = etmq->etm; + struct cs_etm_packet *tmp; + int err = cs_etm_decoder__get_packet(etmq->decoder, etmq->packet); - err = cs_etm_decoder__get_packet(etmq->decoder,&packet); - // if there is no sample, it returns err = -1, no real error + /* + * If there is no sample, it returns err = -1, no real error. + */ if (err) return err; - if (etmq->etm->synth_opts.last_branch) { - *cpu = packet.cpu; + + if (etm->synth_opts.last_branch) { + *cpu = etmq->packet->cpu; /* * FIXME: as the trace sampling does not work for now, (for @@ -961,17 +982,30 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, int *cpu) * should be rewritten as "if reached sampling period". */ if (etmq->last_branch_rb->nr == - etmq->etm->synth_opts.last_branch_sz) { - err = cs_etm__synth_instruction_sample(etmq, &packet); + etm->synth_opts.last_branch_sz) { + err = cs_etm__synth_instruction_sample(etmq); if (err) return err; } - cs_etm__update_last_branch_rb(etmq, &packet); - } else if (packet.sample_type & CS_ETM_RANGE) { - err = cs_etm__synth_instruction_sample(etmq,&packet); - if (err) - return err; - } + /* + * Record a branch when the last instruction in PREV_PACKET is a + * branch. + */ + if (etmq->prev_packet->last_instruction_is_branch) + cs_etm__update_last_branch_rb(etmq); + + /* + * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for + * the next incoming packet. + */ + tmp = etmq->packet; + etmq->packet = etmq->prev_packet; + etmq->prev_packet = tmp; + } else if (etmq->packet->sample_type & CS_ETM_RANGE) { + err = cs_etm__synth_instruction_sample(etmq); + if (err) + return err; + } return 0; } @@ -1016,15 +1050,14 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq, u64 *timestamp) * buffer at the end of the trace. */ if (etmq->etm->synth_opts.last_branch) { - struct cs_etm_packet packet; struct branch_stack *bs = etmq->last_branch_rb; struct branch_entry *be = &bs->entries[etmq->last_branch_pos]; - packet.cpu = cpu; - packet.start_addr = be->from; - packet.end_addr = be->to; + etmq->packet->cpu = cpu; + etmq->packet->start_addr = be->to; + etmq->packet->end_addr = be->to + 4; - err = cs_etm__synth_instruction_sample(etmq, &packet); + err = cs_etm__synth_instruction_sample(etmq); if (err) return err; } -- 2.7.4

9 years, 1 month

[PATCH v7 00/22] Add support for CoreSight trace decoding

by Tor Jeremiassen

Hi, This patchset adds support for user space decoding of CoreSight traces [1] of the ARM architecture. Kernel support for configuring CoreSight tracers and collect the hardware trace data in the auxtrace section of the perf.data file is already integrated [2]. The user space implementation mirrors to a large degree that of the Intel Processor Trace (PT) [3] implementation, except that the decoder library itself is separate from the perf tool sources, and is built and maintained as a separate open source project [4]. Instead, this patch set includes the necessary code and build settings to interfaces to the decoder library, as well as a "stub" or "null" library for the case when the perf tool is built without the library. The decoder library interface code in this patch set only supports ETMv4 trace decoding, though the library itself supports a broader range. Future patches will add support for more versions of the ARM ETM trace encoding. Changes from v2: Changed patch sequence to enable packet dump (-D or --dump-raw-trace option) first. Then build up to full packet decode. Also added functions to the trace decoder library interface as they are referenced by the functions in the main coresight processing file and combined them in those patches. Changes from v3: Introduced functions in cs-etm-decoder.c at the same time they are referenced in cs-etm.c, and not waiting until the very end to change the build script to compile the full decoder library interface. Changes from v4: Removed function to directly read vmlinux file text section, instead relying on perf dso access functions. Changes from v5: Refactored cs-etm-decoder-stub.c so that the different parts are introduced when the corresponding parts in cs-etm-decoder.c are added. Changed error returns in cs-etm-decoder.c to use enums as opposed to literals. Changed handling of how memory access function is added to decoder library. Now, instead of adding for each MMAP2 entry and the kernel only one entry is added for the entire address space. The functionality is equivalent to the previous, except the code is simpler. Changes from v6: Removed stub library, instead replaced by conditionally using a static inline function in cs-etm.h when the decoder library is not available. Tor Jeremiassen (22): perf tools: Add initial hooks for decoding coresight traces perf tools: Add processing of coresight metadata perf tools: Add coresight trace decoder library interface perf tools: Add data block processing function perf tools: Add etmv4i packet printing capability perf tools: Add decoder new and free perf tools: Add trace packet print for dump_trace option perf tools: Add code to process the auxtrace perf event perf tools: Add function to read data from dsos perf tools: Add mapping from cpu to cs_etm_queue perf tools: Add functions to allocate and free queues perf tools: Add functions to setup and initialize queues perf tools: Add functions to allocate and free queues perf tools: Add function to get trace data from aux buffer perf tools: Add function to run the trace decoder and process samples perf tools: Add functions to process queues and run the trace decoder perf tools: Add perf event processing perf tools: Add processing of queues when events are flushed perf tools: Add synth_events and supporting functions perf tools: Add function to clear the decoder packet buffer perf tools: Add functions for full etmv4i packet decode MAINTAINERS: Adding entry for CoreSight trace decoding MAINTAINERS | 3 +- tools/perf/Makefile.config | 26 + tools/perf/util/Build | 6 + tools/perf/util/auxtrace.c | 2 + tools/perf/util/cs-etm-decoder/Build | 2 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 526 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 133 +++ tools/perf/util/cs-etm.c | 1179 +++++++++++++++++++++++ tools/perf/util/cs-etm.h | 50 + 9 files changed, 1926 insertions(+), 1 deletion(-) create mode 100644 tools/perf/util/cs-etm-decoder/Build create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.h create mode 100644 tools/perf/util/cs-etm.c -- 2.7.4

9 years, 1 month

[PATCH 0/2] perf tools: floating autoFDO patches

by Mathieu Poirier

These two patches generated a fair amount of discussion on the mailing list when they were sent and as such I didn't apply them. But from what I understand people use them when doing autoFDO testing. They may not be perfect but at least provide a base for discussion and further improvement. My intention is to add them to the perf-opencsd-master branch for the 4.14 cycle. If anyone is categorically against it please get back to me with convincing arguments. Best regards, Mathieu Sebastian Pop (2): perf inject: correct recording of branch address and destination perf inject: record branches in chronological order tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 136 ++++++++++++++---------- 3 files changed, 95 insertions(+), 54 deletions(-) -- 2.7.4

9 years, 1 month

Re: Re: Re: OpenCSD + DragonBoard 410c

by marekzmyslowski

Great. Thank you. Regards Marek W dniu 2017-09-14 23:45:51 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 14 September 2017 at 15:24, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mike, > > > > Thank you. I will try to use it. One more question if I may. Where do you get userdata/rootfs - for example something like this > https://github.com/96boards/documentation/blob/master/ConsumerEdition/Drago… > ? > > > I'm not sure about what you need here... The user space I run can be > found here [1] but it seems you've already found that page... > > Mathieu > > [1]. https://96boards.org/documentation/ConsumerEdition/DragonBoard-410c/Downloa… > > > > > > > Regards > > Marek > > > > W dniu 2017-09-14 18:13:26 użytkownik Mike Leach <mike.leach(a)linaro.org> napisał: > >> Hi, > >> > >> I've attached the .config I am using to debug coresight drivers on > >> DB410c - used to build the opencsd-perf-4.13 kernel tree in the > >> OpenCSD github project. > >> The .dtb to use is apq8016-sbc.dtb > >> > >> Regards > >> > >> Mike > >> > >> On 14 September 2017 at 09:31, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hi, > >> > > >> > I'm trying to build kernel for the DragonBoard 410c to use the CoreSight. What config should I used (default for the qcom) and what dtb file is related to that board? > >> > > >> > Regards > >> > Marek > >> > _______________________________________________ > >> > CoreSight mailing list > >> > CoreSight(a)lists.linaro.org > >> > https://lists.linaro.org/mailman/listinfo/coresight > >> > >> > >> > >> -- > >> Mike Leach > >> Principal Engineer, ARM Ltd. > >> Blackburn Design Centre. UK > >> > > > > > > > > _______________________________________________ > > CoreSight mailing list > > CoreSight(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/coresight >

9 years, 1 month

Re: Re: OpenCSD + DragonBoard 410c

by marekzmyslowski

Hello Mike, Thank you. I will try to use it. One more question if I may. Where do you get userdata/rootfs - for example something like this https://github.com/96boards/documentation/blob/master/ConsumerEdition/Drago… ? Regards Marek W dniu 2017-09-14 18:13:26 użytkownik Mike Leach <mike.leach(a)linaro.org> napisał: > Hi, > > I've attached the .config I am using to debug coresight drivers on > DB410c - used to build the opencsd-perf-4.13 kernel tree in the > OpenCSD github project. > The .dtb to use is apq8016-sbc.dtb > > Regards > > Mike > > On 14 September 2017 at 09:31, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hi, > > > > I'm trying to build kernel for the DragonBoard 410c to use the CoreSight. What config should I used (default for the qcom) and what dtb file is related to that board? > > > > Regards > > Marek > > _______________________________________________ > > CoreSight mailing list > > CoreSight(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/coresight > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Blackburn Design Centre. UK >

9 years, 1 month

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