CoreSight

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2604 discussions

[PATCH 0/2] coresight: Dismiss smatch warnings

by Leo Yan

This series polishes the code to address warnings reported by the smatch static checker. Smatch reports a error "Function too hairy" for etm4x_sysreg_read() and etm4x_sysreg_write(). This is a trade off to avoid large code blocks, the implementation encapsulates logic using nested macros. But this is not friendly to static checker. For now, the code will be kept as is. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (2): coresight: stm: Remove redundant NULL checks coresight: perf: Use %px for printing pointers drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++-- drivers/hwtracing/coresight/coresight-stm.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250611-arm_cs_fix_smatch_warning_v1-6c2b5e78e38a Best regards, -- Leo Yan <leo.yan(a)arm.com>

6 months

Re: [PATCH v5 1/5] dt-bindings: arm: Add CoreSight QMI component description

by Jinlong Mao

On 2025/4/25 4:30, Konrad Dybcio wrote: > On 4/24/25 1:58 PM, Mao Jinlong wrote: >> Add new coresight-qmi.yaml file describing the bindings required >> to define qmi node in the device trees. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- > > Is the service-id hardcoded/well-known? If so, we can drop > this devicetree node and create a new platform device (& probe the > related driver) based on the presence of qcom,qmi-id that you add > in patch 3 > > Konrad service-id is not hardcoded. Different qmi connections will have different service ids. >

6 months

Re: [PATCH] hwtracing: coresight: Use of_reserved_mem_region_to_resource() for "memory-region"

by Suzuki K Poulose

On Thu, 03 Jul 2025 13:35:33 -0500, Rob Herring (Arm) wrote: > Use the newly added of_reserved_mem_region_to_resource() function to > handle "memory-region" properties. > > Applied, thanks! [1/1] hwtracing: coresight: Use of_reserved_mem_region_to_resource() for "memory-region" https://git.kernel.org/coresight/c/f0148bd7 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

6 months

[PATCH] coresight: Only register perf symlink for sinks with alloc_buffer

by Yuanfang Zhang

Ensure that etm_perf_add_symlink_sink() is only called for devices that implement the alloc_buffer operation. This prevents invalid symlink creation for dummy sinks that do not implement alloc_buffer. Without this check, perf may attempt to use a dummy sink that lacks alloc_buffer operationsu to initialise perf's ring buffer, leading to runtime failures. Fixes: 9d3ba0b6c0569 ("Coresight: Add coresight dummy driver") Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index fa758cc21827552a5c97b6bdd05d22dec4994b22..fddf04c5ee46eb4d559416296f7e85ce6c5689fa 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1374,8 +1374,9 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) goto out_unlock; } - if (csdev->type == CORESIGHT_DEV_TYPE_SINK || - csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) { + if ((csdev->type == CORESIGHT_DEV_TYPE_SINK || + csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) && + sink_ops(csdev)->alloc_buffer) { ret = etm_perf_add_symlink_sink(csdev); if (ret) { --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250630-etm_perf_sink-ee0fcffc6820 Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

6 months

[PATCH] coresight: Fix missing include for FIELD_GET

by James Clark

Include the header for FIELD_GET which is only sometimes transitively included on some configs and kernel releases. Reported-by: Linux Kernel Functional Testing <lkft(a)linaro.org> Closes: https://lists.linaro.org/archives/list/lkft-triage@lists.linaro.org/thread/… Fixes: a4e65842e114 ("coresight: Only check bottom two claim bits") Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 1 + drivers/hwtracing/coresight/ultrasoc-smb.h | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index fa758cc21827..c2db94f2ab23 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -3,6 +3,7 @@ * Copyright (c) 2012, The Linux Foundation. All rights reserved. */ +#include <linux/bitfield.h> #include <linux/build_bug.h> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 42e5d37403ad..cbea200489c8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -4,6 +4,7 @@ */ #include <linux/acpi.h> +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/kernel.h> #include <linux/kvm_host.h> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ab251865b893..e9eeea6240d5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier <mathieu.poirier(a)linaro.org> */ +#include <linux/bitfield.h> #include <linux/coresight.h> #include <linux/pid_namespace.h> #include <linux/pm_runtime.h> diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h index c4c111275627..323f0ccb6878 100644 --- a/drivers/hwtracing/coresight/ultrasoc-smb.h +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h @@ -7,6 +7,7 @@ #ifndef _ULTRASOC_SMB_H #define _ULTRASOC_SMB_H +#include <linux/bitfield.h> #include <linux/miscdevice.h> #include <linux/spinlock.h> --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250707-james-coresight-bitfield-include-03d14f5369f2 Best regards, -- James Clark <james.clark(a)linaro.org>

6 months

[PATCH] coresight: trbe: Add ISB after TRBLIMITR write

by James Clark

DEN0154 states that hardware will be allowed to ignore writes to TRB* registers while the trace buffer is enabled. Add an ISB to ensure that it's disabled before clearing the other registers. This is purely defensive because it's expected that arm_trbe_disable() would be called before teardown which has the required ISB. Fixes: a2b579c41fe9 ("coresight: trbe: Remove redundant disable call") Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-trbe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 8267dd1a2130..10f3fb401edf 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -257,6 +257,7 @@ static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata) static void trbe_reset_local(struct trbe_cpudata *cpudata) { write_sysreg_s(0, SYS_TRBLIMITR_EL1); + isb(); trbe_drain_buffer(); write_sysreg_s(0, SYS_TRBPTR_EL1); write_sysreg_s(0, SYS_TRBBASER_EL1); --- base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 change-id: 20250609-james-cs-trblimitr-isb-523f20d874d6 Best regards, -- James Clark <james.clark(a)linaro.org>

6 months

[PATCH 0/5] Refactoring finding CPU phandles in DT

by Alireza Sanaee

This series refactors the way CPU IDs are retrieved from the device tree. Usually, there is a for loop that goes over every single CPU that can be avoided. This also reduces the amount of NULL pointer checks in drivers. I have abstracted away that loop and introduced a new function (of_cpu_node_to_id) for this. This patchset is a subset of [1], where I removed content and patches relevant to hyper-threaded cores for DT. Based on the discussion, the code refactor is still useful, hence this patchset. [1] https://lore.kernel.org/all/20250512080715.82-1-alireza.sanaee@huawei.com/ Alireza Sanaee (5): of: add infra for finding CPU id from phandle arch_topology: update CPU map to use the new API coresight: cti: Use of_cpu_phandle_to_id for grabbing CPU id coresight: Use of_cpu_phandle_to_id for grabbing CPU id perf/arm-dsu: refactor cpu id retrieval via new API of_cpu_phandle_to_id drivers/base/arch_topology.c | 12 ++++---- .../coresight/coresight-cti-platform.c | 15 ++-------- .../hwtracing/coresight/coresight-platform.c | 14 ++------- drivers/of/cpu.c | 29 +++++++++++++++++++ drivers/perf/arm_dsu_pmu.c | 6 ++-- include/linux/of.h | 9 ++++++ 6 files changed, 51 insertions(+), 34 deletions(-) -- 2.43.0

6 months, 1 week

[PATCH] coresight-tmc: Add configurable timeout for flush and tmcready

by Yuanfang Zhang

The current implementation uses a fixed timeout via coresight_timeout(), which may be insufficient when multiple sources are enabled or under heavy load, leading to TMC readiness or flush completion timeout. This patch introduces a configurable timeout mechanism for flush and tmcready. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tmc-core.c | 43 ++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 88afb16bb6bec395ba535155228d176250f38625..286d56ce88fe80fbfa022946dc798f0f4e72f961 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -8,6 +8,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/types.h> +#include <linux/delay.h> #include <linux/device.h> #include <linux/idr.h> #include <linux/io.h> @@ -35,13 +36,31 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); +static u32 tmc_timeout; + +static void tmc_extend_timeout(struct csdev_access *csa, u32 offset, int pos, int val) +{ + int i; + + for (i = tmc_timeout; i > 0; i--) { + if (i - 1) + udelay(1); + } +} + +static int tmc_wait_status(struct csdev_access *csa, u32 offset, int pos, int val) +{ + return coresight_timeout_action(csa, offset, pos, val, + tmc_extend_timeout); +} + int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; /* Ensure formatter, unformatter and hardware fifo are empty */ - if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { + if (tmc_wait_status(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { dev_err(&csdev->dev, "timeout while waiting for TMC to be Ready\n"); return -EBUSY; @@ -61,7 +80,7 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */ - if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { + if (tmc_wait_status(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { dev_err(&csdev->dev, "timeout while waiting for completion of Manual Flush\n"); } @@ -561,11 +580,31 @@ static ssize_t stop_on_flush_store(struct device *dev, static DEVICE_ATTR_RW(stop_on_flush); +static ssize_t timeout_cfg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d\n", tmc_timeout); +} + +static ssize_t timeout_cfg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + tmc_timeout = val; + + return size; +} +static DEVICE_ATTR_RW(timeout_cfg); static struct attribute *coresight_tmc_attrs[] = { &dev_attr_trigger_cntr.attr, &dev_attr_buffer_size.attr, &dev_attr_stop_on_flush.attr, + &dev_attr_timeout_cfg.attr, NULL, }; --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250627-flush_timeout-a598b4c0ce7b Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

6 months, 1 week

Re: [PATCH v2 06/28] coresight: etm4x: Add context synchronization before enabling trace

by Leo Yan

On Wed, Jul 02, 2025 at 12:05:10PM +0100, Yeoreum Yun wrote: [...] > > @@ -445,13 +445,37 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) > > etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); > > > > etm4x_allow_trace(drvdata); > > + > > + /* > > + * According to software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), > > + * execute a Context synchronization event to guarantee the trace unit > > + * will observe the new values of the System registers. > > + */ > > + if (!csa->io_mem) > > + isb(); > > + > > But, when write to SYS_TRFCR_EL1 in etm4x_allow_trace(), it already does > isb(). Is it redundant? Good point. It is not sufficient. As a system register writing in kvm_tracing_set_el1_configuration(), this is why adds a ISB here. Thanks, Leo

6 months, 1 week

Re: [PATCH v2 05/28] coresight: etm4x: Ensure context synchronization is not ignored

by Leo Yan

Hi Levi, On Wed, Jul 02, 2025 at 12:10:17PM +0100, Yeoreum Yun wrote: [...] > > @@ -579,6 +572,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > > > > if (!drvdata->paused) > > rc = etm4_enable_trace_unit(drvdata); > > + > > + /* > > + * As recommended by section 4.3.7 (Synchronization of register updates) > > + * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an > > + * ISB instruction after programming the trace unit registers. > > + */ > > + isb(); > > But according to 4.3.7 ("Synchronization when using memory-mapped > interface"), doesn't it need to dsb like: > > if (csa->iomem) > dsb(sy); > isb(); > > Or am I missing something? Section 4.3.7 suggests using a DSB barrier to ensure that writes have completed in MMIO mode. It also mentions an alternative: "If the memory is marked as Device-nGnRE or stronger, read back the value of any register in the trace unit. This relies on the peripheral coherence order defined in the Arm architecture." In the etm4_{enable|disable}_trace_unit() functions, each time the TRCPRGCTLR register is written, the driver polls bits in TRCSTATR. This acts as synchronization using read-after-write (RAW), which is exactly the approach suggested above. This is why we don't need DSB() anymore. Thanks, Leo

6 months, 1 week

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