CoreSight

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2727 discussions

[PATCH 00/19] coresight: Support for ETMv4.4 system instructions

by Suzuki K Poulose

CoreSight ETMv4.4 introduced system instructions for accessing the ETM. This also implies that they may not be on the amba bus. Right now all the CoreSight components are accessed via memory map. Also, we have some common routines in coresight generic code driver (e.g, CS_LOCK, claim/disclaim), which assume the mmio. In order to preserve the generic algorithms at a single place and to allow dynamic switch for ETMs, this series introduces an abstraction layer for accessing a coresight device. It is designed such that the mmio access are fast tracked (i.e, without an indirect function call). This will also help us to get rid of the driver+attribute specific sysfs show/store routines and replace them with a single routine to access a given register offset (which can be embedded in the dev_ext_attribute). This is not currently implemented in the series, but can be achieved. Further we switch the generic routines to work with the abstraction. With this in place, we refactor the etm4x code a bit to allow for supporting the system instructions with very little new code. The changes also switch to using the system instructions by default even when we may have an MMIO. We use TRCDEVARCH for the detection of the ETM component, which is a standard register as per CoreSight architecture, rather than the etm specific id register TRCIDR3. This is for making sure that we are able to detect the ETM via system instructions accurately, when the the trace unit could be anything (etm or a custom trace unit). The series has been mildly tested on a model. I would really appreciate any testing on real hardware. Applies on coresight/next Changes since V1: - Flip the switch for iomem from no_iomem to io_mem in csdev_access. - Split patches for claim/disclaim and CS_LOCK/UNLOCK conversions. - Move device access initialisation for etm4x to the target CPU - Cleanup secure exception level mask handling. - Switch to use TRCDEVARCH for ETM component discovery. This is for making - Check the availability of OS/Software Locks before using them. Suzuki K Poulose (19): coresight: Introduce device access abstraction coresight: tpiu: Prepare for using coresight device access abstraction coresight: Convert coresight_timeout to use access abstraction coresight: Convert claim/disclaim operations to use access wrappers coresight: Use device access layer for Software lock/unlock operations coresight: etm4x: Always read the registers on the host CPU coresight: etm4x: Convert all register accesses coresight: etm4x: Add commentary on the registers coresight: etm4x: Add sysreg access helpers coresight: etm4x: Define DEVARCH register fields coresight: etm4x: Check for OS and Software Lock coresight: etm4x: Cleanup secure exception level masks coresight: etm4x: Clean up exception level masks coresight: etm4x: Detect access early on the target CPU coresight: etm4x: Use TRCDEVARCH for component discovery coresight: etm4x: Detect system instructions support coresight: etm4x: Refactor probing routine coresight: etm4x: Add support for sysreg only devices dts: bindings: coresight: ETMv4.4 system register access only units .../devicetree/bindings/arm/coresight.txt | 6 +- drivers/hwtracing/coresight/coresight-catu.c | 24 +- .../hwtracing/coresight/coresight-cpu-debug.c | 22 +- .../hwtracing/coresight/coresight-cti-sysfs.c | 5 +- drivers/hwtracing/coresight/coresight-cti.c | 34 +- drivers/hwtracing/coresight/coresight-etb10.c | 29 +- .../coresight/coresight-etm3x-sysfs.c | 10 +- drivers/hwtracing/coresight/coresight-etm3x.c | 35 +- .../coresight/coresight-etm4x-sysfs.c | 44 +- drivers/hwtracing/coresight/coresight-etm4x.c | 716 +++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 440 ++++++++++- .../hwtracing/coresight/coresight-funnel.c | 22 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- .../coresight/coresight-replicator.c | 31 +- drivers/hwtracing/coresight/coresight-stm.c | 50 +- .../hwtracing/coresight/coresight-tmc-etf.c | 38 +- .../hwtracing/coresight/coresight-tmc-etr.c | 20 +- drivers/hwtracing/coresight/coresight-tmc.c | 16 +- drivers/hwtracing/coresight/coresight-tpiu.c | 32 +- drivers/hwtracing/coresight/coresight.c | 130 +++- include/linux/coresight.h | 230 +++++- 21 files changed, 1449 insertions(+), 494 deletions(-) -- 2.24.1

6 years, 1 month

[PATCHv2 0/2] Coresight ETF perf NULL pointer dereference and ETM save/restore fixes

by Sai Prakash Ranjan

This 2 patch series provides fixes to ETF null pointer dereference crash and TRCVMIDCCTLR1 register save and restore fix. Patch 1 is an RFC since I am not sure of the fix provided since it looks more like a band-aid than the actual fix. Changes in v2: * Remove extra fixes tag (Suzuki) Sai Prakash Ranjan (2): coresight: tmc-etf: Fix NULL pointer dereference in tmc_enable_etf_sink_perf() coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- drivers/hwtracing/coresight/coresight-tmc-etf.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) base-commit: e209e73bee253afe969410150248f0c300c13d84 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 1 month

[PATCH 5.4 159/388] perf cs-etm: Correct synthesizing instruction samples

by Greg Kroah-Hartman

From: Leo Yan <leo.yan(a)linaro.org> [ Upstream commit c9f5baa136777b2c982f6f7a90c9da69a88be148 ] When 'etm->instructions_sample_period' is less than 'tidq->period_instructions', the function cs_etm__sample() cannot handle this case properly with its logic. Let's see below flow as an example: - If we set itrace option '--itrace=i4', then function cs_etm__sample() has variables with initialized values: tidq->period_instructions = 0 etm->instructions_sample_period = 4 - When the first packet is coming: packet->instr_count = 10; the number of instructions executed in this packet is 10, thus update period_instructions as below: tidq->period_instructions = 0 + 10 = 10 instrs_over = 10 - 4 = 6 offset = 10 - 6 - 1 = 3 tidq->period_instructions = instrs_over = 6 - When the second packet is coming: packet->instr_count = 10; in the second pass, assume 10 instructions in the trace sample again: tidq->period_instructions = 6 + 10 = 16 instrs_over = 16 - 4 = 12 offset = 10 - 12 - 1 = -3 -> the negative value tidq->period_instructions = instrs_over = 12 So after handle these two packets, there have below issues: The first issue is that cs_etm__instr_addr() returns the address within the current trace sample of the instruction related to offset, so the offset is supposed to be always unsigned value. But in fact, function cs_etm__sample() might calculate a negative offset value (in handling the second packet, the offset is -3) and pass to cs_etm__instr_addr() with u64 type with a big positive integer. The second issue is it only synthesizes 2 samples for sample period = 4. In theory, every packet has 10 instructions so the two packets have total 20 instructions, 20 instructions should generate 5 samples (4 x 5 = 20). This is because cs_etm__sample() only calls once cs_etm__synth_instruction_sample() to generate instruction sample per range packet. This patch fixes the logic in function cs_etm__sample(); the basic idea for handling coming packet is: - To synthesize the first instruction sample, it combines the left instructions from the previous packet and the head of the new packet; then generate continuous samples with sample period; - At the tail of the new packet, if it has the rest instructions, these instructions will be left for the sequential sample. Suggested-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Reviewed-by: Mike Leach <mike.leach(a)linaro.org> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Robert Walker <robert.walker(a)arm.com> Cc: Suzuki Poulouse <suzuki.poulose(a)arm.com> Cc: coresight ml <coresight(a)lists.linaro.org> Cc: linux-arm-kernel(a)lists.infradead.org Link: http://lore.kernel.org/lkml/20200219021811.20067-4-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- tools/perf/util/cs-etm.c | 87 ++++++++++++++++++++++++++++++++-------- 1 file changed, 70 insertions(+), 17 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 38298cbb07524..451eee24165ee 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1359,9 +1359,12 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, struct cs_etm_auxtrace *etm = etmq->etm; int ret; u8 trace_chan_id = tidq->trace_chan_id; - u64 instrs_executed = tidq->packet->instr_count; + u64 instrs_prev; - tidq->period_instructions += instrs_executed; + /* Get instructions remainder from previous packet */ + instrs_prev = tidq->period_instructions; + + tidq->period_instructions += tidq->packet->instr_count; /* * Record a branch when the last instruction in @@ -1379,26 +1382,76 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, * TODO: allow period to be defined in cycles and clock time */ - /* Get number of instructions executed after the sample point */ - u64 instrs_over = tidq->period_instructions - - etm->instructions_sample_period; + /* + * Below diagram demonstrates the instruction samples + * generation flows: + * + * Instrs Instrs Instrs Instrs + * Sample(n) Sample(n+1) Sample(n+2) Sample(n+3) + * | | | | + * V V V V + * -------------------------------------------------- + * ^ ^ + * | | + * Period Period + * instructions(Pi) instructions(Pi') + * + * | | + * \---------------- -----------------/ + * V + * tidq->packet->instr_count + * + * Instrs Sample(n...) are the synthesised samples occurring + * every etm->instructions_sample_period instructions - as + * defined on the perf command line. Sample(n) is being the + * last sample before the current etm packet, n+1 to n+3 + * samples are generated from the current etm packet. + * + * tidq->packet->instr_count represents the number of + * instructions in the current etm packet. + * + * Period instructions (Pi) contains the the number of + * instructions executed after the sample point(n) from the + * previous etm packet. This will always be less than + * etm->instructions_sample_period. + * + * When generate new samples, it combines with two parts + * instructions, one is the tail of the old packet and another + * is the head of the new coming packet, to generate + * sample(n+1); sample(n+2) and sample(n+3) consume the + * instructions with sample period. After sample(n+3), the rest + * instructions will be used by later packet and it is assigned + * to tidq->period_instructions for next round calculation. + */ /* - * Calculate the address of the sampled instruction (-1 as - * sample is reported as though instruction has just been - * executed, but PC has not advanced to next instruction) + * Get the initial offset into the current packet instructions; + * entry conditions ensure that instrs_prev is less than + * etm->instructions_sample_period. */ - u64 offset = (instrs_executed - instrs_over - 1); - u64 addr = cs_etm__instr_addr(etmq, trace_chan_id, - tidq->packet, offset); + u64 offset = etm->instructions_sample_period - instrs_prev; + u64 addr; - ret = cs_etm__synth_instruction_sample( - etmq, tidq, addr, etm->instructions_sample_period); - if (ret) - return ret; + while (tidq->period_instructions >= + etm->instructions_sample_period) { + /* + * Calculate the address of the sampled instruction (-1 + * as sample is reported as though instruction has just + * been executed, but PC has not advanced to next + * instruction) + */ + addr = cs_etm__instr_addr(etmq, trace_chan_id, + tidq->packet, offset - 1); + ret = cs_etm__synth_instruction_sample( + etmq, tidq, addr, + etm->instructions_sample_period); + if (ret) + return ret; - /* Carry remaining instructions into next sample period */ - tidq->period_instructions = instrs_over; + offset += etm->instructions_sample_period; + tidq->period_instructions -= + etm->instructions_sample_period; + } } if (etm->sample_branches) { -- 2.25.1

6 years, 1 month

[PATCH 5.4 158/388] perf cs-etm: Swap packets for instruction samples

by Greg Kroah-Hartman

From: Leo Yan <leo.yan(a)linaro.org> [ Upstream commit d01751563caf0dec7be36f81de77cc0197b77e59 ] If use option '--itrace=iNNN' with Arm CoreSight trace data, perf tool fails inject instruction samples; the root cause is the packets are only swapped for branch samples and last branches but not for instruction samples, so the new coming packets cannot be properly handled for only synthesizing instruction samples. To fix this issue, this patch refactors the code with a new function cs_etm__packet_swap() which is used to swap packets and adds the condition for instruction samples. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Reviewed-by: Mike Leach <mike.leach(a)linaro.org> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Robert Walker <robert.walker(a)arm.com> Cc: Suzuki Poulouse <suzuki.poulose(a)arm.com> Cc: coresight ml <coresight(a)lists.linaro.org> Cc: linux-arm-kernel(a)lists.infradead.org Link: http://lore.kernel.org/lkml/20200219021811.20067-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- tools/perf/util/cs-etm.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index f5f855fff412e..38298cbb07524 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -363,6 +363,23 @@ struct cs_etm_packet_queue return NULL; } +static void cs_etm__packet_swap(struct cs_etm_auxtrace *etm, + struct cs_etm_traceid_queue *tidq) +{ + struct cs_etm_packet *tmp; + + if (etm->sample_branches || etm->synth_opts.last_branch || + etm->sample_instructions) { + /* + * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for + * the next incoming packet. + */ + tmp = tidq->packet; + tidq->packet = tidq->prev_packet; + tidq->prev_packet = tmp; + } +} + static void cs_etm__packet_dump(const char *pkt_string) { const char *color = PERF_COLOR_BLUE; @@ -1340,7 +1357,6 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, struct cs_etm_traceid_queue *tidq) { struct cs_etm_auxtrace *etm = etmq->etm; - struct cs_etm_packet *tmp; int ret; u8 trace_chan_id = tidq->trace_chan_id; u64 instrs_executed = tidq->packet->instr_count; @@ -1404,15 +1420,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, } } - if (etm->sample_branches || etm->synth_opts.last_branch) { - /* - * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for - * the next incoming packet. - */ - tmp = tidq->packet; - tidq->packet = tidq->prev_packet; - tidq->prev_packet = tmp; - } + cs_etm__packet_swap(etm, tidq); return 0; } @@ -1441,7 +1449,6 @@ static int cs_etm__flush(struct cs_etm_queue *etmq, { int err = 0; struct cs_etm_auxtrace *etm = etmq->etm; - struct cs_etm_packet *tmp; /* Handle start tracing packet */ if (tidq->prev_packet->sample_type == CS_ETM_EMPTY) @@ -1476,15 +1483,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq, } swap_packet: - if (etm->sample_branches || etm->synth_opts.last_branch) { - /* - * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for - * the next incoming packet. - */ - tmp = tidq->packet; - tidq->packet = tidq->prev_packet; - tidq->prev_packet = tmp; - } + cs_etm__packet_swap(etm, tidq); return err; } -- 2.25.1

6 years, 1 month

[PATCH 0/2] Coresight ETF NULL pointer dereference and ETM save/restore fixes

by Sai Prakash Ranjan

This 2 patch series provides fixes to ETF null pointer dereference crash and TRCVMIDCCTLR1 register save and restore fix. Patch 1 is an RFC since I am not sure of the fix provided since it looks more like a band-aid than the actual fix. Sai Prakash Ranjan (2): coresight: tmc-etf: Fix NULL pointer dereference in tmc_enable_etf_sink_perf() coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- drivers/hwtracing/coresight/coresight-tmc-etf.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) base-commit: e209e73bee253afe969410150248f0c300c13d84 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 1 month

ETM save and restore not called for perf mode possibly resulting in bad timestamps.

by Sai Prakash Ranjan

Hello guys, There was an issue reported where the ETM timestamp values would freeze or be 0 sometimes when using perf mode of tracing. This was observed only with perf mode and not sysfs but was reproducible with both ETR and ETF as sinks. After some debugging, I found that it's mostly to do with CPU idle states. For perf mode, I never see entering CPU_PM_ENTER or EXIT(since the check is mode) and so etm4_cpu_save() and restore() are not called and I believe the contexts are not properly saved and restored across low power states leading to these bad timestamp values. For sysfs tracing, I see save and restore called for respective ETMs when CPUs enter low power states. For testing, I would run perf record and report commands in a loop. perf record -e cs_etm/@tmc_etf0/ -N -o perf.data -- some_test perf report -D -i perf.data | grep Timestamp | head On other shell, I would try to suspend the system: echo freeze/mem > /sys/power/state After waking up from suspend, perf commands would continue to run and reports would continue to show either 0 or same timestamps for some period of time. Even the above test does not always reproduce the issue but the observation that save and restore is not called is always consistent with perf cs mode. Any idea as to what might be missing for perf mode or if it is expected or some limitation? Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 1 month

[PATCH v11 00/24] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v10: Rebase to latest coresight-next Protect etmdrvdata[] by modifying it on relevant CPU for ETM3. (Mathieu and Suzuki) -It's not tested. Refine the alignment in coresight makefile. (Mathieu) Add reason for cti_remove_conn_xrefs change. (Mathieu) Set owner for static funnel driver. (Suzuki) Change from v9: Fix warning reported by kernel test robot <lkp(a)intel.com> Rebase to coresight-next Change from v8: Protect etmdrvdata[] by modifying it on relevant CPU (Mathieu and Suzuki) Grab the device before allocating memory for the node (Mathieu) Add author of coresight core driver (Mathieu) Change from v7: Depends on below change for ETM hotplug (Sai) https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash.… Add mutex lock to protect etmdrvdata[] (Suzuki) Add helper function coresight_get_ref() (Suzuki) Reorg replicator and funnel change. Use two patches to support these two drivers. (Suzuki) Add fix tag to "coresight: etm: perf: Fix warning caused by etm_setup_aux failure" (Suzuki) Update author of "coresight: cti: Fix bug clearing sysfs links on callback" Change from v6: Correct module description for CATU (Mike) Check ect_ret equals 0 and set ect_enabled flag (Mike) Add Tested-by and Reviewed-by from Mike Change from v5: Add below CTI clean up change from Mike into series -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Increase module reference count when enabling CTI device (Mike) Change from v4: Fix error handling in coresight_grab_devicei() (Greg) Add coresight: cti: Fix remove sysfs link error from Mike -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html Move cti_remove_conn_xrefs() into cti_remove() (Mike) Align patch subject to coresight: <component>: <description> (Mike) Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (8): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: etm3x: allow etm3x to be built as a module coresight: etm4x: allow etm4x to be built as a module coresight: etb: allow etb to be built as a module coresight: tpiu: allow tpiu to be built as a module coresight: tmc: allow tmc to be built as a module coresight: allow funnel driver to be built as module coresight: allow replicator driver to be built as module Mian Yousaf Kaukab (2): coresight: export global symbols coresight: tmc-etr: add function to register catu ops Mike Leach (2): coresight: cti: Fix remove sysfs link error coresight: cti: Fix bug clearing sysfs links on callback Tingwei Zhang (12): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() coresight: stm: allow to build coresight-stm as a module coresight: etm: perf: Fix warning caused by etm_setup_aux failure coresight: cti: add function to register cti associate ops coresight: cti: don't disable ect device if it's not enabled coresight: cti: increase reference count when enabling cti coresight: cti: allow cti to be built as a module coresight: catu: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 ++++-- drivers/hwtracing/coresight/Makefile | 26 +-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 154 +++++++++++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 67 ++++++-- drivers/hwtracing/coresight/coresight-etb10.c | 28 +++- .../hwtracing/coresight/coresight-etm-perf.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 148 +++++++++++++---- ...resight-etm4x.c => coresight-etm4x-core.c} | 84 +++++++--- .../hwtracing/coresight/coresight-funnel.c | 65 +++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 23 ++- .../coresight/coresight-replicator.c | 65 +++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 25 ++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 20 ++- include/linux/coresight.h | 3 +- 24 files changed, 726 insertions(+), 144 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (92%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (90%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (96%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (95%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

6 years, 1 month

[PATCH AUTOSEL 5.4 165/330] perf cs-etm: Correct synthesizing instruction samples

by Sasha Levin

6 years, 1 month

[PATCH AUTOSEL 5.4 164/330] perf cs-etm: Swap packets for instruction samples

by Sasha Levin

6 years, 1 month

[PATCH] coresight: etm4x: Fix number of resources check for ETM 4.3 and above.

by Mike Leach

The initialisation code checks TRCIDR4 to determine the number of resource selectors available on the system. Since ETM v 4.3, the value 0 has a different meaning. This patch takes into account this change. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 8 +++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 00c9f0bb8b1a..be687276704c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -742,8 +742,14 @@ static void etm4_init_arch_data(void *info) * The number of resource pairs conveyed by the HW starts at 0, i.e a * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. * As such add 1 to the value of NUMRSPAIR for a better representation. + * + * For ETM v4.3 and later, 0x0 means 0, and no pairs are available - + * the default TRUE and FALSE resource selectors are omitted. + * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ - drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1; + drvdata->nr_resource = BMVAL(etmidr4, 16, 19); + if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0)) + drvdata->nr_resource += 1; /* * NUMSSCC, bits[23:20] the number of single-shot * comparator control for tracing. Read any status regs as these diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 5259f96fd28a..eefc7371c6c4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -200,6 +200,9 @@ /* NS MON (EL3) mode never implemented */ #define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) +/* Interpretation of resource numbers change at ETM v4.3 architecture */ +#define ETM4X_ARCH_4V3 0x43 + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. -- 2.17.1

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