On Thu, Sep 10, 2020 at 04:45:52AM +0800, tsoni(a)codeaurora.org wrote:
> On 2020-09-09 09:15, Mathieu Poirier wrote:
> >On Wed, Sep 09, 2020 at 02:54:33AM +0000, Tingwei Zhang wrote:
> >>On Wed, Sep 09, 2020 at 01:53:51AM +0800, Mathieu Poirier wrote:
> >>> Hi Tingwei,
> >>>
> >>> Apologies for the untimely response to this set, I am hoping to get
> to
> >>> it in the next two weeks.
> >>>
> >>
> >>It's fine, Mathieu. Please let me know your comments once you have time.
> >>I'm targeting to get these set merged in 5.10 Kernel.
> >
> >From the above it is not clear if you want this set to be _in_ the 5.10
> >cycle
> >or added to my list _during_ the 5.10 cycle, which would make it part of
> >the
> >5.11 cycle. In any case the latter seems more realistic.
>
> Tingwei can correct me here, but we prefer to have patches to be part of the
> 5.10 release. It means they should get merged in Linus's tree in the next
> merge window.
Yes. The target is to merge this series into Linus's tree in 5.10 Kernel.
Thanks,
Tingwei
>
> ---Trilok Soni
On Wed, Sep 09, 2020 at 02:54:33AM +0000, Tingwei Zhang wrote:
> On Wed, Sep 09, 2020 at 01:53:51AM +0800, Mathieu Poirier wrote:
> > Hi Tingwei,
> >
> > Apologies for the untimely response to this set, I am hoping to get to
> > it in the next two weeks.
> >
>
> It's fine, Mathieu. Please let me know your comments once you have time.
> I'm targeting to get these set merged in 5.10 Kernel.
>From the above it is not clear if you want this set to be _in_ the 5.10 cycle
or added to my list _during_ the 5.10 cycle, which would make it part of the
5.11 cycle. In any case the latter seems more realistic.
>
> > Thanks,
> > Mathieu
> >
> > On Wed, 19 Aug 2020 at 23:47, Tingwei Zhang <tingwei(a)codeaurora.org>
> > wrote:
> > >
> > > Allow to build coresight as modules. This gives developers the
> > feasibility to
> > > test their code without reboot.
> > >
> > > This series is based on below two series.
> > >
> > > - "coresight: allow to build components as modules"
> > > https://lkml.org/lkml/2018/6/5/989
> > > - "coresight: make drivers modular"
> > > https://lkml.org/lkml/2020/1/17/468
> > >
> > > Change from v8:
> > > Protect etmdrvdata[] by modifying it on relevant CPU (Mathieu and
> > Suzuki)
> > > Grab the device before allocating memory for the node (Mathieu)
> > > Add author of coresight core driver (Mathieu)
> > >
> > > Change from v7:
> > > Depends on below change for ETM hotplug (Sai)
> > >
> > https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash
> > .ranjan(a)codeaurora.org/
> > > Add mutex lock to protect etmdrvdata[] (Suzuki)
> > > Add helper function coresight_get_ref() (Suzuki)
> > > Reorg replicator and funnel change. Use two patches to support these
> > > two drivers. (Suzuki)
> > > Add fix tag to "coresight: etm: perf: Fix warning caused by
> > etm_setup_aux
> > > failure" (Suzuki)
> > > Update author of "coresight: cti: Fix bug clearing sysfs links on
> > callback"
> > >
> > > Change from v6:
> > > Correct module description for CATU (Mike)
> > > Check ect_ret equals 0 and set ect_enabled flag (Mike)
> > > Add Tested-by and Reviewed-by from Mike
> > >
> > > Change from v5:
> > > Add below CTI clean up change from Mike into series
> > > -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html
> > > Increase module reference count when enabling CTI device (Mike)
> > >
> > > Change from v4:
> > > Fix error handling in coresight_grab_devicei() (Greg)
> > > Add coresight: cti: Fix remove sysfs link error from Mike
> > > -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html
> > > Move cti_remove_conn_xrefs() into cti_remove() (Mike)
> > > Align patch subject to coresight: <component>: <description> (Mike)
> > >
> > > Change from v3:
> > > Rebase to coresight-next (Mike and Mathieu)
> > > Reorder try_get_module() (Suzuki)
> > > Clean up etmdrvdata[] in device remote path (Mike)
> > > Move cti_remove_conn_xrefs to cti_remove (Mike)
> > >
> > > Change from v2:
> > > Rebase to 5.8-rc5. Export coresight_add_sysfs_link and
> > > coresight_remove_sysfs_link
> > > Fix one cut and paste error on MODULE_DESCRIPTION of CTI
> > >
> > > Change from v1:
> > > Use try_module_get() to avoid module to be unloaded when device is used
> > > in active trace session. (Mathieu P)
> > >
> > > Change from above two series.
> > > This series adds the support to dynamically remove module when the
> > device in
> > > that module is enabled and used by some trace path. It disables all
> > trace
> > > paths with that device and release the trace path.
> > >
> > > Kim Phillips (8):
> > > coresight: use IS_ENABLED for CONFIGs that may be modules
> > > coresight: etm3x: allow etm3x to be built as a module
> > > coresight: etm4x: allow etm4x to be built as a module
> > > coresight: etb: allow etb to be built as a module
> > > coresight: tpiu: allow tpiu to be built as a module
> > > coresight: tmc: allow tmc to be built as a module
> > > coresight: allow funnel driver to be built as module
> > > coresight: allow replicator driver to be built as module
> > >
> > > Mian Yousaf Kaukab (2):
> > > coresight: export global symbols
> > > coresight: tmc-etr: add function to register catu ops
> > >
> > > Mike Leach (2):
> > > coresight: cti: Fix remove sysfs link error
> > > coresight: cti: Fix bug clearing sysfs links on callback
> > >
> > > Tingwei Zhang (12):
> > > coresight: cpu_debug: add module name in Kconfig
> > > coresight: cpu_debug: define MODULE_DEVICE_TABLE
> > > coresight: add coresight prefix to barrier_pkt
> > > coresight: add try_get_module() in coresight_grab_device()
> > > coresight: stm: allow to build coresight-stm as a module
> > > coresight: etm: perf: Fix warning caused by etm_setup_aux failure
> > > coresight: cti: add function to register cti associate ops
> > > coresight: cti: don't disable ect device if it's not enabled
> > > coresight: cti: increase reference count when enabling cti
> > > coresight: cti: allow cti to be built as a module
> > > coresight: catu: allow catu drivers to be built as modules
> > > coresight: allow the coresight core driver to be built as a module
> > >
> > > drivers/hwtracing/coresight/Kconfig | 54 ++++--
> > > drivers/hwtracing/coresight/Makefile | 22 +--
> > > drivers/hwtracing/coresight/coresight-catu.c | 37 ++++-
> > > drivers/hwtracing/coresight/coresight-catu.h | 2 -
> > > .../{coresight.c => coresight-core.c} | 154 +++++++++++++++---
> > > .../hwtracing/coresight/coresight-cpu-debug.c | 2 +
> > > .../{coresight-cti.c => coresight-cti-core.c} | 63 ++++++-
> > > drivers/hwtracing/coresight/coresight-etb10.c | 28 +++-
> > > .../hwtracing/coresight/coresight-etm-perf.c | 13 +-
> > > .../hwtracing/coresight/coresight-etm-perf.h | 5 +-
> > > ...resight-etm3x.c => coresight-etm3x-core.c} | 28 +++-
> > > ...resight-etm4x.c => coresight-etm4x-core.c} | 84 +++++++---
> > > .../hwtracing/coresight/coresight-funnel.c | 64 +++++++-
> > > .../hwtracing/coresight/coresight-platform.c | 1 +
> > > drivers/hwtracing/coresight/coresight-priv.h | 24 ++-
> > > .../coresight/coresight-replicator.c | 65 +++++++-
> > > drivers/hwtracing/coresight/coresight-stm.c | 20 ++-
> > > drivers/hwtracing/coresight/coresight-sysfs.c | 2 +
> > > .../{coresight-tmc.c => coresight-tmc-core.c} | 25 ++-
> > > .../hwtracing/coresight/coresight-tmc-etf.c | 2 +-
> > > .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++-
> > > drivers/hwtracing/coresight/coresight-tmc.h | 3 +
> > > drivers/hwtracing/coresight/coresight-tpiu.c | 20 ++-
> > > include/linux/coresight.h | 3 +-
> > > 24 files changed, 634 insertions(+), 108 deletions(-)
> > > rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c}
> > (92%)
> > > rename drivers/hwtracing/coresight/{coresight-cti.c =>
> > coresight-cti-core.c} (94%)
> > > rename drivers/hwtracing/coresight/{coresight-etm3x.c =>
> > coresight-etm3x-core.c} (97%)
> > > rename drivers/hwtracing/coresight/{coresight-etm4x.c =>
> > coresight-etm4x-core.c} (96%)
> > > rename drivers/hwtracing/coresight/{coresight-tmc.c =>
> > coresight-tmc-core.c} (95%)
> > >
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel(a)lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Mike,
On Mon, 7 Sep 2020 at 10:52, Mike Leach <mike.leach(a)linaro.org> wrote:
>
> Hi,
>
> On Thu, 3 Sep 2020 at 18:42, Mathieu Poirier <mathieu.poirier(a)linaro.org> wrote:
> >
> > On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote:
> > > The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid
> > > accessing the reserved register.
> > >
> > > Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
> > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
> > > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com>
> > > Cc: Mike Leach <mike.leach(a)linaro.org>
> > > Cc: Shaokun Zhang <zhangshaokun(a)hisilicon.com>
> > > Cc: lizixian(a)hisilicon.com
> > >
> > > Signed-off-by: Jonathan Zhou <jonathan.zhouwen(a)huawei.com>
> > > ---
> > > drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > index 96425e818fc2..44e44c817bf8 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > > state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
> > > state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
> > >
> > > - for (i = 0; i < drvdata->nrseqstate; i++)
> > > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
> >
> > The section 3.4.3 "Guidelines for trace unit registers to be saved and restored"
> > of the ETM4 Architecture Specification (ARM IHI0064F ID042818) is clear on the
> > fact that registers TRCSEQEVR0-3 have to be taken into account when saving the
>
> I think this is a typo in the TRM. I'll ping the docs people in ARM.
Did you get an answer from the document people? Is this really a
typographical problem?
Thanks,
Mathieu
>
> > trace unit state.
> >
>
> Looking @ the register descriptions for TRCSEQEVRn (7.3.63) in the
> above document n=0-2.
> The number of states is set by TRCIDR5.NUMSEQSTATE (7.3.35). This can
> take the value 0 or 4.
> If 4 then there are 3 TRCSEQEVR(n) registers - 0 to 2 - one for each
> state transition.
>
> Thus this patch is correct in using nrseqstate - 1.
>
> Regards
>
> Mike
>
> > Thanks,
> > Mathieu
> >
> > >
> > > state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
> > > @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> > > writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
> > > writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
> > >
> > > - for (i = 0; i < drvdata->nrseqstate; i++)
> > > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > writel_relaxed(state->trcseqevr[i],
> > > drvdata->base + TRCSEQEVRn(i));
> > > --
> > > 1.9.1
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
Allow to build coresight as modules. This gives developers the feasibility to
test their code without reboot.
This series is based on below two series.
- "coresight: allow to build components as modules"
https://lkml.org/lkml/2018/6/5/989
- "coresight: make drivers modular"
https://lkml.org/lkml/2020/1/17/468
Change from v8:
Protect etmdrvdata[] by modifying it on relevant CPU (Mathieu and Suzuki)
Grab the device before allocating memory for the node (Mathieu)
Add author of coresight core driver (Mathieu)
Change from v7:
Depends on below change for ETM hotplug (Sai)
https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash.…
Add mutex lock to protect etmdrvdata[] (Suzuki)
Add helper function coresight_get_ref() (Suzuki)
Reorg replicator and funnel change. Use two patches to support these
two drivers. (Suzuki)
Add fix tag to "coresight: etm: perf: Fix warning caused by etm_setup_aux
failure" (Suzuki)
Update author of "coresight: cti: Fix bug clearing sysfs links on callback"
Change from v6:
Correct module description for CATU (Mike)
Check ect_ret equals 0 and set ect_enabled flag (Mike)
Add Tested-by and Reviewed-by from Mike
Change from v5:
Add below CTI clean up change from Mike into series
-https://lists.linaro.org/pipermail/coresight/2020-July/004349.html
Increase module reference count when enabling CTI device (Mike)
Change from v4:
Fix error handling in coresight_grab_devicei() (Greg)
Add coresight: cti: Fix remove sysfs link error from Mike
-https://lists.linaro.org/pipermail/coresight/2020-July/004275.html
Move cti_remove_conn_xrefs() into cti_remove() (Mike)
Align patch subject to coresight: <component>: <description> (Mike)
Change from v3:
Rebase to coresight-next (Mike and Mathieu)
Reorder try_get_module() (Suzuki)
Clean up etmdrvdata[] in device remote path (Mike)
Move cti_remove_conn_xrefs to cti_remove (Mike)
Change from v2:
Rebase to 5.8-rc5. Export coresight_add_sysfs_link and
coresight_remove_sysfs_link
Fix one cut and paste error on MODULE_DESCRIPTION of CTI
Change from v1:
Use try_module_get() to avoid module to be unloaded when device is used
in active trace session. (Mathieu P)
Change from above two series.
This series adds the support to dynamically remove module when the device in
that module is enabled and used by some trace path. It disables all trace
paths with that device and release the trace path.
Kim Phillips (8):
coresight: use IS_ENABLED for CONFIGs that may be modules
coresight: etm3x: allow etm3x to be built as a module
coresight: etm4x: allow etm4x to be built as a module
coresight: etb: allow etb to be built as a module
coresight: tpiu: allow tpiu to be built as a module
coresight: tmc: allow tmc to be built as a module
coresight: allow funnel driver to be built as module
coresight: allow replicator driver to be built as module
Mian Yousaf Kaukab (2):
coresight: export global symbols
coresight: tmc-etr: add function to register catu ops
Mike Leach (2):
coresight: cti: Fix remove sysfs link error
coresight: cti: Fix bug clearing sysfs links on callback
Tingwei Zhang (12):
coresight: cpu_debug: add module name in Kconfig
coresight: cpu_debug: define MODULE_DEVICE_TABLE
coresight: add coresight prefix to barrier_pkt
coresight: add try_get_module() in coresight_grab_device()
coresight: stm: allow to build coresight-stm as a module
coresight: etm: perf: Fix warning caused by etm_setup_aux failure
coresight: cti: add function to register cti associate ops
coresight: cti: don't disable ect device if it's not enabled
coresight: cti: increase reference count when enabling cti
coresight: cti: allow cti to be built as a module
coresight: catu: allow catu drivers to be built as modules
coresight: allow the coresight core driver to be built as a module
drivers/hwtracing/coresight/Kconfig | 54 ++++--
drivers/hwtracing/coresight/Makefile | 22 +--
drivers/hwtracing/coresight/coresight-catu.c | 37 ++++-
drivers/hwtracing/coresight/coresight-catu.h | 2 -
.../{coresight.c => coresight-core.c} | 154 +++++++++++++++---
.../hwtracing/coresight/coresight-cpu-debug.c | 2 +
.../{coresight-cti.c => coresight-cti-core.c} | 63 ++++++-
drivers/hwtracing/coresight/coresight-etb10.c | 28 +++-
.../hwtracing/coresight/coresight-etm-perf.c | 13 +-
.../hwtracing/coresight/coresight-etm-perf.h | 5 +-
...resight-etm3x.c => coresight-etm3x-core.c} | 28 +++-
...resight-etm4x.c => coresight-etm4x-core.c} | 84 +++++++---
.../hwtracing/coresight/coresight-funnel.c | 64 +++++++-
.../hwtracing/coresight/coresight-platform.c | 1 +
drivers/hwtracing/coresight/coresight-priv.h | 24 ++-
.../coresight/coresight-replicator.c | 65 +++++++-
drivers/hwtracing/coresight/coresight-stm.c | 20 ++-
drivers/hwtracing/coresight/coresight-sysfs.c | 2 +
.../{coresight-tmc.c => coresight-tmc-core.c} | 25 ++-
.../hwtracing/coresight/coresight-tmc-etf.c | 2 +-
.../hwtracing/coresight/coresight-tmc-etr.c | 21 ++-
drivers/hwtracing/coresight/coresight-tmc.h | 3 +
drivers/hwtracing/coresight/coresight-tpiu.c | 20 ++-
include/linux/coresight.h | 3 +-
24 files changed, 634 insertions(+), 108 deletions(-)
rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (92%)
rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%)
rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%)
rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (96%)
rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (95%)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
If the specified/hinted sink is not reachable from a subset of the CPUs,
we could end up unable to trace the event on those CPUs. This
is the best effort we could do until we support 1:1 configurations.
Fail gracefully in such cases avoiding a WARN_ON, which can be easily
triggered by the user on certain platforms (Arm N1SDP), with the following
trace paths :
CPU0
\
-- Funnel0 --> ETF0 -->
/ \
CPU1 \
MainFunnel
CPU2 /
\ /
-- Funnel1 --> ETF1 -->
/
CPU1
$ perf record --per-thread -e cs_etm/@ETF0/u -- <app>
could trigger the following WARNING, when the event is scheduled
on CPU2.
[10919.513250] ------------[ cut here ]------------
[10919.517861] WARNING: CPU: 2 PID: 24021 at
drivers/hwtracing/coresight/coresight-etm-perf.c:316 etm_event_start+0xf8/0x100
...
[10919.564403] CPU: 2 PID: 24021 Comm: perf Not tainted 5.8.0+ #24
[10919.570308] pstate: 80400089 (Nzcv daIf +PAN -UAO BTYPE=--)
[10919.575865] pc : etm_event_start+0xf8/0x100
[10919.580034] lr : etm_event_start+0x80/0x100
[10919.584202] sp : fffffe001932f940
[10919.587502] x29: fffffe001932f940 x28: fffffc834995f800
[10919.592799] x27: 0000000000000000 x26: fffffe0011f3ced0
[10919.598095] x25: fffffc837fce244c x24: fffffc837fce2448
[10919.603391] x23: 0000000000000002 x22: fffffc8353529c00
[10919.608688] x21: fffffc835bb31000 x20: 0000000000000000
[10919.613984] x19: fffffc837fcdcc70 x18: 0000000000000000
[10919.619281] x17: 0000000000000000 x16: 0000000000000000
[10919.624577] x15: 0000000000000000 x14: 00000000000009f8
[10919.629874] x13: 00000000000009f8 x12: 0000000000000018
[10919.635170] x11: 0000000000000000 x10: 0000000000000000
[10919.640467] x9 : fffffe00108cd168 x8 : 0000000000000000
[10919.645763] x7 : 0000000000000020 x6 : 0000000000000001
[10919.651059] x5 : 0000000000000002 x4 : 0000000000000001
[10919.656356] x3 : 0000000000000000 x2 : 0000000000000000
[10919.661652] x1 : fffffe836eb40000 x0 : 0000000000000000
[10919.666949] Call trace:
[10919.669382] etm_event_start+0xf8/0x100
[10919.673203] etm_event_add+0x40/0x60
[10919.676765] event_sched_in.isra.134+0xcc/0x210
[10919.681281] merge_sched_in+0xb0/0x2a8
[10919.685017] visit_groups_merge.constprop.140+0x15c/0x4b8
[10919.690400] ctx_sched_in+0x15c/0x170
[10919.694048] perf_event_sched_in+0x6c/0xa0
[10919.698130] ctx_resched+0x60/0xa0
[10919.701517] perf_event_exec+0x288/0x2f0
[10919.705425] begin_new_exec+0x4c8/0xf58
[10919.709247] load_elf_binary+0x66c/0xf30
[10919.713155] exec_binprm+0x15c/0x450
[10919.716716] __do_execve_file+0x508/0x748
[10919.720711] __arm64_sys_execve+0x40/0x50
[10919.724707] do_el0_svc+0xf4/0x1b8
[10919.728095] el0_sync_handler+0xf8/0x124
[10919.732003] el0_sync+0x140/0x180
Even though we don't support using separate sinks for the ETMs yet (e.g,
for 1:1 configurations), we should at least honor the user's choice and
handle the limitations gracefully, by simply skipping the tracing on ETMs
which can't reach the requested sink.
Fixes: f9d81a657bb8 ("coresight: perf: Allow tracing on hotplugged CPUs")
Reported-by: Jeremy Linton <jeremy.linton(a)arm.com>
Tested-by: Jeremy Linton <jeremy.linton(a)arm.com>
Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
Cc: Mike Leach <mike.leach(a)linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
---
Change since v1:
- Updated the description, added Tested-by.
- No code changes
- Rebased on coresight/next
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 1a3169e69bb1..9d61a71da96f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -321,6 +321,16 @@ static void etm_event_start(struct perf_event *event, int flags)
if (!event_data)
goto fail;
+ /*
+ * Check if this ETM is allowed to trace, as decided
+ * at etm_setup_aux(). This could be due to an unreachable
+ * sink from this ETM. We can't do much in this case if
+ * the sink was specified or hinted to the driver. For
+ * now, simply don't record anything on this ETM.
+ */
+ if (!cpumask_test_cpu(cpu, &event_data->mask))
+ goto fail_end_stop;
+
path = etm_event_cpu_path(event_data, cpu);
/* We need a sink, no need to continue without one */
sink = coresight_get_sink(path);
--
2.24.1
If the specified/hinted sink is not reachable from a subset of the CPUs,
we could end up unable to trace the event on those CPUs. This
is the best effort we could do until we support 1:1 configurations.
Fail gracefully in such cases avoiding a WARN_ON, which can be easily
triggered by the user on certain platforms, like :
[10919.513250] ------------[ cut here ]------------
[10919.517861] WARNING: CPU: 2 PID: 24021 at
drivers/hwtracing/coresight/coresight-etm-perf.c:316 etm_event_start+0xf8/0x100
...
[10919.564403] CPU: 2 PID: 24021 Comm: perf Not tainted 5.8.0+ #24
[10919.570308] pstate: 80400089 (Nzcv daIf +PAN -UAO BTYPE=--)
[10919.575865] pc : etm_event_start+0xf8/0x100
[10919.580034] lr : etm_event_start+0x80/0x100
[10919.584202] sp : fffffe001932f940
[10919.587502] x29: fffffe001932f940 x28: fffffc834995f800
[10919.592799] x27: 0000000000000000 x26: fffffe0011f3ced0
[10919.598095] x25: fffffc837fce244c x24: fffffc837fce2448
[10919.603391] x23: 0000000000000002 x22: fffffc8353529c00
[10919.608688] x21: fffffc835bb31000 x20: 0000000000000000
[10919.613984] x19: fffffc837fcdcc70 x18: 0000000000000000
[10919.619281] x17: 0000000000000000 x16: 0000000000000000
[10919.624577] x15: 0000000000000000 x14: 00000000000009f8
[10919.629874] x13: 00000000000009f8 x12: 0000000000000018
[10919.635170] x11: 0000000000000000 x10: 0000000000000000
[10919.640467] x9 : fffffe00108cd168 x8 : 0000000000000000
[10919.645763] x7 : 0000000000000020 x6 : 0000000000000001
[10919.651059] x5 : 0000000000000002 x4 : 0000000000000001
[10919.656356] x3 : 0000000000000000 x2 : 0000000000000000
[10919.661652] x1 : fffffe836eb40000 x0 : 0000000000000000
[10919.666949] Call trace:
[10919.669382] etm_event_start+0xf8/0x100
[10919.673203] etm_event_add+0x40/0x60
[10919.676765] event_sched_in.isra.134+0xcc/0x210
[10919.681281] merge_sched_in+0xb0/0x2a8
[10919.685017] visit_groups_merge.constprop.140+0x15c/0x4b8
[10919.690400] ctx_sched_in+0x15c/0x170
[10919.694048] perf_event_sched_in+0x6c/0xa0
[10919.698130] ctx_resched+0x60/0xa0
[10919.701517] perf_event_exec+0x288/0x2f0
[10919.705425] begin_new_exec+0x4c8/0xf58
[10919.709247] load_elf_binary+0x66c/0xf30
[10919.713155] exec_binprm+0x15c/0x450
[10919.716716] __do_execve_file+0x508/0x748
[10919.720711] __arm64_sys_execve+0x40/0x50
[10919.724707] do_el0_svc+0xf4/0x1b8
[10919.728095] el0_sync_handler+0xf8/0x124
[10919.732003] el0_sync+0x140/0x180
Fixes: f9d81a657bb8 ("coresight: perf: Allow tracing on hotplugged CPUs")
Reported-by: Jeremy Linton <jeremy.linton(a)arm.com>
Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
Cc: Mike Leach <mike.leach(a)linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 1a3169e69bb1..9d61a71da96f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -321,6 +321,16 @@ static void etm_event_start(struct perf_event *event, int flags)
if (!event_data)
goto fail;
+ /*
+ * Check if this ETM is allowed to trace, as decided
+ * at etm_setup_aux(). This could be due to an unreachable
+ * sink from this ETM. We can't do much in this case if
+ * the sink was specified or hinted to the driver. For
+ * now, simply don't record anything on this ETM.
+ */
+ if (!cpumask_test_cpu(cpu, &event_data->mask))
+ goto fail_end_stop;
+
path = etm_event_cpu_path(event_data, cpu);
/* We need a sink, no need to continue without one */
sink = coresight_get_sink(path);
--
2.24.1
I compile coresight and perf on my dragonboard 410c.
I have disabled user address space randomization.
I run my application program under perf, and then run `perf script`.
The address perf+opencoresight prints for main is: aaaaaaaaa910 main+0x0 (nm on the application program says the address for main is 0x910).
Why does perf+coresight change the leading hexits in the printed address from 0 to 'a'?
Is there a way to disable this behavior?
Is this behavior documented anywhere?
Many thanks,
Robert Henry
