CoreSight

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2384 discussions

[PATCH] coresight: Add a KUnit test for coresight_find_default_sink()

by James Clark

Add a test to confirm that default sink selection skips over an ETF and returns an ETR even if it's further away. This also makes it easier to add new unit tests in the future. Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/Kconfig | 9 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 1 + .../coresight/coresight-kunit-tests.c | 90 +++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-kunit-tests.c diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169..056d04bc540a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -247,4 +247,13 @@ config CORESIGHT_DUMMY To compile this driver as a module, choose M here: the module will be called coresight-dummy. + +config CORESIGHT_KUNIT_TESTS + tristate "Enable Coresight unit tests" + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable Coresight unit tests. Only useful for development and not + intended for production. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..c170a41b3056 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o +obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ea38ecf26fcb..ce63b68d5503 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -869,6 +869,7 @@ coresight_find_default_sink(struct coresight_device *csdev) } return csdev->def_sink; } +EXPORT_SYMBOL_GPL(coresight_find_default_sink); static int coresight_remove_sink_ref(struct device *dev, void *data) { diff --git a/drivers/hwtracing/coresight/coresight-kunit-tests.c b/drivers/hwtracing/coresight/coresight-kunit-tests.c new file mode 100644 index 000000000000..d022bacc8357 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-kunit-tests.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <kunit/test.h> +#include <kunit/device.h> +#include <linux/coresight.h> + +#include "coresight-priv.h" + +static struct coresight_device *coresight_test_device(struct device *dev) +{ + struct coresight_device *csdev = devm_kcalloc(dev, 1, + sizeof(struct coresight_device), + GFP_KERNEL); + csdev->pdata = devm_kcalloc(dev, 1, + sizeof(struct coresight_platform_data), + GFP_KERNEL); + return csdev; +} + +static void coresight_free_test_device(struct device *dev, + struct coresight_device *csdev) +{ + devm_kfree(dev, csdev->pdata->out_conns); + devm_kfree(dev, csdev->pdata); + devm_kfree(dev, csdev); +} + +static int coresight_test_cpuid(struct coresight_device *csdev) +{ + return 0; +} + +static void test_default_sink(struct kunit *test) +{ + /* + * ETM -> ETF -> ETR -> CATU + * ^ + * | default + */ + struct device *dev = kunit_device_register(test, "coresight_kunit"); + struct coresight_device *etm = coresight_test_device(dev), + *etf = coresight_test_device(dev), + *etr = coresight_test_device(dev), + *catu = coresight_test_device(dev); + struct coresight_connection conn = {}; + struct coresight_ops_source src_ops = {.cpu_id = coresight_test_cpuid }; + struct coresight_ops etm_cs_ops = { .source_ops = &src_ops }; + + etm->type = CORESIGHT_DEV_TYPE_SOURCE; + etm->ops = &etm_cs_ops; + etf->type = CORESIGHT_DEV_TYPE_LINKSINK; + etf->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + etr->type = CORESIGHT_DEV_TYPE_SINK; + etr->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; + catu->type = CORESIGHT_DEV_TYPE_HELPER; + + conn.src_dev = etm; + conn.dest_dev = etf; + coresight_add_out_conn(dev, etm->pdata, &conn); + + conn.src_dev = etf; + conn.dest_dev = etr; + coresight_add_out_conn(dev, etf->pdata, &conn); + + conn.src_dev = etr; + conn.dest_dev = catu; + coresight_add_out_conn(dev, etr->pdata, &conn); + + KUNIT_ASSERT_PTR_EQ(test, coresight_find_default_sink(etm), etr); + + coresight_free_test_device(dev, etm); + coresight_free_test_device(dev, etf); + coresight_free_test_device(dev, etr); + coresight_free_test_device(dev, catu); +} + +static struct kunit_case coresight_testcases[] = { + KUNIT_CASE(test_default_sink), + {} +}; + +static struct kunit_suite coresight_test_suite = { + .name = "coresight_test_suite", + .test_cases = coresight_testcases, +}; + +kunit_test_suites(&coresight_test_suite); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("James Clark <james.clark(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight KUnit tests"); -- 2.34.1

3 months, 4 weeks

Re: [PATCH v15 02/10] Coresight: Add trace_id function to retrieving the trace ID

by Mike Leach

Hi, On Mon, 3 Mar 2025 at 03:30, Jie Gan <quic_jiegan(a)quicinc.com> wrote: > > Add 'trace_id' function pointer in coresight_ops. It's responsible for retrieving > the device's trace ID. > > Co-developed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: James Clark <james.clark(a)linaro.org> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 30 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-dummy.c | 13 +++++++- > .../coresight/coresight-etm3x-core.c | 1 + > .../coresight/coresight-etm4x-core.c | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 11 +++++++ > drivers/hwtracing/coresight/coresight-tpda.c | 11 +++++++ > include/linux/coresight.h | 5 ++++ > 7 files changed, 71 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index ab55e10d4b79..32aa07f4f8c1 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -24,6 +24,7 @@ > #include "coresight-etm-perf.h" > #include "coresight-priv.h" > #include "coresight-syscfg.h" > +#include "coresight-trace-id.h" > > /* > * Mutex used to lock all sysfs enable and disable actions and loading and > @@ -1557,6 +1558,35 @@ void coresight_remove_driver(struct amba_driver *amba_drv, > } > EXPORT_SYMBOL_GPL(coresight_remove_driver); > > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink) > +{ > + int trace_id; > + int cpu = source_ops(csdev)->cpu_id(csdev); > + This is a global funciton so need to check that this csdev is a source,. and does provide a cpu function before calling it. > + switch (mode) { > + case CS_MODE_SYSFS: > + trace_id = coresight_trace_id_get_cpu_id(cpu); > + break; > + case CS_MODE_PERF: > + if (WARN_ON(!sink)) > + return -EINVAL; > + > + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > + break; > + default: > + trace_id = -EINVAL; > + break; > + } > + > + if (!IS_VALID_CS_TRACE_ID(trace_id)) > + dev_err(&csdev->dev, > + "Failed to allocate trace ID on CPU%d\n", cpu); > + > + return trace_id; > +} > +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id); > + > MODULE_LICENSE("GPL v2"); > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); > diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > index 9be53be8964b..b5692ba358c1 100644 > --- a/drivers/hwtracing/coresight/coresight-dummy.c > +++ b/drivers/hwtracing/coresight/coresight-dummy.c > @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev, > dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); > } > > +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct dummy_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, > void *data) > { > @@ -62,7 +72,8 @@ static const struct coresight_ops_source dummy_source_ops = { > }; > > static const struct coresight_ops dummy_source_cs_ops = { > - .source_ops = &dummy_source_ops, > + .trace_id = dummy_source_trace_id, > + .source_ops = &dummy_source_ops, > }; > > static const struct coresight_ops_sink dummy_sink_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index c103f4c70f5d..c1dda4bc4a2f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -704,6 +704,7 @@ static const struct coresight_ops_source etm_source_ops = { > }; > > static const struct coresight_ops etm_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 2c1a60577728..cfd116b87460 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1067,6 +1067,7 @@ static const struct coresight_ops_source etm4_source_ops = { > }; > > static const struct coresight_ops etm4_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm4_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index b581a30a1cd9..aca25b5e3be2 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -281,12 +281,23 @@ static void stm_disable(struct coresight_device *csdev, > } > } > > +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct stm_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static const struct coresight_ops_source stm_source_ops = { > .enable = stm_enable, > .disable = stm_disable, > }; > > static const struct coresight_ops stm_cs_ops = { > + .trace_id = stm_trace_id, > .source_ops = &stm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 573da8427428..94c2201fc8d3 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -241,12 +241,23 @@ static void tpda_disable(struct coresight_device *csdev, > dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); > } > > +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct tpda_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->atid; > +} > + > static const struct coresight_ops_link tpda_link_ops = { > .enable = tpda_enable, > .disable = tpda_disable, > }; > > static const struct coresight_ops tpda_cs_ops = { > + .trace_id = tpda_trace_id, > .link_ops = &tpda_link_ops, > }; > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index c7cd5886c908..ce9a5e71b261 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -335,6 +335,7 @@ enum cs_mode { > CS_MODE_PERF, > }; > > +#define coresight_ops(csdev) csdev->ops > #define source_ops(csdev) csdev->ops->source_ops > #define sink_ops(csdev) csdev->ops->sink_ops > #define link_ops(csdev) csdev->ops->link_ops > @@ -421,6 +422,8 @@ struct coresight_ops_panic { > }; > > struct coresight_ops { > + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > const struct coresight_ops_sink *sink_ops; > const struct coresight_ops_link *link_ops; > const struct coresight_ops_source *source_ops; > @@ -709,4 +712,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, > > void coresight_remove_driver(struct amba_driver *amba_drv, > struct platform_driver *pdev_drv); > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > #endif /* _LINUX_COREISGHT_H */ > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months, 4 weeks

Re: [PATCH v15 00/10] [subset] Coresight: Add Coresight TMC Control Unit driver

by Suzuki K Poulose

On Mon, 03 Mar 2025 11:29:21 +0800, Jie Gan wrote: > The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration > registers to control various features related to TMC ETR device. > > The CTCU device works as a helper device physically connected to the TMC ETR device. > --------------------------------------------------------- > |ETR0| |ETR1| > . \ / . > . \ / . > . \ / . > . \ / . > --------------------------------------------------- > ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3 > --------------------------------------------------- > Each ETR has four ATID registers with 128 bits long in total. > e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device. > > [...] I have applied patches 1-9, leaving the DTS update for the platform. [01/10] Coresight: Add support for new APB clock name https://git.kernel.org/coresight/c/dc872c5f [02/10] Coresight: Add trace_id function to retrieving the trace ID https://git.kernel.org/coresight/c/c367a89d [03/10] Coresight: Use coresight_etm_get_trace_id() in traceid_show() https://git.kernel.org/coresight/c/182e8c70 [04/10] Coresight: Introduce a new struct coresight_path https://git.kernel.org/coresight/c/3c03c49b [05/10] Coresight: Allocate trace ID after building the path https://git.kernel.org/coresight/c/d87d76d8 [06/10] Coresight: Change to read the trace ID from coresight_path https://git.kernel.org/coresight/c/7b365f05 [07/10] Coresight: Change functions to accept the coresight_path https://git.kernel.org/coresight/c/080ee83c [08/10] dt-bindings: arm: Add Coresight TMC Control Unit hardware https://git.kernel.org/coresight/c/166df2a1 [09/10] Coresight: Add Coresight TMC Control Unit driver https://git.kernel.org/coresight/c/f78d206f Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 months, 4 weeks

Re: [PATCH v15 04/10] Coresight: Introduce a new struct coresight_path

by Suzuki K Poulose

On 03/03/2025 03:29, Jie Gan wrote: > Introduce a new strcuture, 'struct coresight_path', to store the data that > utilized by the devices in the path. The coresight_path will be built/released > by coresight_build_path/coresight_release_path functions. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 16 +++++----- > .../hwtracing/coresight/coresight-etm-perf.c | 30 ++++++++++--------- > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > drivers/hwtracing/coresight/coresight-priv.h | 6 ++-- > drivers/hwtracing/coresight/coresight-sysfs.c | 12 ++++---- > include/linux/coresight.h | 10 +++++++ > 6 files changed, 44 insertions(+), 32 deletions(-) > ... > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index ce9a5e71b261..67cf8bdbe5c0 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \ > > #define to_coresight_device(d) container_of(d, struct coresight_device, dev) > > +/** > + * struct coresight_path - data needed by enable/disable path > + * @path: path from source to sink. This doesn't match the actual variable below. > + * @trace_id: trace_id of the whole path. > + */ > +struct coresight_path { > + struct list_head path_list; > + u8 trace_id; > +}; > + > enum cs_mode { > CS_MODE_DISABLED, > CS_MODE_SYSFS, Suzuki

3 months, 4 weeks

Re: [PATCH v15 09/10] Coresight: Add Coresight TMC Control Unit driver

by Suzuki K Poulose

On 03/03/2025 03:29, Jie Gan wrote: > The Coresight TMC Control Unit hosts miscellaneous configuration registers > which control various features related to TMC ETR sink. > > Based on the trace ID, which is programmed in the related CTCU ATID > register of a specific ETR, trace data with that trace ID gets into > the ETR buffer, while other trace data gets dropped. > > Enabling source device sets one bit of the ATID register based on > source device's trace ID. > Disabling source device resets the bit according to the source > device's trace ID. > > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> ... > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu.h > @@ -0,0 +1,39 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _CORESIGHT_CTCU_H > +#define _CORESIGHT_CTCU_H > +#include "coresight-trace-id.h" > + > +/* Maximum number of supported ETR devices for a single CTCU. */ > +#define ETR_MAX_NUM 2 > + WARNING: please, no space before tabs #413: FILE: drivers/hwtracing/coresight/coresight-ctcu.h:11: +#define ETR_MAX_NUM ^I2$ total: 0 errors, 2 warnings, 397 lines checked Another checkpatch warning. Please take care in the future. Suzuki

3 months, 4 weeks

Re: [PATCH v15 05/10] Coresight: Allocate trace ID after building the path

by Suzuki K Poulose

On 03/03/2025 03:29, Jie Gan wrote: > The trace_id will be stored in coresight_path instead of being declared > everywhere and allocated after building the path. > > Co-developed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 44 +++++++++++++++++++ > .../hwtracing/coresight/coresight-etm-perf.c | 5 +-- > drivers/hwtracing/coresight/coresight-priv.h | 2 + > drivers/hwtracing/coresight/coresight-sysfs.c | 4 ++ > 4 files changed, 52 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index ed0e9368324d..6adc06995d76 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -655,6 +655,50 @@ static void coresight_drop_device(struct coresight_device *csdev) > } > } > > +/* > + * coresight device will read their existing or alloc a trace ID, if their trace_id > + * callback is set. > + * > + * Return 0 if the trace_id callback is not set. > + * Return the result of the trace_id callback if it is set. The return value > + * will be the trace_id if successful, and an error number if it fails. > + */ > +static int coresight_get_trace_id(struct coresight_device *csdev, > + enum cs_mode mode, > + struct coresight_device *sink) > +{ > + if (coresight_ops(csdev)->trace_id) > + return coresight_ops(csdev)->trace_id(csdev, mode, sink); > + > + return 0; > +} > + > +/* > + * Call this after creating the path and before enabling it. This leaves > + * the trace ID set on the path, or it remains 0 if it couldn't be assigned. > + */ > +void coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode) > +{ > + struct coresight_device *sink = coresight_get_sink(&path->path_list); > + struct coresight_node *nd; > + int trace_id; > + > + list_for_each_entry(nd, &path->path_list, link) { > + /* Assign a trace ID to the path for the first device that wants to do it */ > + trace_id = coresight_get_trace_id(nd->csdev, mode, sink); > + > + /* > + * 0 in this context is that it didn't want to assign so keep searching. > + * Non 0 is either success or fail. > + */ checkpatch complains: WARNING: Block comments should align the * on each line #65: FILE: drivers/hwtracing/coresight/coresight-core.c:694: + * Non 0 is either success or fail. + */ Please make sure to run the checkpatch on individual patches before submitting in the future. I will fix this up locally for now. Kind regards Suzuki > + if (trace_id != 0) { > + path->trace_id = trace_id; > + return; > + } > + } > +} > + > /** > * _coresight_build_path - recursively build a path from a @csdev to a sink. > * @csdev: The device to start from. > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index b0426792f08a..134290ab622e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -319,7 +319,6 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > { > u32 id, cfg_hash; > int cpu = event->cpu; > - int trace_id; > cpumask_t *mask; > struct coresight_device *sink = NULL; > struct coresight_device *user_sink = NULL, *last_sink = NULL; > @@ -409,8 +408,8 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > } > > /* ensure we can allocate a trace ID for this CPU */ > - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > - if (!IS_VALID_CS_TRACE_ID(trace_id)) { > + coresight_path_assign_trace_id(path, CS_MODE_PERF); > + if (!IS_VALID_CS_TRACE_ID(path->trace_id)) { > cpumask_clear_cpu(cpu, mask); > coresight_release_path(path); > continue; > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 27b7dc348d4a..2bea35bae0d4 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig, > void coresight_remove_links(struct coresight_device *orig, > struct coresight_connection *conn); > u32 coresight_get_sink_id(struct coresight_device *csdev); > +void coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode); > > #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) > extern int etm_readl_cp14(u32 off, unsigned int *val); > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index cb4c39732d26..d03751bf3d8a 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -209,6 +209,10 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > goto out; > } > > + coresight_path_assign_trace_id(path, CS_MODE_SYSFS); > + if (!IS_VALID_CS_TRACE_ID(path->trace_id)) > + goto err_path; > + > ret = coresight_enable_path(&path->path_list, CS_MODE_SYSFS, NULL); > if (ret) > goto err_path;

3 months, 4 weeks

Re: [PATCH v15 10/10] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes

by Suzuki K Poulose

On 03/03/2025 03:29, Jie Gan wrote: > Add CTCU and ETR nodes in DT to enable related functionalities. > > Reviewed-by: Konrad Dybcio <konrad.dybcio(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> Assuming this goes via the soc tree, Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++ > 1 file changed, 153 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 3394ae2d1300..31aa94d2a043 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -2429,6 +2429,35 @@ crypto: crypto@1dfa000 { > interconnect-names = "memory"; > }; > > + ctcu@4001000 { > + compatible = "qcom,sa8775p-ctcu"; > + reg = <0x0 0x04001000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + ctcu_in0: endpoint { > + remote-endpoint = <&etr0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + ctcu_in1: endpoint { > + remote-endpoint = <&etr1_out>; > + }; > + }; > + }; > + }; > + > stm: stm@4002000 { > compatible = "arm,coresight-stm", "arm,primecell"; > reg = <0x0 0x4002000 0x0 0x1000>, > @@ -2633,6 +2662,122 @@ qdss_funnel_in1: endpoint { > }; > }; > > + replicator@4046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x0 0x04046000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + qdss_rep_in: endpoint { > + remote-endpoint = <&swao_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + port { > + qdss_rep_out0: endpoint { > + remote-endpoint = <&etr_rep_in>; > + }; > + }; > + }; > + }; > + > + tmc_etr: tmc@4048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x0 0x04048000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + iommus = <&apps_smmu 0x04c0 0x00>; > + > + arm,scatter-gather; > + > + in-ports { > + port { > + etr0_in: endpoint { > + remote-endpoint = <&etr_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + port { > + etr0_out: endpoint { > + remote-endpoint = <&ctcu_in0>; > + }; > + }; > + }; > + }; > + > + replicator@404e000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x0 0x0404e000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etr_rep_in: endpoint { > + remote-endpoint = <&qdss_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + etr_rep_out0: endpoint { > + remote-endpoint = <&etr0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + etr_rep_out1: endpoint { > + remote-endpoint = <&etr1_in>; > + }; > + }; > + }; > + }; > + > + tmc_etr1: tmc@404f000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x0 0x0404f000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + iommus = <&apps_smmu 0x04a0 0x40>; > + > + arm,scatter-gather; > + arm,buffer-size = <0x400000>; > + > + in-ports { > + port { > + etr1_in: endpoint { > + remote-endpoint = <&etr_rep_out1>; > + }; > + }; > + }; > + > + out-ports { > + port { > + etr1_out: endpoint { > + remote-endpoint = <&ctcu_in1>; > + }; > + }; > + }; > + }; > + > funnel@4b04000 { > compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > reg = <0x0 0x4b04000 0x0 0x1000>; > @@ -2708,6 +2853,14 @@ out-ports { > #address-cells = <1>; > #size-cells = <0>; > > + port@0 { > + reg = <0>; > + > + swao_rep_out0: endpoint { > + remote-endpoint = <&qdss_rep_in>; > + }; > + }; > + > port@1 { > reg = <1>; > swao_rep_out1: endpoint {

4 months

Re: [PATCH 4/5] coresight-tnoc: add node to configure flag type

by Yuanfang Zhang

On 2/22/2025 6:55 PM, Krzysztof Kozlowski wrote: > On 21/02/2025 08:40, Yuanfang Zhang wrote: >> + >> +static ssize_t flag_type_show(struct device *dev, >> + struct device_attribute *attr, >> + char *buf) >> +{ >> + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> + return sysfs_emit(buf, "%u\n", drvdata->flag_type); >> +} >> +static DEVICE_ATTR_RW(flag_type); >> + >> static struct attribute *trace_noc_attrs[] = { >> &dev_attr_flush_req.attr, >> &dev_attr_flush_status.attr, >> + &dev_attr_flag_type.attr, > > Where is the ABI documentation? will update in V3. > > Best regards, > Krzysztof

4 months

Re: [PATCH 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition

by Yuanfang Zhang

On 2/26/2025 7:07 PM, Krzysztof Kozlowski wrote: > On 26/02/2025 11:52, Yuanfang Zhang wrote: >> >> >> On 2/22/2025 6:47 PM, Krzysztof Kozlowski wrote: >>> On 21/02/2025 08:40, Yuanfang Zhang wrote: >>>> Adds new coresight-tnoc.yaml file describing the bindings required >>>> to define Trace NOC in the device trees. >>>> >>>> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >>> >>> >>> So you just sent the same v1, ignoring previous review. That's not how >>> it works. >>> >> sorry for this incorrect process. because i just update --to-cc list and no other >> change, i forced the version to V1, hoped it would work like resend, >> but the result was not as expected. > > > But you got feedback, so why resending without implementing it? That's > the problem, not you labeled/not-labeled it as resend. > got it, will implement it in next patch. > Best regards, > Krzysztof

4 months

OpenCSD version 1.5.6

by Mike Leach

Version 1.5.6 is now release. Contains build fixes and documentation upates Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months

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