CoreSight

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6 participants
2467 discussions

Re: [PATCH v3 00/11] (subset) ARM: qcom: fix APQ8064 schema warnings

by Suzuki K Poulose

On Fri, 25 Apr 2025 20:47:00 +0300, Dmitry Baryshkov wrote: > Rob's bot has reported [1] several warnings for Nexus 4 submisson, > however none of those warnings are specific to that device. Fix all > those warnings for all APQ8064 platforms by extending existing schemas, > adding missing schemas and making APQ8064 DT follow all the schema > files. > > [1]: https://lore.kernel.org/linux-arm-msm/174221818190.3957236.3364090534153729… > > [...] Applied, thanks! [06/11] dt-bindings: arm: arm,coresight-static-replicator: add optional clocks https://git.kernel.org/coresight/c/13e3a882 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 months, 2 weeks

[PATCH v2 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Changes in V2: 1. Add enum for compatible items. 2. Move offset arraies to coresight-cti-core Mao Jinlong (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 4 +- .../hwtracing/coresight/coresight-cti-core.c | 127 ++++++++++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 124 +++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 72 +++++----- 5 files changed, 243 insertions(+), 100 deletions(-) -- 2.25.1

4 months, 2 weeks

Re: [PATCH v4] coresight: prevent deactivate active config while enabling the config

by Leo Yan

Hi Levi, On Wed, Mar 26, 2025 at 07:34:25AM +0000, Yeoreum Yun wrote: [...] > > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > > @@ -1020,6 +1020,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) > > > smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); > > > > > > raw_spin_unlock(&drvdata->spinlock); > > > + > > > + cscfg_csdev_disable_active_config(csdev); > > > + > > > > In general, we need to split changes into several patches if each > > addresses a different issue. From my understanding, the change above is > > to fix missing to disable config when disable Sysfs mode. > > > > If so, could we use a seperate patch for this change? > > > > It's not a differnt issue. Without this line, the active count wouldn't > decrese and it raise another issue -- unloadable moudle for active_cnt :( > So I think it should be included in this patch. I read the code again and concluded the change above is not related to locking and would be a separate issue: when we close a Sysfs session, we need to disable a config on a CoreSight device. Could you clarify what is meaning "unloadable moudle for active_cnt"? I only saw "cscfg_mgr->sys_active_cnt" is used for module unloading, but have no clue why "active_cnt" impacts module unloading. > > > cpus_read_unlock(); > > > > > > /* > > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > > > index a70c1454b410..6d8c212ad434 100644 > > > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > > > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > > > @@ -391,14 +391,17 @@ static void cscfg_owner_put(struct cscfg_load_owner_info *owner_info) > > > static void cscfg_remove_owned_csdev_configs(struct coresight_device *csdev, void *load_owner) > > > { > > > struct cscfg_config_csdev *config_csdev, *tmp; > > > + unsigned long flags; > > > > > > if (list_empty(&csdev->config_csdev_list)) > > > return; > > > > > > + raw_spin_lock_irqsave(&csdev->cscfg_csdev_lock, flags); > > > > I think we should use spinlock to guard the condition checking > > list_empty(). > > > > Here the race condition is the 'config_csdev_list' list and > > configurations on the list. For atomicity, we should use lock to > > protect any operations on the list (read, add, delete, etc). > > Interesting... Would you let me know which race it is? > here to check list_empty(), it already guarded with "cscfg_mutex". Thanks for pointing out this. I read the code and understood that in some scenarios the list is protected by the mutex "cscfg_mutex". I would argue for using locking, we need to make clear for two thigns: - What is the race condition; - What locking is used to protect the race condition. For current case, a CoreSight device has a config list, the race condition is the config list will be manipulated by multiple places (e.g., for module loading / unloading, opening or closing a perf or SysFS session). So a spinlock is used to to protect the config list. "cscfg_mutex" is a high level lock, my understanding is to protect the high level operations from the Sysfs knobs, though sometimes it can mitigate the race condition on configuration list mentioned above, but the spinlock is the locking mechanism for the low level's config list on a CoreSight device. > However list_del() is special case because iterating config_csdev_list > can be done without cscfg_mutex -- see > cscfg_csdev_enable_active_config(). > This gurad with spinlock purpose to guard race unloading and > get the config in cscfg_csdev_enable_active_config() > (Please see my response below...). > > the emptiness of config_csdev_list is guarded with cscfg_mutex. > therefore, It seems enough to guard iterating part with spinlock :) Mixed using cscfg_mutex and spinlock get code complexity, and I am a bit concerned this is not best practice. At a glance, I would say 'cscfg_mutex' is purposed to protect the global 'cscfg_mgr', per CoreSight device's config list should be protected by 'cscfg_csdev_lock'. > > A side topic, as here it adds locks for protecting 'config_csdev_list', > > I am wandering why we do not do the same thing for > > 'feature_csdev_list' (See cscfg_remove_owned_csdev_features() and > > cscfg_get_feat_csdev()). > > In case of feature, It's okay since it couldn't be accessed when it > gets failed to get related config. I looked at cscfg_load_feat_csdev(), it uses 'cscfg_csdev_lock' to protect the feature list. This is why I thought the feature list also need to be protected by the lock. Now it is only partially protected. > When we see cscfg_csdev_enable_active_config(), the config could be > accessed without cscfg_mutex lock. so the config need to be guarded with > spin_lock otherwise it could be acquired while unload module > (after get active_cnt in search logic cscfg_csdev_enable_active_config() > and other running unloading process) To make things more clear, I have a questions. 'cscfg_mgr->sys_active_cnt' is used in the cscfg_unload_config_sets() function to decide if can unload module, if any configuration is active, why this variable cannot prevent unloading module? Sorry for late replying. Leo > But feature list is depends on config, If config is safe from > load/unload, this is not an issue so we don't need it. > > Thanks for your review!

4 months, 2 weeks

Re: [PATCH] coresight: trbe: Save/restore state across CPU low power state

by Mike Leach

Hi On Fri, 25 Apr 2025 at 23:05, Yabin Cui <yabinc(a)google.com> wrote: > > On Thu, Apr 24, 2025 at 9:16 PM Anshuman Khandual > <anshuman.khandual(a)arm.com> wrote: > > > > On 4/24/25 04:30, Yabin Cui wrote: > > > Similar to ETE, TRBE may lose its context when a CPU enters low > > > power state. To make things worse, if ETE state is restored without > > > restoring TRBE state, it can lead to a stuck CPU due to an enabled > > > source device with no enabled sink devices. > > > > Could you please provide some more details about when the cpu gets > > stuck e.g dmesg, traces etc. Also consider adding those details in > > the commit message as well to establish the problem, this patch is > > trying to address. > > This is already the best I know. When experimenting TRBE locally > (on Pixel 9), if I don't save TRBE state across low power state, when > recording system wide ETM data using TRBE on a CPU core. In a > few seconds, the CPU state becomes unknown (no message in dmesg). > Since the core may hold locks needed by other cores, it soon locks > other cores and causes a watchdog reset. I found the coresight driver > always carefully enables sink before source, and disables sink after > source. I guess there is some risk in not doing so, like the CPU hang > here. Maybe you know why? > > > > > > > > > > This patch introduces support for "arm,coresight-loses-context-with-cpu" > > > in the TRBE driver. When present, TRBE registers are saved before > > > and restored after CPU low power state. To prevent CPU hangs, TRBE > > > state is always saved after ETE state and restored after ETE state. > > > > The save and restore order here is > > > > 1. Save ETE > > 2. Save TRBE > > 3. Restore ETE > > 4. Restore TRBE > > > > > > > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > > > --- > > > .../coresight/coresight-etm4x-core.c | 13 ++++- > > > drivers/hwtracing/coresight/coresight-trbe.c | 53 +++++++++++++++++++ > > > include/linux/coresight.h | 6 +++ > > > 3 files changed, 71 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > > index e5972f16abff..1bbaa1249206 100644 > > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > > @@ -1863,6 +1863,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > > > static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > > > { > > > int ret = 0; > > > + struct coresight_device *sink; > > > > > > /* Save the TRFCR irrespective of whether the ETM is ON */ > > > if (drvdata->trfcr) > > > @@ -1871,8 +1872,14 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > > > * Save and restore the ETM Trace registers only if > > > * the ETM is active. > > > */ > > > - if (coresight_get_mode(drvdata->csdev) && drvdata->save_state) > > > + if (coresight_get_mode(drvdata->csdev) && drvdata->save_state) { > > > ret = __etm4_cpu_save(drvdata); > > > + if (ret == 0) { > > > + sink = coresight_get_percpu_sink(drvdata->cpu); > > > + if (sink && sink_ops(sink)->percpu_save) > > > + sink_ops(sink)->percpu_save(sink); > > > + } > > > + } > > > return ret; > > > } > > > > > > @@ -1977,6 +1984,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > > > > > > static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) > > > { > > > + struct coresight_device *sink = coresight_get_percpu_sink(drvdata->cpu); > > > + > > > + if (sink && sink_ops(sink)->percpu_restore) > > > + sink_ops(sink)->percpu_restore(sink); > > > > TRBE gets restored first which contradicts the order mentioned > > earlier in the commit message ? > > > An error in the commit message, should be: > To prevent CPU hangs, TRBE state is always saved after ETE state and > restored before ETE state. > > > > > > if (drvdata->trfcr) > > > write_trfcr(drvdata->save_trfcr); > > > if (drvdata->state_needs_restore) > > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > > > index fff67aac8418..38bf46951a82 100644 > > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > > > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > > > @@ -115,6 +115,13 @@ static int trbe_errata_cpucaps[] = { > > > */ > > > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE_SKIP_BYTES 256 > > > > > > +struct trbe_save_state { > > > + u64 trblimitr; > > > + u64 trbbaser; > > > + u64 trbptr; > > > + u64 trbsr; > > > +}; > > > > This seems to accommodate all required TRBE registers. Although this is > > very intuitive could you please also add a comment above this structure > > explaining the elements like other existing structures in the file ? > > Will do in the v2 patch. > > > > > + > > > /* > > > * struct trbe_cpudata: TRBE instance specific data > > > * @trbe_flag - TRBE dirty/access flag support > > > @@ -123,6 +130,9 @@ static int trbe_errata_cpucaps[] = { > > > * @cpu - CPU this TRBE belongs to. > > > * @mode - Mode of current operation. (perf/disabled) > > > * @drvdata - TRBE specific drvdata > > > + * @state_needs_save - Need to save trace registers when entering cpu idle > > > + * @state_needs_restore - Need to restore trace registers when exiting cpu idle > > > + * @save_state - Saved trace registers > > > * @errata - Bit map for the errata on this TRBE. > > > */ > > > struct trbe_cpudata { > > > @@ -133,6 +143,9 @@ struct trbe_cpudata { > > > enum cs_mode mode; > > > struct trbe_buf *buf; > > > struct trbe_drvdata *drvdata; > > > + bool state_needs_save; > > > > This tracks whether coresight_loses_context_with_cpu() is supported > > on the CPU or not. > > > > > + bool state_needs_restore; > > > > This tracks whether the state has been saved earlier and hence can > > be restored later on when required. > > Will update the comment in the v2 patch. > > > > > > + struct trbe_save_state save_state; > > > DECLARE_BITMAP(errata, TRBE_ERRATA_MAX); > > > }; > > > > > > @@ -1187,12 +1200,49 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > > > return IRQ_HANDLED; > > > } > > > > > > +static void arm_trbe_cpu_save(struct coresight_device *csdev) > > > +{ > > > + struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); > > > + struct trbe_save_state *state = &cpudata->save_state; > > > > Please move the above statement after the following conditional > > block. Because struct trbe_save_state is not going to be required > > if arm_trbe_cpu_save() returns prematurely from here. > > > Will do in the v2 patch. > > > + > > > + if (cpudata->mode == CS_MODE_DISABLED || !cpudata->state_needs_save) > > > + return;> + > > > + state->trbbaser = read_sysreg_s(SYS_TRBBASER_EL1); > > > + state->trbptr = read_sysreg_s(SYS_TRBPTR_EL1); > > > + state->trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > > + state->trbsr = read_sysreg_s(SYS_TRBSR_EL1); > > > + cpudata->state_needs_restore = true; > > > > This looks right. > > > > > +} > > > + > > > +static void arm_trbe_cpu_restore(struct coresight_device *csdev) > > > +{ > > > + struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); > > > + struct trbe_save_state *state = &cpudata->save_state; > > Please move this assignment inside the block where these registers > > actually get restored after all checks are done. > > > Will do in the v2 patch. > > > + > > > + if (cpudata->state_needs_restore) { > > > + /* > > > + * To avoid disruption of normal tracing, restore trace > > > + * registers only when TRBE lost power (TRBLIMITR == 0). > > > + */ > > > > Although this sounds like a reasonable condition, but what happens > > when TRBE restoration is skipped ? > > > There are cases when a CPU fails to enter a low power state or only enters > a shallow low power state. So TRBE state may not be lost when calling > arm_trbe_cpu_restore(). In this case, if we write the TRBE registers, probably > we lose ETM data written between save and restore. This may not matter, > but could there be a race condition between this restore function and TRBE > interrupt handler (which could also write TRBE registers)? I can't think > this up very well. So I only restore registers when state is lost. If > the state isn't > lost, TRBE should stay in enabled mode, and continue receiving data from ETE. > > > > + if (read_sysreg_s(SYS_TRBLIMITR_EL1) == 0) { > > > > state = &cpudata->save_state > > > > > + write_sysreg_s(state->trbbaser, SYS_TRBBASER_EL1); > > > + write_sysreg_s(state->trbptr, SYS_TRBPTR_EL1); > > > + write_sysreg_s(state->trbsr, SYS_TRBSR_EL1); > > > + set_trbe_enabled(cpudata, state->trblimitr); > > > + } > > > + cpudata->state_needs_restore = false; > > > > That means earlier captured state is dropped without a restoration. > > > > > + } > > > +} > > > + > > > static const struct coresight_ops_sink arm_trbe_sink_ops = { > > > .enable = arm_trbe_enable, > > > .disable = arm_trbe_disable, > > > .alloc_buffer = arm_trbe_alloc_buffer, > > > .free_buffer = arm_trbe_free_buffer, > > > .update_buffer = arm_trbe_update_buffer, > > > + .percpu_save = arm_trbe_cpu_save, > > > + .percpu_restore = arm_trbe_cpu_restore, > > > > Why this percpu_* prefix ? > > > Added percpu_ prefix because it's only for percpu_sink > (coresight_get_percpu_sink). > Please let me know if you have a better name. > > > }; > > > > > > static const struct coresight_ops arm_trbe_cs_ops = { > > > @@ -1358,6 +1408,9 @@ static void arm_trbe_probe_cpu(void *info) > > > cpudata->trbe_flag = get_trbe_flag_update(trbidr); > > > cpudata->cpu = cpu; > > > cpudata->drvdata = drvdata; > > > + cpudata->state_needs_save = coresight_loses_context_with_cpu( > > > + &drvdata->pdev->dev); > > > + cpudata->state_needs_restore = false; > > > > The init here looks good. > > > > > return; > > > cpu_clear: > > > cpumask_clear_cpu(cpu, &drvdata->supported_cpus); > > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > > > index d79a242b271d..fec375d02535 100644 > > > --- a/include/linux/coresight.h > > > +++ b/include/linux/coresight.h > > > @@ -362,6 +362,10 @@ enum cs_mode { > > > * @alloc_buffer: initialises perf's ring buffer for trace collection. > > > * @free_buffer: release memory allocated in @get_config. > > > * @update_buffer: update buffer pointers after a trace session. > > > + * @percpu_save: saves state when CPU enters idle state. > > > + * Only set for percpu sink. > > > + * @percpu_restore: restores state when CPU exits idle state. > > > + * only set for percpu sink. > > > */ > > > struct coresight_ops_sink { > > > int (*enable)(struct coresight_device *csdev, enum cs_mode mode, > > > @@ -374,6 +378,8 @@ struct coresight_ops_sink { > > > unsigned long (*update_buffer)(struct coresight_device *csdev, > > > struct perf_output_handle *handle, > > > void *sink_config); > > > + void (*percpu_save)(struct coresight_device *csdev); > > > + void (*percpu_restore)(struct coresight_device *csdev); > > > > Again - why this percpu_* prefix ? > > > > > }; > > > > > > /** I do not think this is the best approach. The TRBE driver has its own power management registration functions, so is it not possible for the save and restore should be handled there, through a PM notifier, just as the ETM/ETE is? Drop the unnecessary DT entry - TRBE is a per cpu architectural device - if a TRBE is present, we know it will power down with the PE. The CoreSight architecture permits an ETE to drive trace to an external sink - so the TRBE might be present but unused, therefore hooking into a source driver that may not be driving trace into the device does not seem wise.. The TRBE PM can follow the model of the ETE / ETMv4 and save and restore if currently in use. This approach will isolate the changes to the TRBE driver where they should be. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 months, 2 weeks

Re: [PATCH v1 1/2] dt-bindings: arm: Add Qualcomm extended CTI

by Jinlong Mao

On 2025/4/28 15:39, Krzysztof Kozlowski wrote: > On 28/04/2025 09:31, Jinlong Mao wrote: >> >> >> On 2024/9/3 20:42, Krzysztof Kozlowski wrote: >>> On 03/09/2024 14:18, Mao Jinlong wrote: >>>> Add Qualcomm extended CTI support in CTI binding file. Qualcomm >>>> extended CTI supports up to 128 triggers. >>>> >>>> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >>>> --- >>>> .../devicetree/bindings/arm/arm,coresight-cti.yaml | 14 ++++++++++++++ >>>> 1 file changed, 14 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> index 6a73eaa66a42..141efba7c697 100644 >>>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> @@ -87,6 +87,10 @@ properties: >>>> - const: arm,coresight-cti-v8-arch >>>> - const: arm,coresight-cti >>>> - const: arm,primecell >>>> + - items: >>>> + - const: qcom,coresight-cti-extended >>> >>> That's just enum in previous entry/list. >> Sorry for the late response. This is a new CTI type. Need the three >> items in compatible at the same time, just like other kind of CTIs. > > > Comment stays valid, you did not address it at all. Hi Krzysztof, Do you mean we only need const: qcom,coresight-cti-extended here ? No need const: arm,coresight-cti and const: arm,primecell as they are in previous entry/list, right ? > >> >>> >>>> + - const: arm,coresight-cti >>>> + - const: arm,primecell >>>> >>>> reg: >>>> maxItems: 1 >>>> @@ -254,6 +258,16 @@ examples: >>>> clocks = <&soc_smc50mhz>; >>>> clock-names = "apb_pclk"; >>>> }; >>>> + # minimum extended CTI definition. >>>> + - | >>> >>> No need for new example. No differences here. >> This is a new type CTI. > > > Comment stays valid, you did not address it at all. > > Best regards, > Krzysztof

4 months, 2 weeks

Re: [PATCH 1/2] perf: Allow non-contiguous AUX buffer pages via PMU capability

by James Clark

On 23/04/2025 8:52 pm, Yabin Cui wrote: > On Tue, Apr 22, 2025 at 7:10 AM Leo Yan <leo.yan(a)arm.com> wrote: >> >> On Tue, Apr 22, 2025 at 02:49:54PM +0200, Ingo Molnar wrote: >> >> [...] >> >>>> Hi Yabin, >>>> >>>> I was wondering if this is just the opposite of >>>> PERF_PMU_CAP_AUX_NO_SG, and that order 0 should be used by default >>>> for all devices to solve the issue you describe. Because we already >>>> have PERF_PMU_CAP_AUX_NO_SG for devices that need contiguous pages. >>>> Then I found commit 5768402fd9c6 ("perf/ring_buffer: Use high order >>>> allocations for AUX buffers optimistically") that explains that the >>>> current allocation strategy is an optimization. >>>> >>>> Your change seems to decide that for certain devices we want to >>>> optimize for fragmentation rather than performance. If these are >>>> rarely used features specifically when looking at performance should >>>> we not continue to optimize for performance? Or at least make it user >>>> configurable? >>> >>> So there seems to be 3 categories: >>> >>> - 1) Must have physically contiguous AUX buffers, it's a hardware ABI. >>> (PERF_PMU_CAP_AUX_NO_SG for Intel BTS and PT.) >>> >>> - 2) Would be nice to have continguous AUX buffers, for a bit more >>> performance. >>> >>> - 3) Doesn't really care. >>> >>> So we do have #1, and it appears Yabin's usecase is #3? > > Yes, in my usecase, I care much more about MM-friendly than a little potential > performance when using PMU. It's not a rarely used feature. On Android, we > collect ETM data periodically on internal user devices for AutoFDO optimization > (for both userspace libraries and the kernel). Allocating a large > chunk of contiguous > AUX pages (4M for each CPU) periodically is almost unbearable. The kernel may > need to kill many processes to fulfill the request. It affects user > experience even > after using PMU. > > I am totally fine to reuse PERF_PMU_CAP_AUX_NO_SG. If PMUs don't want to > sacrifice performance for MM-friendly, why support scatter gather mode? If there > are strong performance reasons to allocate contiguous AUX pages in > scatter gather > mode, I hope max_order is configurable in userspace. > > Currently, max_order is affected by aux_watermark. But aux_watermark > also affects > how frequently the PMU overflows AUX buffer and notifies userspace. > It's not ideal > to set aux_watermark to 1 page size. So if we want to make max_order user > configurable, maybe we can add a one bit field in perf_event_attr? > >> >> In Yabin's case, the AUX buffer work as a bounce buffer. The hardware >> trace data is copied by a driver from low level's contiguous buffer to >> the AUX buffer. >> >> In this case we cannot benefit much from continguous AUX buffers. >> >> Thanks, >> Leo Hi Yabin, So after doing some testing it looks like there is 0 difference in overhead for max_order=0 vs ensuring the buffer is one contiguous allocation for Arm SPE, and TRBE would be exactly the same. This makes sense because we're vmapping pages individually anyway regardless of the base allocation. Seems like the performance optimization of the optimistically large mappings is only for devices that require extra buffer management stuff other than normal virtual memory. Can we add a new capability PERF_PMU_CAP_AUX_PREFER_LARGE and apply it to Intel PT and BTS? Then the old (before the optimistic large allocs change) max_order=0 behavior becomes the default again, and PREFER_LARGE is just for those two devices. Other and new devices would get the more memory friendly allocations by default, as it's unlikely they'll benefit from anything different. Thanks James

4 months, 2 weeks

Re: [PATCH v3 06/11] dt-bindings: arm: arm,coresight-static-replicator: add optional clocks

by Suzuki K Poulose

Hi Dmitry On 25/04/2025 18:47, Dmitry Baryshkov wrote: > As most other CoreSight devices the replicator can use either of the > optional clocks. Document those optional clocks in the schema. > Additionally document the one-off case of Zynq-7000 platforms which uses > apb_pclk and two additional debug clocks. What is the plan for merging this series ? I am happy to pick this patch via coresight tree. > > Fixes: 3c15fddf3121 ("dt-bindings: arm: Convert CoreSight bindings to DT schema") > Reviewed-by: Rob Herring (Arm) <robh(a)kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)oss.qualcomm.com> Otherwise, Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Suzuki > --- > .../bindings/arm/arm,coresight-static-replicator.yaml | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml > index a6f793ea03b6c193fc0ff72a45e0249a63a2ba3c..0c1017affbad2f03892b250ad864d9a5dc8d02f1 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml > @@ -30,6 +30,19 @@ properties: > power-domains: > maxItems: 1 > > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + oneOf: > + - items: > + - enum: [apb_pclk, atclk] > + - items: # Zynq-700 > + - const: apb_pclk > + - const: dbg_trc > + - const: dbg_apb > + > in-ports: > $ref: /schemas/graph.yaml#/properties/ports > additionalProperties: false >

4 months, 2 weeks

Re: [PATCH v1 1/2] dt-bindings: arm: Add Qualcomm extended CTI

by Jinlong Mao

On 2024/9/3 20:42, Krzysztof Kozlowski wrote: > On 03/09/2024 14:18, Mao Jinlong wrote: >> Add Qualcomm extended CTI support in CTI binding file. Qualcomm >> extended CTI supports up to 128 triggers. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> .../devicetree/bindings/arm/arm,coresight-cti.yaml | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> index 6a73eaa66a42..141efba7c697 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> @@ -87,6 +87,10 @@ properties: >> - const: arm,coresight-cti-v8-arch >> - const: arm,coresight-cti >> - const: arm,primecell >> + - items: >> + - const: qcom,coresight-cti-extended > > That's just enum in previous entry/list. Sorry for the late response. This is a new CTI type. Need the three items in compatible at the same time, just like other kind of CTIs. > >> + - const: arm,coresight-cti >> + - const: arm,primecell >> >> reg: >> maxItems: 1 >> @@ -254,6 +258,16 @@ examples: >> clocks = <&soc_smc50mhz>; >> clock-names = "apb_pclk"; >> }; >> + # minimum extended CTI definition. >> + - | > > No need for new example. No differences here. This is a new type CTI. > > > Best regards, > Krzysztof >

4 months, 2 weeks

Re: [PATCH v3 2/2] coresight: core: Disable helpers for devices that fail to enable

by James Clark

On 08/04/2025 8:59 pm, Yabin Cui wrote: > When enabling a SINK or LINK type coresight device fails, the > associated helpers should be disabled. > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index fb43ef6a3b1f..a56ba9087538 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -486,8 +486,10 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, > * that need disabling. Disabling the path here > * would mean we could disrupt an existing session. > */ > - if (ret) > + if (ret) { > + coresight_disable_helpers(csdev); Hi Yabin, Unfortunately coresight_disable_helpers() takes a path pointer now so this needs to be updated. I tested with that change made and it works ok. > goto out; > + } > break; > case CORESIGHT_DEV_TYPE_SOURCE: > /* sources are enabled from either sysFS or Perf */ > @@ -496,10 +498,13 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, > parent = list_prev_entry(nd, link)->csdev; > child = list_next_entry(nd, link)->csdev; > ret = coresight_enable_link(csdev, parent, child, source); > - if (ret) > + if (ret) { > + coresight_disable_helpers(csdev); > goto err; > + } > break; > default: > + coresight_disable_helpers(csdev); Minor nit, you could collapse these last two into "goto err_disable_helpers" and add another label before err: that disables helpers before falling through to err:. Other than that: Reviewed-by: James Clark <james.clark(a)linaro.org> > goto err; > } > }

4 months, 3 weeks

OpenCSD, ARM Cortex R8: observing I_COND_FLUSH and errors, no OCSD_GEN_TRC_ELEM_INSTR_RANGE seen.

by Tushar Rane

I am trying to get OpenCSD working to decode traces for code running on Dual core Arm Cortex-R8, all running in the context of Nucleus OS. I am running into some issues as described below; will appreciate any advice/suggestions. I have been able to get some of this working. So far following is the progress: -------------------------------------------------------------------------------------------------------- - OpenCSD library version: 1.5.5 - Using c_api_pkt_print_test.c test program to configure OpenCSD library and decode. Configuration or changes done in c_api_pkt_print_test.c::create_decoder_etmv4 for the Arm Cortex R8. Not using snapshot, but hard coded the mem_file_path and trace_file_path for my Arm Cortex R8 files. Logs are attached at the end of this message for reference. - Configuration from the code running on Arm Cortex-R8 for ETM, ETB, ETMFUN, Replicator, seems to be working. - Able to get ETB traces successfully. - Changed c_api_pkt_print_test.c and was able to compile and get some decoding done. - In the output of "c_api_pkt_print_test -raw -decode", the addresses can be co-related to the executed code, so it seems to be working so far till here. For example: Frame Data; Index 3984; ID_DATA[0x06]; e3 06 19 96 60 02 00 81 03 9a 04 00 ff ff Idx:3981;[ 0x96 0xDF 0xE3 ];I_ADDR_S_IS1 : Address, Short, IS1.; Addr=0x00000000201FE3BE ~[0xE3BE] Idx:3985;[ 0x06 0x19 ];I_EXCEPT : Exception.; Data Fault; Ret Addr Follows; Idx:3987;[ 0x96 0x60 ];I_ADDR_S_IS1 : Address, Short, IS1.; Addr=0x00000000201FE3C0 ~[0xC0] Idx:3989;[ 0x02 0x00 ];I_TIMESTAMP : Timestamp.; Updated val = 0x0 The “Addr=” can be co-related to the executed code before the trace was collected. Following are the issues encountered and the post here is to seek any ideas on what could be causing these and what could be to be done to fix them. ------------------------------------------------------------------- a. In the output for “c_api_pkt_print_test -raw -decode”, the decoder is not generating any OCSD_GEN_TRC_ELEM_INSTR_RANGE elements, which Is the main issue here. b. There are multiple occurrences of following errors: OCSD_ERR_BAD_DECODE_PKT (along with I_COND_FLUSH), OCSD_ERR_COMMIT_PKT_OVERRUN Idx:441;[ 0x9B 0x21 0xDB 0x21 0x20 ];I_ADDR_L_32IS1 : Address, Long, 32 bit, IS1.; Addr=0x000000002021DB42; Idx:446;[ 0x43 ];I_RESERVED_CFG : Reserved header for current configuration.[I_COND_FLUSH] DCD_ETMV4_0006 : 0x0019 (OCSD_ERR_BAD_DECODE_PKT) [Reserved or unknown packet in decoder.]; TrcIdx=446; CS ID=06; Unknown packet type.Frame Data; Index 448; ID_DATA[0x06]; 02 00 f7 da 2f 03 81 83 00 00 00 00 43 96 29 Idx:448;[ 0x02 0x00 ];I_TIMESTAMP : Timestamp.; Updated val = 0x0 Idx:448; TrcID:0x06; OCSD_GEN_TRC_ELEM_NO_SYNC( [bad-packet]) Idx:450;[ 0xF7 ];I_ATOM_F1 : Atom format 1.; E c. On running just “c_api_pkt_print_test -raw” (no decode), multiple OCSD_ERR_INVALID_PCKT_HDR errors are observed, along with I_COND_FLUSH are observed: PKTP_ETMV4I_0006 : 0x0014 (OCSD_ERR_INVALID_PCKT_HDR) [Invalid packet header]; TrcIdx=460; CS ID=06; Idx:460; I_RESERVED_CFG : Reserved header for current configuration.[I_COND_FLUSH] However, conditional Instruction Tracing is disabled (as seen below) , so it's unclear why I_COND_FLUSH above are observed. Could I_COND_FLUSH be throwing off the decoder? NOTES: -------- I did run a test by configuring the processor to stall, setting TRCSTALLCTLR to 0x50c (in case traces were being dropped and processor stalling helped). However that did not make any difference. CONFIGURATION DONE IN CODE RUNNING ON ARM CORTEX-R8: ------------------------------------------------------------------- // INSTP0 = 0 (Only branches are P0 instructions) // BB = 0 (Branch broadcast mode disabled) // CCI = 0 (cycle counting in instruction trace disabled) // CID = 1 (Context ID tracing enabled) // COND = 0 (Conditional instruction tracing disabled) // TS = 1 (Global timestamp tracing enabled) // RS = 1 (Return stack enabled) // DA = 0 (Data address tracing disabled) // DV = 0 (Data value tracing disabled) TRCCONFIGR = 0x1841; // disable all event tracing TRCEVENTCTL0R = 0; TRCEVENTCTL1R = 0; // ISTALL = 0 (Do not stall processor) // DSTALL = 0 (Do not stall processor) // LEVEL = 0 (Lowest level, where zero invasion occurs) // the risk of overflow) TRCSTALLCTLR = 0; // Enable trace synchronization every 256 bytes of trace TRCSYNCPR = 0x8 //Trace ID = 6, only on trace stream from one Cortex R8 core. TRCTRACEIDR = 6; // Disable the timestamp event. The trace unit still generates // timestamps due to other reasons such // as trace synchronization TRCTSCTLR = 0; // Enable ViewInst to trace everything, with the Start/Stop logic // started // EXLEVEL_S3 = 0 (Enable ViewInst in this exception level. // Highest privilege level. FW runs at this level) // TRCERR = 1 (System error exception is always traced regardless of // the value of ViewInst) // SSSTATUS = 1 (Start/stop logic is in the started state) // TYPE = 0 (Single selected resource) // SEL = 1 (Selects the resource number 1, which always returns TRUE) TRCVICTLR = 0xa01 // No address range filtering for ViewIns TRCVIIECTLR = 0; // No start or stop points for ViewInst TRCVISSCTLR = 0; // enable ETM TRCPRGCTLR = 1; Configuration for ETMv4 done in c_api_pkt_print_test.c --------------------------------------------------------- trace_config.arch_ver = ARCH_V7; trace_config.core_prof = profile_CortexR; trace_config.reg_configr = 0x1841; printf("trace_config.reg_configr = 0x%x", trace_config.reg_configr); trace_config.reg_traceidr = 0x6; // CRT = 6 if(test_trc_id_override != 0) { trace_config.reg_traceidr = (uint32_t)test_trc_id_override; } test_trc_id_override = trace_config.reg_traceidr; /* remember what id we actually used */ trace_config.reg_idr0 = 0x6001eff; trace_config.reg_idr1 = 0x4100f400; trace_config.reg_idr2 = 0x420084; trace_config.reg_idr8 = 0x40; trace_config.reg_idr9 = 0x40; trace_config.reg_idr10 = 0x40; trace_config.reg_idr11 = 0x11; trace_config.reg_idr12 = 0x20; trace_config.reg_idr13 = 0x0; /* create an ETMV4 decoder - no context needed as we have a single stream to a single handler. */ return create_generic_decoder(dcd_tree_h,OCSD_BUILTIN_DCD_ETMV4I,(void *)&trace_config,0); Attached following logs: ------------------------------ Output of “c_api_pkt_print_test -raw -decode” - 5.raw.decode.newoutput.log Output of “c_api_pkt_print_test -raw” - 5.raw.newoutput.log I would appreciate any feedback regarding this to help get the needed output from the decoder.

4 months, 3 weeks

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