CoreSight

coresight@lists.linaro.org

2 participants
2518 discussions

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") This tag isn't right. Although this is where the register accesses were last touched, the root issue was present from the introduction of the driver. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

2 months, 3 weeks

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards, Reviewed-by: James Clark <james.clark(a)linaro.org>

2 months, 3 weeks

Re: [PATCH] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 11/08/2025 10:57 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > Looks like this should have a fixes: tag. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..8a9c4caceff0165e4fce7ac4250f3e16ccc1d34e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->nrseqstate) Shouldn't this be "if (drvdata->numextinsel)"? Or it needs a comment saying why it's different to the others. Otherwise looks ok. > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

2 months, 3 weeks

Re: [PATCH v1] coresight: tpda: fix the logic to setup the element size

by James Clark

On 06/08/2025 9:09 am, Jie Gan wrote: > Some TPDM devices support both CMB and DSB datasets, requiring > the system to enable the port with both corresponding element sizes. > > Currently, the logic treats tpdm_read_element_size as successful if > the CMB element size is retrieved correctly, regardless of whether > the DSB element size is obtained. This behavior causes issues > when parsing data from TPDM devices that depend on both element sizes. > > To address this, the function should explicitly fail if the DSB > element size cannot be read correctly. > > Fixes: e6d7f5252f73 ("coresight-tpda: Add support to configure CMB element") > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 0633f04beb24..333b3cb23685 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -71,6 +71,8 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > if (tpdm_data->dsb) { > rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > "qcom,dsb-element-bits", &drvdata->dsb_esize); > + if (rc) > + goto out; > } > > if (tpdm_data->cmb) { > @@ -78,6 +80,7 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > "qcom,cmb-element-bits", &drvdata->cmb_esize); > } > > +out: > if (rc) > dev_warn_once(&csdev->dev, > "Failed to read TPDM Element size: %d\n", rc); Reviewed-by: James Clark <james.clark(a)linaro.org>

3 months

[PATCH v10 0/2] coresight: Add label sysfs node support

by Mao Jinlong

Change since V9: 1. Replace scnprintf with sysfs_emit. 2. Update date in ABI files. V9 link: https://lkml.org/lkml/2025/7/17/832 Change since V8: 1. Add label in all documentations of coresight components. 2. Add control of the visibility of the label sysfs attribute. V8 link: https://lkml.org/lkml/2025/7/3/985 Change since V7: 1. Update the conflict when apply to coresight next. 2. Update the Date and version in ABI file. V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.… Change since V6: 1. Update the date and version in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++ .../sysfs-bus-coresight-devices-dummy-source | 6 ++ .../testing/sysfs-bus-coresight-devices-etb10 | 6 ++ .../testing/sysfs-bus-coresight-devices-etm3x | 6 ++ .../testing/sysfs-bus-coresight-devices-etm4x | 6 ++ .../sysfs-bus-coresight-devices-funnel | 6 ++ .../testing/sysfs-bus-coresight-devices-stm | 6 ++ .../testing/sysfs-bus-coresight-devices-tmc | 6 ++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ .../testing/sysfs-bus-coresight-devices-trbe | 6 ++ .../bindings/arm/arm,coresight-cti.yaml | 4 ++ .../arm/arm,coresight-dummy-sink.yaml | 4 ++ .../arm/arm,coresight-dummy-source.yaml | 4 ++ .../arm/arm,coresight-dynamic-funnel.yaml | 4 ++ .../arm/arm,coresight-dynamic-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-etb10.yaml | 4 ++ .../bindings/arm/arm,coresight-etm.yaml | 4 ++ .../arm/arm,coresight-static-funnel.yaml | 4 ++ .../arm/arm,coresight-static-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-tmc.yaml | 4 ++ .../bindings/arm/arm,coresight-tpiu.yaml | 4 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++ .../arm/qcom,coresight-remote-etm.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpda.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++ drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++- 26 files changed, 189 insertions(+), 2 deletions(-) -- 2.25.1

3 months

[PATCH v9 0/2] coresight: Add label sysfs node support

by Mao Jinlong

Change since V8: 1. Add label in all documentations of coresight components. 2. Add control of the visibility of the label sysfs attribute. V8 link: https://lkml.org/lkml/2025/7/3/985 Change since V7: 1. Update the conflict when apply to coresight next. 2. Update the Date and version in ABI file. V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.… Change since V6: 1. Update the date and verison in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++ .../sysfs-bus-coresight-devices-dummy-source | 6 ++ .../testing/sysfs-bus-coresight-devices-etb10 | 6 ++ .../testing/sysfs-bus-coresight-devices-etm3x | 6 ++ .../testing/sysfs-bus-coresight-devices-etm4x | 6 ++ .../sysfs-bus-coresight-devices-funnel | 6 ++ .../testing/sysfs-bus-coresight-devices-stm | 6 ++ .../testing/sysfs-bus-coresight-devices-tmc | 6 ++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ .../testing/sysfs-bus-coresight-devices-trbe | 6 ++ .../bindings/arm/arm,coresight-cti.yaml | 4 ++ .../arm/arm,coresight-dummy-sink.yaml | 4 ++ .../arm/arm,coresight-dummy-source.yaml | 4 ++ .../arm/arm,coresight-dynamic-funnel.yaml | 4 ++ .../arm/arm,coresight-dynamic-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-etb10.yaml | 4 ++ .../bindings/arm/arm,coresight-etm.yaml | 4 ++ .../arm/arm,coresight-static-funnel.yaml | 4 ++ .../arm/arm,coresight-static-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-tmc.yaml | 4 ++ .../bindings/arm/arm,coresight-tpiu.yaml | 4 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++ .../arm/qcom,coresight-remote-etm.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpda.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++ drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++- 26 files changed, 189 insertions(+), 2 deletions(-) -- 2.25.1

3 months

[PATCH v3 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Changes in v3: 1. Rename is_extended_cti() to of_is_extended_cti(). 2. Add the missing 'i' when write the CTI trigger registers. 3. Convert the multi-line output in sysfs to single line. 4. Initialize offset arrays using designated initializer. Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… Changes in V2: 1. Add enum for compatible items. 2. Move offset arrays to coresight-cti-core Yingchao Deng (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 4 +- .../hwtracing/coresight/coresight-cti-core.c | 127 +++++++++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 128 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 75 +++++----- 5 files changed, 248 insertions(+), 102 deletions(-) -- 2.25.1

3 months

Re: [PATCH v4 05/10] coresight: tmc: Introduce tmc_read_ops to wrap read operations

by Mike Leach

On Wed, 6 Aug 2025 at 07:30, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > > > On 8/5/2025 6:55 PM, Mike Leach wrote: > > Hi > > > > On Fri, 25 Jul 2025 at 11:08, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > >> > >> Introduce tmc_read_ops as a wrapper, wrap read operations, for reading > >> trace data from the TMC buffer. > >> > >> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > >> --- > >> .../hwtracing/coresight/coresight-tmc-core.c | 50 +++++++++---------- > >> drivers/hwtracing/coresight/coresight-tmc.h | 17 +++++++ > >> 2 files changed, 40 insertions(+), 27 deletions(-) > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > >> index 4d249af93097..f668047c5df4 100644 > >> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > >> @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) > >> { > >> int ret = 0; > >> > >> - switch (drvdata->config_type) { > >> - case TMC_CONFIG_TYPE_ETB: > >> - case TMC_CONFIG_TYPE_ETF: > >> - ret = tmc_read_prepare_etb(drvdata); > >> - break; > >> - case TMC_CONFIG_TYPE_ETR: > >> - ret = tmc_read_prepare_etr(drvdata); > >> - break; > >> - default: > >> + if (drvdata->read_ops) > >> + ret = drvdata->read_ops->read_prepare(drvdata); > >> + else > >> ret = -EINVAL; > >> - } > >> > >> if (!ret) > >> dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); > >> @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) > >> { > >> int ret = 0; > >> > >> - switch (drvdata->config_type) { > >> - case TMC_CONFIG_TYPE_ETB: > >> - case TMC_CONFIG_TYPE_ETF: > >> - ret = tmc_read_unprepare_etb(drvdata); > >> - break; > >> - case TMC_CONFIG_TYPE_ETR: > >> - ret = tmc_read_unprepare_etr(drvdata); > >> - break; > >> - default: > >> + if (drvdata->read_ops) > >> + ret = drvdata->read_ops->read_unprepare(drvdata); > >> + else > >> ret = -EINVAL; > >> - } > >> > >> if (!ret) > >> dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); > >> @@ -291,13 +277,8 @@ static int tmc_open(struct inode *inode, struct file *file) > >> static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, > >> char **bufpp) > >> { > >> - switch (drvdata->config_type) { > >> - case TMC_CONFIG_TYPE_ETB: > >> - case TMC_CONFIG_TYPE_ETF: > >> - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); > >> - case TMC_CONFIG_TYPE_ETR: > >> - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > >> - } > >> + if (drvdata->read_ops) > >> + return drvdata->read_ops->get_trace_data(drvdata, pos, len, bufpp); > >> > >> return -EINVAL; > >> } > >> @@ -769,6 +750,18 @@ static void register_crash_dev_interface(struct tmc_drvdata *drvdata, > >> "Valid crash tracedata found\n"); > >> } > >> > >> +static const struct tmc_read_ops tmc_etb_read_ops = { > >> + .read_prepare = tmc_read_prepare_etb, > >> + .read_unprepare = tmc_read_unprepare_etb, > >> + .get_trace_data = tmc_etb_get_sysfs_trace, > >> +}; > >> + > >> +static const struct tmc_read_ops tmc_etr_read_ops = { > >> + .read_prepare = tmc_read_prepare_etr, > >> + .read_unprepare = tmc_read_unprepare_etr, > >> + .get_trace_data = tmc_etr_get_sysfs_trace, > >> +}; > >> + > >> static int __tmc_probe(struct device *dev, struct resource *res) > >> { > >> int ret = 0; > >> @@ -818,6 +811,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > >> desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; > >> desc.ops = &tmc_etb_cs_ops; > >> dev_list = &etb_devs; > >> + drvdata->read_ops = &tmc_etb_read_ops; > >> break; > >> case TMC_CONFIG_TYPE_ETR: > >> desc.groups = coresight_etr_groups; > >> @@ -831,6 +825,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > >> mutex_init(&drvdata->idr_mutex); > >> dev_list = &etr_devs; > >> INIT_LIST_HEAD(&drvdata->etr_buf_list); > >> + drvdata->read_ops = &tmc_etr_read_ops; > >> break; > >> case TMC_CONFIG_TYPE_ETF: > >> desc.groups = coresight_etf_groups; > >> @@ -839,6 +834,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > >> desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; > >> desc.ops = &tmc_etf_cs_ops; > >> dev_list = &etf_devs; > >> + drvdata->read_ops = &tmc_etb_read_ops; > >> break; > >> default: > >> pr_err("%s: Unsupported TMC config\n", desc.name); > >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > >> index 3cb8ba9f88f5..2ad8e288c94b 100644 > >> --- a/drivers/hwtracing/coresight/coresight-tmc.h > >> +++ b/drivers/hwtracing/coresight/coresight-tmc.h > >> @@ -223,6 +223,8 @@ struct etr_buf_node { > >> struct list_head node; > >> }; > >> > >> +struct tmc_read_ops; > >> + > > > > declare the entire structure here rather than later. > > There is an issue of declare the entire structure here because the > function pointer needs use the struct tmc_drvdata which is not defined > at this point and it will cause a compile error. > Understood. Mike > Thanks, > Jie > > > > >> /** > >> * struct tmc_drvdata - specifics associated to an TMC component > >> * @pclk: APB clock if present, otherwise NULL > >> @@ -259,6 +261,7 @@ struct etr_buf_node { > >> * Used by ETR/ETF. > >> * @etr_buf_list: List that is used to manage allocated etr_buf. > >> * @reading_node: Available buffer for byte-cntr reading. > >> + * @tmc_read_ops: Read operations for TMC device. > >> */ > >> struct tmc_drvdata { > >> struct clk *pclk; > >> @@ -290,6 +293,20 @@ struct tmc_drvdata { > >> struct tmc_resrv_buf crash_mdata; > >> struct list_head etr_buf_list; > >> struct etr_buf_node *reading_node; > >> + const struct tmc_read_ops *read_ops; > > > > probably should be named sysfs_read_ops to be consistent with the > > perf/sysfs differentiation within the rest of the structure > > > >> +}; > >> + > >> +/** > >> + * struct tmc_read_ops - read operations for TMC and its helper devices > >> + * @read_prepare: prepare operation. > >> + * @read_unprepare: unprepare operation. > >> + * @get_trace_data: read operation. > >> + */ > >> +struct tmc_read_ops { > >> + int (*read_prepare)(struct tmc_drvdata *drvdata); > >> + int (*read_unprepare)(struct tmc_drvdata *drvdata); > >> + ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos, > >> + size_t len, char **bufpp); > >> }; > >> > >> struct etr_buf_operations { > >> -- > >> 2.34.1 > >> > > > > with the above changes:- > > > > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

Re: [PATCH v4 08/10] coresight: add a new function in helper_ops

by Mike Leach

Hi, On Fri, 25 Jul 2025 at 11:08, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > Add a new function to identifiy whether the byte-cntr function is > enabled or not in helper_ops. > > The byte-cntr's read_ops is expected if the byte-cntr is enabled when > the user try to read trace data via sysfs node. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../hwtracing/coresight/coresight-ctcu-core.c | 35 +++++++++++++++++++ > include/linux/coresight.h | 3 ++ > 2 files changed, 38 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index 8fc08e42187e..dec911980939 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -234,9 +234,44 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) > return ctcu_set_etr_traceid(csdev, path, false); > } > > +static bool ctcu_qcom_byte_cntr_in_use(struct coresight_device *csdev, > + void **data) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct coresight_device *helper; > + struct ctcu_drvdata *drvdata; > + int port; > + > + if (!csdev) > + return false; > + > + helper = coresight_get_helper(csdev, CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); > + if (!helper) > + return false; > + > + port = coresight_get_in_port_dest(csdev, helper); > + if (port < 0) > + return false; > + > + drvdata = dev_get_drvdata(helper->dev.parent); > + /* Something wrong when initialize byte_cntr_read_ops */ > + if (!drvdata->byte_cntr_read_ops) > + return false; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port]; > + /* Return the pointer of the ctcu_drvdata if byte-cntr has enabled */ > + if (byte_cntr_data && byte_cntr_data->thresh_val) { > + *data = (void *)drvdata->byte_cntr_read_ops; > + return true; > + } > + > + return false; > +} > + > static const struct coresight_ops_helper ctcu_helper_ops = { > .enable = ctcu_enable, > .disable = ctcu_disable, > + .qcom_byte_cntr_in_use = ctcu_qcom_byte_cntr_in_use, These ops structures are for generic functions used throughout the devices. Do not put this function here. This is a specific ctcu helper. Make it external to the file and declare it in coresight-ctcu.h Mike > }; > > static const struct coresight_ops ctcu_ops = { > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 4ac65c68bbf4..b5f052854b08 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -419,11 +419,14 @@ struct coresight_ops_source { > * > * @enable : Enable the device > * @disable : Disable the device > + * @qcom_byte_cntr_in_use: check whether the byte-cntr is enabled. > */ > struct coresight_ops_helper { > int (*enable)(struct coresight_device *csdev, enum cs_mode mode, > void *data); > int (*disable)(struct coresight_device *csdev, void *data); > + bool (*qcom_byte_cntr_in_use)(struct coresight_device *csdev, > + void **data); > }; > > > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

Re: [PATCH v4 08/10] coresight: add a new function in helper_ops

by Mike Leach

Hi, On Fri, 25 Jul 2025 at 11:08, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > Add a new function to identifiy whether the byte-cntr function is > enabled or not in helper_ops. > > The byte-cntr's read_ops is expected if the byte-cntr is enabled when > the user try to read trace data via sysfs node. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../hwtracing/coresight/coresight-ctcu-core.c | 35 +++++++++++++++++++ > include/linux/coresight.h | 3 ++ > 2 files changed, 38 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index 8fc08e42187e..dec911980939 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -234,9 +234,44 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) > return ctcu_set_etr_traceid(csdev, path, false); > } > > +static bool ctcu_qcom_byte_cntr_in_use(struct coresight_device *csdev, > + void **data) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct coresight_device *helper; > + struct ctcu_drvdata *drvdata; > + int port; > + > + if (!csdev) > + return false; > + > + helper = coresight_get_helper(csdev, CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); > + if (!helper) > + return false; > + > + port = coresight_get_in_port_dest(csdev, helper); > + if (port < 0) > + return false; > + > + drvdata = dev_get_drvdata(helper->dev.parent); > + /* Something wrong when initialize byte_cntr_read_ops */ > + if (!drvdata->byte_cntr_read_ops) > + return false; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port]; > + /* Return the pointer of the ctcu_drvdata if byte-cntr has enabled */ > + if (byte_cntr_data && byte_cntr_data->thresh_val) { > + *data = (void *)drvdata->byte_cntr_read_ops; > + return true; > + } > + > + return false; > +} > + > static const struct coresight_ops_helper ctcu_helper_ops = { > .enable = ctcu_enable, > .disable = ctcu_disable, > + .qcom_byte_cntr_in_use = ctcu_qcom_byte_cntr_in_use, > }; > > static const struct coresight_ops ctcu_ops = { > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 4ac65c68bbf4..b5f052854b08 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -419,11 +419,14 @@ struct coresight_ops_source { > * > * @enable : Enable the device > * @disable : Disable the device > + * @qcom_byte_cntr_in_use: check whether the byte-cntr is enabled. > */ > struct coresight_ops_helper { > int (*enable)(struct coresight_device *csdev, enum cs_mode mode, > void *data); > int (*disable)(struct coresight_device *csdev, void *data); > + bool (*qcom_byte_cntr_in_use)(struct coresight_device *csdev, > + void **data); > }; > > > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

← Newer
1
...
7
8
9
10
11
12
13
...
252
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight