Since the commit:
18049c8cff9 ("perf/aux: Allocate non-contiguous AUX pages by default")
it changed the AUX buffer allocator to allocate AUX pages page-by-page
(order=0) unless a PMU explicitly asks for contiguous allocations via
the capability flag PERF_PMU_CAP_AUX_PREFER_LARGE. The goal was to make
AUX allocation more memory-friendly by default, because not all PMUs
require physically contiguous AUX pages and large contiguous allocations
can contribute to fragmentation on long-running systems.
However, Arm SPE and CoreSight/TRBE rely on page-table translation when
writing trace data to memory. With page-by-page AUX allocation, a large
AUX buffer is mapped with many small mappings. This increases TLB
pressure, in practice this can increase trace-buffer latency due to
table translation walks (TTW) and contribute to trace discontinuities.
This series restores large AUX allocation for Arm CoreSight and SPE by
setting PERF_PMU_CAP_AUX_PREFER_LARGE.
This is intended to work together with the mm large-mapping series [1].
That series allows vmap() to map physically contiguous pages with
larger granules. With this series, perf first tries larger-order AUX
allocations, and the vmap() code can then create larger mappings for the
contiguous chunks.
The fragmentation concern from commit 18049c8cff9c should not block this
opt-in. PERF_PMU_CAP_AUX_PREFER_LARGE is a preference, not a hard
requirement. The AUX allocator already falls back to smaller orders when
a high-order allocation fails. So this series gives Arm trace PMUs the
performance benefit when large chunks are available.
The comparison below uses a baseline that already includes the mm
large-mapping series [1]. "Baseline" means that the mm series is applied
but this Arm PMU series is not. "Large AUX" means the same kernel plus
this series. Some configurations to mitigate noise during test:
1) The tests were run with CPU10 isolated with the kernel parameter
"isolcpus=10".
2) CPU10 was used as the traced CPU, the PMU counter CPU, and the
workload CPU. The perf control tasks were pinned to CPU2 so that
they did not add extra work on CPU10.
3) Each test was run for 10 iterations, and the tables report the
average counter values across those runs.
The results show that using larger AUX mappings reduces the TLB pressure.
This is mainly visible in the refill events: CoreSight/TRBE shows a
large drop in l2d_tlb_refill and a smaller reduction in l1d_tlb_refill,
while SPE also reduces l2d_tlb_refill. The dtlb_walk event also drops in
both tests, which shows fewer data TLB walks after the AUX buffer can be
mapped with larger granules.
ETM sparse branch delay (cs_etm, AUX 1GB)
taskset -c 2 perf stat -C 10 -e cycles:u,instructions:u,dtlb_walk:u,l1d_tlb:u,l1d_tlb_refill:u,l2d_tlb_refill:u \
-- taskset -c 2 perf record -C 10 -m ,1G -e cs_etm// \
-- taskset -c 10 ./sparse_branch_delay.elf
| | Baseline | Large map | | |
| Metric | Avg. | Avg. | Delta | Change |
|----------------+-----------+-----------+------------+---------|
| dtlb_walk | 72.8 | 63.9 | -8.9 | -12.23% |
| l1d_tlb | 7,434.4 | 1,982.2 | -5,452.2 | -73.34% |
| l1d_tlb_refill | 163.7 | 148.2 | -15.5 | -9.47% |
| l2d_tlb_refill | 161,884.9 | 513.1 | -161,371.8 | -99.68% |
SPE dd memory copy (arm_spe, AUX 512MB)
taskset -c 2 perf stat -C 10 -e cycles:u,instructions:u,dtlb_walk:u,l1d_tlb:u,l1d_tlb_refill:u,l2d_tlb_refill:u \
-- taskset -c 2 perf record -C 10 -m ,512M -e arm_spe_0/ts_enable=1,pa_enable=1,period=64,min_latency=0/ \
-- taskset -c 10 dd if=/dev/zero of=/dev/shm/dd_mem_test bs=1M count=1024 status=progress
| | Baseline | Large map | | |
| Metric | Avg. | Avg. | Delta | Change |
|----------------+-----------+-----------+------------+---------|
| dtlb_walk | 1,760.2 | 1,387.9 | -372.3 | -21.15% |
| l1d_tlb | 257,312.4 | 251,460.9 | -5,851.5 | -2.27% |
| l1d_tlb_refill | 15,921.9 | 15,933.6 | 11.7 | +0.07% |
| l2d_tlb_refill | 4,285.0 | 2,796.5 | -1,488.5 | -34.74% |
Note that after setting PREFER_LARGE for CoreSight and SPE, the existing
AUX trace drivers either prefer large pages or, in the case of Intel
BTS/PT, use the stronger AUX_NO_SG constraint. We can refactor this
later by either dropping PREFER_LARGE entirely or reversing the flag if
a driver needs discrete pages. For now, keep PREFER_LARGE to preserve
flexibility in the allocation policy.
[1] https://lore.kernel.org/linux-mm/20260715120813.3609949-1-jiangwen6@xiaomi.…
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Dev Jain (1):
coresight: perf: Prefer large AUX mappings
Leo Yan (1):
perf: arm_spe: Prefer large AUX mappings
drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ++-
drivers/perf/arm_spe_pmu.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
---
base-commit: db2ddb87143519e20a95aa36c60b36107b736a58
change-id: 20260717-perf_aux_trace_large_granule-d9b30cc14b5a
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
Hi Greg
Please find this pull request for CoreSight subsystem targeting v7.3.
Almost all of them are fixes to the existing code, along with a MAINTAINERS
update for HiSilicon PTT driver.
Kindly pull
Suzuki
The following changes since commit 8cdeaa50eae8dad34885515f62559ee83e7e8dda:
Linux 7.2-rc2 (2026-07-05 14:44:06 -1000)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v7.3
for you to fetch changes up to 9e3604d7369cfc0110100eb1a0acab1865ee2d18:
coresight: etm4x: remove redundant fields in etmv4_save_state (2026-08-07 10:45:11 +0100)
----------------------------------------------------------------
coresight: Updates for Linux v7.3
This is relatively smaller update for CoreSight/hwtracing subsystem updates.
- MAINTAINERS update for HiSilicon PCI Trace & Tune drivers
- Minor fixes to hisi_ptt driver
- Various fixes to the coresight etm4x dirvers
Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
----------------------------------------------------------------
Jonathan Cameron (1):
MAINTAINERS: Update HiSilicon PCI Trace and Tune maintainer
Kuan-Wei Chiu (1):
coresight: etm3x: Fix cntr_val_show() to match cntr_val_store() behavior
Sanman Pradhan (2):
hwtracing: hisi_ptt: Propagate DMA reset timeout in trace_start()
hwtracing: hisi_ptt: Remove unnecessary trace buffer zeroing in trace_start()
Yeoreum Yun (5):
coresight: etm4x: fix wrong check of etm4x_sspcicrn_present()
coresight: etm4x: fix underflow for usage of (nrseqstate - 1)
coresight: etm4x: fix leaked trace id
coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
coresight: etm4x: remove redundant fields in etmv4_save_state
MAINTAINERS | 3 +-
.../hwtracing/coresight/coresight-etm3x-sysfs.c | 15 ++----
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 59 +++++++++++++---------
.../hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++-
drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++---
drivers/hwtracing/ptt/hisi_ptt.c | 25 ++++-----
7 files changed, 63 insertions(+), 59 deletions(-)
On 03/08/26 4:55 AM, Yuho Choi wrote:
> coresight_get_ref() ignores the return value of pm_runtime_get_sync()
> and reports success even when runtime resume fails. A path is then built
> and the CoreSight device may be accessed while it remains powered off.
>
> Use pm_runtime_resume_and_get() so a failed resume is reported and its
> runtime PM usage reference is rolled back. Drop the module and device
> references acquired before the resume attempt when it fails.
>
> Fixes: 5da5325fa856 ("coresight: moving PM runtime operations to core framework")
> Signed-off-by: Yuho Choi <dbgh9129(a)gmail.com>
> ---
Should 'Fixes:' be tagging the following commit - which had introduced
coresight_get_ref() unconditionally calling pm_runtime_get_sync() ?
32b0707a4182 ("coresight: Add try_get_module() in coresight_grab_device()")
> drivers/hwtracing/coresight/coresight-core.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 6d65c43d574f..77d05b360484 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -843,7 +843,11 @@ static bool coresight_get_ref(struct coresight_device *csdev)
> goto err_module;
>
> /* Make sure the device is powered on */
> - pm_runtime_get_sync(parent);
> + if (pm_runtime_resume_and_get(parent) < 0) {
> + module_put(drv->owner);
> + goto err_module;
> + }
> +
> return true;
>
> err_module:
