Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejfi...
Hi Chunyan,
CoreSight components that output trace onto the ATB (into a funnel or other interconnect component) will need either an ATCLK or be clocked synchronously to this clock.
This is transparent to the programming and use of STM.
Regards
Mike
---------------------------------------------------------------- Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE ----------------------------------------------------------------
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf ib.html
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hi Chunyan,
A quick follow up to this after a discussion with one of the trace architects. The STM drives the trace ATB interface at the main STM clock speed (the CLK input). It is up to the system designer to choose when they bridge from the CLK to the ATCLK for input to ATCLKed trace components.
Regards
Mike
---------------------------------------------------------------- Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE ----------------------------------------------------------------
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf ib.html
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hi, Mike
Thanks for your answer!
On Wed, Jan 27, 2016 at 8:16 PM, Mike Leach Mike.Leach@arm.com wrote:
Hi Chunyan,
A quick follow up to this after a discussion with one of the trace architects. The STM drives the trace ATB interface at the main STM clock speed (the CLK input). It is up to the system designer to choose when they bridge from the CLK to the ATCLK for input to ATCLKed trace components.
The system designer, you meant the hardware system designer?
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
Thanks, Chunyan
Regards
Mike
Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf ib.html
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
The system designer, you meant the hardware system designer?
Yes
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
ATCLK and the ATB is all hardware.
You only need to deal with issues outlined in the programmers model. ATB and clocking is completely transparent to the software.
Regards
Mike
---------------------------------------------------------------- Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE ----------------------------------------------------------------
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 12:46 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: Re: ATCLK on STM
Hi, Mike
Thanks for your answer!
On Wed, Jan 27, 2016 at 8:16 PM, Mike Leach Mike.Leach@arm.com wrote:
Hi Chunyan,
A quick follow up to this after a discussion with one of the trace architects.
The STM drives the trace ATB interface at the main STM clock speed (the CLK input).
It is up to the system designer to choose when they bridge from the CLK to
the ATCLK for input to ATCLKed trace components.
The system designer, you meant the hardware system designer?
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
Thanks, Chunyan
Regards
Mike
Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf
ib.html
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On 27 January 2016 at 06:19, Mike Leach Mike.Leach@arm.com wrote:
The system designer, you meant the hardware system designer?
Yes
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
ATCLK and the ATB is all hardware.
You only need to deal with issues outlined in the programmers model. ATB and clocking is completely transparent to the software.
I agree, the clocking itself is transparent to SW. But if present, the clocks still have to be requested by kernel drivers. As such if the CS-STM has an ATCLK interface and that interface is active, it has to be requested in the same way other CS divers do.
Regards
Mike
Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 12:46 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: Re: ATCLK on STM
Hi, Mike
Thanks for your answer!
On Wed, Jan 27, 2016 at 8:16 PM, Mike Leach Mike.Leach@arm.com wrote:
Hi Chunyan,
A quick follow up to this after a discussion with one of the trace architects.
The STM drives the trace ATB interface at the main STM clock speed (the CLK input).
It is up to the system designer to choose when they bridge from the CLK to
the ATCLK for input to ATCLKed trace components.
The system designer, you meant the hardware system designer?
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
Thanks, Chunyan
Regards
Mike
Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf
ib.html
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
-
Chunyan Zhang -
Mathieu Poirier -
Mike Leach