On Wed, Apr 22, 2026 at 02:21:54PM +0100, Yeoreum Yun wrote:
[...]
@@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); for (i = 0; i < caps->nr_ss_cmp; i++) {
/* always clear status bit on restart if using single-shot */if (config->ss_ctrl[i] || config->ss_pe_cmp[i])config->ss_status[i] &= ~TRCSSCSRn_STATUS;etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
/* always clear status and pending bits on restart if using single-shot */etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i));
I am not confident what is the right way to handle the pending bit. I looked a bit Arm ARM but still no clue. In particular, I suspect it may need to be handled when disabling the trace in etm4_disable_hw().
Let's make it clear with some internal check.
@@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
Similarly, the question is: if it is in a pending state, how can we ensure the state machine works properly with the new settings?
raw_spin_unlock(&drvdata->spinlock); return size; }
@@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx = config->ss_idx; config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
- /* must clear bit 31 and 30 in related status register on programming */
- drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
Ditto.
Thanks, Leo