CoreSight

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2606 discussions

Re: [PATCH RESEND 1/2] dt-bindings: arm: qcom,coresight-tpda: drop redundant type from ports

by Suzuki K Poulose

Hi Krzysztof On 25/03/2024 10:40, Krzysztof Kozlowski wrote: > "in-ports" and "out-ports" are defined by graph schema, so defining its > type is redundant. > > Acked-by: Rob Herring <robh(a)kernel.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> Both patches look good to me. How would you like to pull this ? I could queue them for v6.10 via coresight tree. If you would like to take them, Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Suzuki > > --- > > No changes, but patches were split from previous set. First patch in > previouis series was being discussed, so let's just make these accepted. > > v1: https://lore.kernel.org/all/20231206115332.22712-1-krzysztof.kozlowski@lina… > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > index ea3c5db6b52d..7fbd855a66a0 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > @@ -66,13 +66,11 @@ properties: > - const: apb_pclk > > in-ports: > - type: object > description: | > Input connections from TPDM to TPDA > $ref: /schemas/graph.yaml#/properties/ports > > out-ports: > - type: object > description: | > Output connections from the TPDA to legacy CoreSight trace bus. > $ref: /schemas/graph.yaml#/properties/ports

1 year, 9 months

Re: [PATCH 1/4] dt-bindings: arm: qcom,coresight-funnel: Add label for multi-ouput

by Tingwei Zhang

On 3/21/2024 10:42 PM, Rob Herring wrote: > On Thu, Mar 21, 2024 at 04:32:04PM +0800, Tao Zhang wrote: >> Add new property "label" to label the source corresponding to the >> output connection. When the funnel supports multi-output, this >> property needs to be introduced to mark which source component a >> certain output connection corresponds to. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> .../arm/arm,coresight-dynamic-funnel.yaml | 34 ++++++++++++++++--- >> 1 file changed, 30 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> index 44a1041cb0fc..cde62c286d29 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> @@ -66,13 +66,39 @@ properties: >> $ref: /schemas/graph.yaml#/properties/port >> >> out-ports: >> - $ref: /schemas/graph.yaml#/properties/ports >> - additionalProperties: false >> - >> + type: object >> properties: >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 0 >> + >> port: >> + type: object >> + >> + patternProperties: >> + '^port(@[0-7])?$': >> + type: object >> description: Output connection to CoreSight Trace bus >> - $ref: /schemas/graph.yaml#/properties/port > > Nope, now you have no constraints on port node properties. Please look > at how other bindings are done to add properties on endpoint node. > Thanks for pointing this out, Rob. Shall we ref port-base and endpoint-base then add new properties on endpoint? In this way, the redundant code from port schema is not required. >> + >> + patternProperties: >> + "^endpoint(@[0-9a-f]+)?$": >> + type: object >> + properties: >> + remote-endpoint: >> + description: | >> + phandle to an 'endpoint' subnode of a remote device node. >> + $ref: /schemas/types.yaml#/definitions/phandle > > Don't need this. > >> + label: >> + description: Label the source corresponding to the output connection >> + $ref: /schemas/types.yaml#/definitions/string > > label already has a type. > > As this node is an output, aren't you labeling what the destination is, > not the "source"? > > Why can't you look at the remote connection to identify what it is? > This funnel can route data stream from different trace source to different output ports. This lable property is added to describe which source is routed to this output port. For example, the graph is as below. Funnel3 routes trace data from TPDM0 to output[0] and output[0] of funnel3 is connected to input[0] of TPDA0. While Funnels routes trace data from TPDM1 to output[1] which connects to input[1] of TPDA0. Hope that clarifies this a little bit. |---------| |---------| |---------| |---------| |---------| | TPDM0 | | TPDM1 | | TPDM2 | | TPDM3 | | TPDM4 | |---------| |---------| |---------| |---------| |---------| | | | | | | | | | | | | | | | |-----| |-----| |-----| |-----| | | | | | | | | | | | [0]| |[1] [0]| |[1] | \-------------/ \-------------/ \------------/ \ FUNNEL0 / \ FUNNEL1 / \ FUNNEL2 / ----------- ----------- ----------- | | | \-------------/ \-------------/ | \ FUNNEL3 / \ FUNNEL4 / | ----------- ----------- | | | | | [0]| |[1] [0]| |[1] | | |---------- | | | | | | | | |-------| | |------- | | |--------- | | | | | | | | | | | [0]| |[1] |[2] |[3] |[4] \ ---------------------------------------------------/ \ TPDA0 / \ / ------------------------------------------------ > >> + oneOf: >> + - required: >> + - port >> + - required: >> + - "#address-cells" >> + - "#size-cells" > > The common schema that you removed handles this. > > Rob -- Thanks, Tingwei

1 year, 9 months

Re: [PATCH 1/4] dt-bindings: arm: qcom,coresight-funnel: Add label for multi-ouput

by Suzuki K Poulose

On 21/03/2024 14:42, Rob Herring wrote: > On Thu, Mar 21, 2024 at 04:32:04PM +0800, Tao Zhang wrote: >> Add new property "label" to label the source corresponding to the >> output connection. When the funnel supports multi-output, this >> property needs to be introduced to mark which source component a >> certain output connection corresponds to. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> .../arm/arm,coresight-dynamic-funnel.yaml | 34 ++++++++++++++++--- >> 1 file changed, 30 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> index 44a1041cb0fc..cde62c286d29 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> @@ -66,13 +66,39 @@ properties: >> $ref: /schemas/graph.yaml#/properties/port >> >> out-ports: >> - $ref: /schemas/graph.yaml#/properties/ports >> - additionalProperties: false >> - >> + type: object >> properties: >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 0 >> + >> port: >> + type: object >> + >> + patternProperties: >> + '^port(@[0-7])?$': >> + type: object >> description: Output connection to CoreSight Trace bus >> - $ref: /schemas/graph.yaml#/properties/port > > Nope, now you have no constraints on port node properties. Please look > at how other bindings are done to add properties on endpoint node. > >> + >> + patternProperties: >> + "^endpoint(@[0-9a-f]+)?$": >> + type: object >> + properties: >> + remote-endpoint: >> + description: | >> + phandle to an 'endpoint' subnode of a remote device node. >> + $ref: /schemas/types.yaml#/definitions/phandle > > Don't need this. > >> + label: >> + description: Label the source corresponding to the output connection >> + $ref: /schemas/types.yaml#/definitions/string > > label already has a type. > > As this node is an output, aren't you labeling what the destination is, > not the "source"? > > Why can't you look at the remote connection to identify what it is? +1 Suzuki > > >> + oneOf: >> + - required: >> + - port >> + - required: >> + - "#address-cells" >> + - "#size-cells" > > The common schema that you removed handles this. > > Rob

1 year, 9 months

[PATCH V6 00/11] coresight: Move remaining AMBA ACPI devices into platform driver

by Anshuman Khandual

This moves remaining AMBA ACPI devices into respective platform drivers for enabling ACPI based power management support. This series applies on latest coresight next. This series has been built, and boot tested on a DT based (RB5) and ACPI supported coresight platform (N1SDP). https://git.gitlab.arm.com/linux-arm/linux-anshuman.git (amba_other_acpi_migration_v6) Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Maxime Coquelin <mcoquelin.stm32(a)gmail.com> Cc: Alexandre Torgue <alexandre.torgue(a)foss.st.com> Cc: linux-acpi(a)vger.kernel.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-stm32(a)st-md-mailman.stormreply.com Changes in V6: - Dropped Jame's RB tag from [PATCH 3/11] - Added clk_disable_unprepare() for pclk in replicator_probe() error path - Added clk_disable_unprepare() for pclk in funnel_probe() error path - Added clk_put() for pclk in catu_platform_probe() error path - Added clk_put() for pclk in debug_platform_probe() error path - Added WARN_ON(!drvdata) check in replicator_platform_remove() - Added WARN_ON(!drvdata) check in funnel_platform_remove() - Added WARN_ON(!drvdata) check in catu_platform_remove() - Added WARN_ON(!drvdata) check in tpiu_platform_remove() - Added WARN_ON(!drvdata) check in tmc_platform_remove() - Added WARN_ON(!drvdata) check in stm_platform_remove() - Added WARN_ON(!drvdata) check in debug_platform_remove() - Added additional elements for all acpi_device_id[] updates Changes in V5: https://lore.kernel.org/all/20240222082142.3663983-1-anshuman.khandual@arm.… - Used table->mask to filter out bits from pid in coresight_get_uci_data_from_amba() - Dropped custom masks such as STM_AMBA_MASK and TMC_AMBA_MASK - Modified tmc_etr_setup_caps() to accept struct csdev_access argument - Reverted back tmc_etr_setup_caps() call site position in tmc_probe() - Changed replicator and funnel devices to use the new helpers earlier in series - Updated the commit messages regarding xxx_probe() refactoring and renaming Changes in V4: https://lore.kernel.org/all/20240123054608.1790189-1-anshuman.khandual@arm.… - Fixed PM imbalance in etm4_probe() error path with pm_runtime_disable() - Restored back the pm_runtime_disable() on platform probe error paths in replicator, funnel, catu, tpiu, tmc and stm devices - Dropped dev_caps argument from __tmc_probe() - Changed xxxx_platform_remove() for platform_driver->remove_new() callback Changes in V3: https://lore.kernel.org/all/20231208053939.42901-1-anshuman.khandual@arm.co… - Split coresight_init_driver/remove_driver() helpers into a separate patch - Added 'drvdata->pclk' comments in replicator, funnel, tpiu, tmc, and stm devices - Updated funnel, and replicator drivers to use these new helpers - Check for drvdata instead of drvdata->pclk in suspend and resume paths in catu, tmc and debug devices - Added patch to extract device name from AMBA pid based table lookup for stm - Added patch to extract device properties from AMBA pid based table look for tmc - Dropped pm_runtime_put() from common __probe() functions - Handled pm_runtime_put() in AMBA driver in success path - Handled pm_runtime_put() in platform driver in both success and error paths Changes in V2: https://lore.kernel.org/all/20231201062053.1268492-1-anshuman.khandual@arm.… - Dropped redundant devm_ioremap_resource() hunk from tmc_platform_probe() - Defined coresight_[init|remove]_driver() for both AMBA/platform drivers - Changed catu, tmc, tpiu, stm and debug coresight drivers to use the new helpers avoiding build issues arising from module_amba_driver(), and module_platform_driver() being on the same file Changes in V1: https://lore.kernel.org/all/20231027072943.3418997-1-anshuman.khandual@arm.… - Replaced all IS_ERR() instances with IS_ERR_OR_NULL() as per Suzuki Changes in RFC: https://lore.kernel.org/all/20230921042040.1334641-1-anshuman.khandual@arm.… Anshuman Khandual (11): coresight: etm4x: Fix unbalanced pm_runtime_enable() coresight: stm: Extract device name from AMBA pid based table lookup coresight: tmc: Extract device properties from AMBA pid based table lookup coresight: Add helpers registering/removing both AMBA and platform drivers coresight: replicator: Move ACPI support from AMBA driver to platform driver coresight: funnel: Move ACPI support from AMBA driver to platform driver coresight: catu: Move ACPI support from AMBA driver to platform driver coresight: tpiu: Move ACPI support from AMBA driver to platform driver coresight: tmc: Move ACPI support from AMBA driver to platform driver coresight: stm: Move ACPI support from AMBA driver to platform driver coresight: debug: Move ACPI support from AMBA driver to platform driver drivers/acpi/arm64/amba.c | 8 - drivers/hwtracing/coresight/coresight-catu.c | 146 ++++++++++++++--- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 29 ++++ .../hwtracing/coresight/coresight-cpu-debug.c | 146 ++++++++++++++--- .../coresight/coresight-etm4x-core.c | 3 + .../hwtracing/coresight/coresight-funnel.c | 87 +++++----- drivers/hwtracing/coresight/coresight-priv.h | 10 ++ .../coresight/coresight-replicator.c | 82 +++++----- drivers/hwtracing/coresight/coresight-stm.c | 116 +++++++++++-- .../hwtracing/coresight/coresight-tmc-core.c | 154 +++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 103 ++++++++++-- include/linux/coresight.h | 7 + 14 files changed, 729 insertions(+), 165 deletions(-) -- 2.25.1

1 year, 10 months

[PATCH V5 00/11] coresight: Move remaining AMBA ACPI devices into platform driver

by Anshuman Khandual

This moves remaining AMBA ACPI devices into respective platform drivers for enabling ACPI based power management support. This series applies on kernel v6.8-rc5 release. This series has been built, and boot tested on a DT based (RB5) and ACPI supported coresight platform (N1SDP). https://git.gitlab.arm.com/linux-arm/linux-anshuman.git (amba_other_acpi_migration_v5) Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Maxime Coquelin <mcoquelin.stm32(a)gmail.com> Cc: Alexandre Torgue <alexandre.torgue(a)foss.st.com> Cc: linux-acpi(a)vger.kernel.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-stm32(a)st-md-mailman.stormreply.com Changes in V5: - Used table->mask to filter out bits from pid in coresight_get_uci_data_from_amba() - Dropped custom masks such as STM_AMBA_MASK and TMC_AMBA_MASK - Modified tmc_etr_setup_caps() to accept struct csdev_access argument - Reverted back tmc_etr_setup_caps() call site position in tmc_probe() - Changed replicator and funnel devices to use the new helpers earlier in series - Updated the commit messages regarding xxx_probe() refactoring and renaming Changes in V4: https://lore.kernel.org/all/20240123054608.1790189-1-anshuman.khandual@arm.… - Fixed PM imbalance in etm4_probe() error path with pm_runtime_disable() - Restored back the pm_runtime_disable() on platform probe error paths in replicator, funnel, catu, tpiu, tmc and stm devices - Dropped dev_caps argument from __tmc_probe() - Changed xxxx_platform_remove() for platform_driver->remove_new() callback Changes in V3: https://lore.kernel.org/all/20231208053939.42901-1-anshuman.khandual@arm.co… - Split coresight_init_driver/remove_driver() helpers into a separate patch - Added 'drvdata->pclk' comments in replicator, funnel, tpiu, tmc, and stm devices - Updated funnel, and replicator drivers to use these new helpers - Check for drvdata instead of drvdata->pclk in suspend and resume paths in catu, tmc and debug devices - Added patch to extract device name from AMBA pid based table lookup for stm - Added patch to extract device properties from AMBA pid based table look for tmc - Dropped pm_runtime_put() from common __probe() functions - Handled pm_runtime_put() in AMBA driver in success path - Handled pm_runtime_put() in platform driver in both success and error paths Changes in V2: https://lore.kernel.org/all/20231201062053.1268492-1-anshuman.khandual@arm.… - Dropped redundant devm_ioremap_resource() hunk from tmc_platform_probe() - Defined coresight_[init|remove]_driver() for both AMBA/platform drivers - Changed catu, tmc, tpiu, stm and debug coresight drivers to use the new helpers avoiding build issues arising from module_amba_driver(), and module_platform_driver() being on the same file Changes in V1: https://lore.kernel.org/all/20231027072943.3418997-1-anshuman.khandual@arm.… - Replaced all IS_ERR() instances with IS_ERR_OR_NULL() as per Suzuki Changes in RFC: https://lore.kernel.org/all/20230921042040.1334641-1-anshuman.khandual@arm.… Anshuman Khandual (11): coresight: etm4x: Fix unbalanced pm_runtime_enable() coresight: stm: Extract device name from AMBA pid based table lookup coresight: tmc: Extract device properties from AMBA pid based table lookup coresight: Add helpers registering/removing both AMBA and platform drivers coresight: replicator: Move ACPI support from AMBA driver to platform driver coresight: funnel: Move ACPI support from AMBA driver to platform driver coresight: catu: Move ACPI support from AMBA driver to platform driver coresight: tpiu: Move ACPI support from AMBA driver to platform driver coresight: tmc: Move ACPI support from AMBA driver to platform driver coresight: stm: Move ACPI support from AMBA driver to platform driver coresight: debug: Move ACPI support from AMBA driver to platform driver drivers/acpi/arm64/amba.c | 8 - drivers/hwtracing/coresight/coresight-catu.c | 142 +++++++++++++--- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 29 ++++ .../hwtracing/coresight/coresight-cpu-debug.c | 141 ++++++++++++++-- .../coresight/coresight-etm4x-core.c | 3 + .../hwtracing/coresight/coresight-funnel.c | 86 +++++----- drivers/hwtracing/coresight/coresight-priv.h | 10 ++ .../coresight/coresight-replicator.c | 81 +++++----- drivers/hwtracing/coresight/coresight-stm.c | 115 +++++++++++-- .../hwtracing/coresight/coresight-tmc-core.c | 153 +++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 102 ++++++++++-- include/linux/coresight.h | 7 + 14 files changed, 721 insertions(+), 159 deletions(-) -- 2.25.1

1 year, 10 months

Can OpenCSD traces be displayed with tools like Trace Compass?

by Brian Hutchinson

Hi, I've long been interested in the ARM Coresight tools and played around with OpenOCD some. I'm just now getting into OpenCSD so please forgive the noob question but I did search the archives first. I'm curious if the format of OpenCSD traces is such that other tools like TraceCompass can unwind and graphically show them. I'm wondering if I can get like LTTng type info (system wide big picture - kernel plus userspace) out of OpenCSD but take advantage of the built in hardware (ETM etc.) that shouldn't introduce as much latency as other tools like LTTng, trace-cmd etc. Thanks, Brian

1 year, 10 months

[GIT PULL] coresight: hwtracing subsystem updates for v6.9

by Suzuki K Poulose

Hi Greg, Please find the updates for coresight/hwtracing subsystem updates targeting Linux v6.9. Kindly pull. Suzuki The following changes since commit 841c35169323cd833294798e58b9bf63fa4fa1de: Linux 6.8-rc4 (2024-02-11 12:18:13 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.9 for you to fetch changes up to a4f3057d19ffe1f5a7b9320303471a6725f11379: coresight-tpda: Change qcom,dsb-element-size to qcom,dsb-elem-bits (2024-02-27 11:26:45 +0000) ---------------------------------------------------------------- coresight: hwtracing subsystem updates for v6.9 Changes targeting Linux v6.9 include: - CoreSight: Enable W=1 warnings as default - CoreSight: Clean up sysfs/perf mode handling for tracing - Support for Qualcomm TPDM CMB Dataset - Miscellaneous fixes to the CoreSight subsystem - Fix for hisi_ptt PMU to reject events targeting other PMUs Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Greg Kroah-Hartman (1): coresight: make coresight_bustype const James Clark (16): coresight: Fix uninitialized struct warnings coresight: etm3x: Fix build warning coresight: Fix undeclared variable warnings from sparse checker coresight: Make current W=1 warnings default coresight: Fix issue where a source device's helpers aren't disabled coresight: Make language around "activated" sinks consistent coresight: Remove ops callback checks coresight: Move mode to struct coresight_device coresight: Remove the 'enable' field. coresight: Move all sysfs code to sysfs file coresight: Remove atomic type from refcnt coresight: Remove unused stubs coresight: Add explicit member initializers to coresight_dev_type coresight: Add helper for atomically taking the device coresight: Add a helper for getting csdev->mode coresight: Add helper for setting csdev->mode Mao Jinlong (3): coresight: etm4x: Set skip_power_up in etm4_init_arch_data function dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size coresight-tpda: Change qcom,dsb-element-size to qcom,dsb-elem-bits Suzuki K Poulose (1): coresight: tpdm: Fix build break due to uninitialised field Tao Zhang (10): coresight-tpdm: Optimize the store function of tpdm simple dataset coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size coresight-tpdm: Add CMB dataset support coresight-tpda: Add support to configure CMB element coresight-tpdm: Add support to configure CMB coresight-tpdm: Add pattern registers support for CMB coresight-tpdm: Add timestamp control register support for the CMB dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register coresight-tpdm: Add msr register support for CMB Yang Jihong (1): hwtracing: hisi_ptt: Move type check to the beginning of hisi_ptt_pmu_event_init() .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 87 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 40 +- drivers/hwtracing/coresight/Makefile | 20 + drivers/hwtracing/coresight/coresight-cfg-afdo.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 498 ++------------------- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 31 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-etm.h | 2 - drivers/hwtracing/coresight/coresight-etm3x-core.c | 27 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 38 +- drivers/hwtracing/coresight/coresight-etm4x.h | 1 - drivers/hwtracing/coresight/coresight-funnel.c | 4 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- drivers/hwtracing/coresight/coresight-replicator.c | 2 +- drivers/hwtracing/coresight/coresight-stm.c | 32 +- drivers/hwtracing/coresight/coresight-sysfs.c | 391 ++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc-core.c | 4 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 46 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 33 +- drivers/hwtracing/coresight/coresight-tmc.h | 2 - drivers/hwtracing/coresight/coresight-tpda.c | 145 +++--- drivers/hwtracing/coresight/coresight-tpda.h | 6 + drivers/hwtracing/coresight/coresight-tpdm.c | 459 +++++++++++++++++-- drivers/hwtracing/coresight/coresight-tpdm.h | 114 +++++ drivers/hwtracing/coresight/coresight-tpiu.c | 16 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 24 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 - drivers/hwtracing/ptt/hisi_ptt.c | 6 +- include/linux/coresight.h | 148 +++--- 31 files changed, 1385 insertions(+), 811 deletions(-)

1 year, 10 months

[PATCH v3 0/2] coresight: tpdm: Change qcom,dsb-element-size to qcom,dsb-elem-bits

by Mao Jinlong

As unit of dsb element size is bit, change qcom,dsb-element-size to qcom,dsb-elem-bits. And CMB uses -bits suffix as well. There is no TPDM node in any DT now. Make such change before any TPDM node is added to DT. Change since V2: 1. Use fwnode_property_read_u32 to read the proprety value. Change since V1: 1. Update the commit message for dt-binding. 2. Fix the dt_binding_check error for dt-binding change. Mao Jinlong (2): dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size coresight-tpda: Change qcom,dsb-element-size to qcom,dsb-elem-bits .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 5 ++--- drivers/hwtracing/coresight/coresight-tpda.c | 4 ++-- drivers/hwtracing/coresight/coresight-tpda.h | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) -- 2.41.0

1 year, 10 months

Re: [PATCH] Correcting the spelling mistake in Coresight subsystem

by Anshuman Khandual

Although a trivial typo fix in documentation, the subject line still might need "doc: ABI: coresight: <typo fix in tmc>" format etc but I guess it's upto the maintainers. On 2/27/24 00:32, Prabhav Kumar Vaish wrote: > Changes : > - "avaialble" corrected to "available" in "Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc" > > Signed-off-by: Prabhav Kumar Vaish <pvkumar5749404(a)gmail.com> > --- > Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > index 96aafa66b4a5..339cec3b2f1a 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc > @@ -97,7 +97,7 @@ Date: August 2023 > KernelVersion: 6.7 > Contact: Anshuman Khandual <anshuman.khandual(a)arm.com> > Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available > - for the users to configure explicitly. This file is avaialble only > + for the users to configure explicitly. This file is available only LGTM Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > for TMC ETR devices. > > What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred

1 year, 10 months

Re: [PATCH v6 5/8] arm64: KVM: Add iflag for FEAT_TRF

by James Clark

On 26/02/2024 13:35, Marc Zyngier wrote: > On Mon, 26 Feb 2024 11:30:33 +0000, > James Clark <james.clark(a)arm.com> wrote: >> >> Add an extra iflag to signify if the TRFCR register is accessible. > > That's not what this flag means: it indicates whether TRFCR needs to > be saved. At lease that's what the name suggests. > >> Because TRBE requires FEAT_TRF, DEBUG_STATE_SAVE_TRBE still has the same >> behavior even though it's only set when FEAT_TRF is present. > > This sentence seems completely out of context, because you didn't > explain that you were making TRBE *conditional* on TRF being > implemented, as per the architecture requirements. > >> >> The following holes are left in struct kvm_vcpu_arch, but there aren't >> enough other 8 bit fields to rearrange it to leave any hole smaller than >> 7 bytes: >> >> u8 cflags; /* 2292 1 */ >> /* XXX 1 byte hole, try to pack */ >> u16 iflags; /* 2294 2 */ >> u8 sflags; /* 2296 1 */ >> bool pause; /* 2297 1 */ >> /* XXX 6 bytes hole, try to pack */ > > I don't think that's particularly useful in a commit message, but more > relevant to the cover letter. However, see below. > >> >> Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> Signed-off-by: James Clark <james.clark(a)arm.com> >> --- >> arch/arm64/include/asm/kvm_host.h | 4 +++- >> arch/arm64/kvm/debug.c | 24 ++++++++++++++++++++---- >> 2 files changed, 23 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h >> index 21c57b812569..85b5477bd1b4 100644 >> --- a/arch/arm64/include/asm/kvm_host.h >> +++ b/arch/arm64/include/asm/kvm_host.h >> @@ -569,7 +569,7 @@ struct kvm_vcpu_arch { >> u8 cflags; >> >> /* Input flags to the hypervisor code, potentially cleared after use */ >> - u8 iflags; >> + u16 iflags; >> >> /* State flags for kernel bookkeeping, unused by the hypervisor code */ >> u8 sflags; >> @@ -779,6 +779,8 @@ struct kvm_vcpu_arch { >> #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) >> /* vcpu running in HYP context */ >> #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) >> +/* Save trace filter controls */ >> +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(8)) > > I'd rather you cherry-pick [1] and avoid expanding the iflags. > > [1] https://lore.kernel.org/r/20240226100601.2379693-4-maz@kernel.org > > Now, I think the whole SPE/TRBE/TRCR flag management should be > improved, see below. > >> >> /* SVE enabled for host EL0 */ >> #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) >> diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c >> index ce8886122ed3..49a13e72ddd2 100644 >> --- a/arch/arm64/kvm/debug.c >> +++ b/arch/arm64/kvm/debug.c >> @@ -332,14 +332,30 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) >> !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) >> vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); >> >> - /* Check if we have TRBE implemented and available at the host */ >> - if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && >> - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) >> - vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); >> + /* >> + * Set SAVE_TRFCR flag if FEAT_TRF (TraceFilt) exists. This flag >> + * signifies that the exclude_host/exclude_guest settings of any active >> + * host Perf session on a core running a VCPU can be written into >> + * TRFCR_EL1 on guest switch. >> + */ >> + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) { >> + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); > > Can we avoid doing this unconditionally? It only makes sense to save > the trace crud if it is going to be changed, right? > Do you mean to see if kvm_guest_trfcr was non-zero (and would have to be changed) at VCPU load? I assumed that it could be modified between load and switch. That would mean there is no way to do it conditionally. I also assumed that's the reason SPE and TRBE were implemented like this, with the feat check at load and the enabled check at switch. It doesn't feel like TRFCR is any different to those two. Or do you mean to only set DEBUG_STATE_SAVE_TRFCR on switch if tracing was enabled? I suppose the names DEBUG_STATE_SAVE_SPE and DEBUG_STATE_SAVE_TRBE are slightly misleading because neither are actually saved if they weren't enabled. They're more like DEBUG_STATE_HAS_SPE and DEBUG_STATE_HAS_TRBE. >> + /* >> + * Check if we have TRBE implemented and available at the host. >> + * If it's in use at the time of guest switch then trace will >> + * need to be completely disabled. The architecture mandates >> + * FEAT_TRF with TRBE, so we only need to check for TRBE after >> + * TRF. >> + */ >> + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && >> + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) >> + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); >> + } >> } >> >> void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) >> { >> vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE); >> vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); >> + vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); >> } > > Dealing with flags that are strongly coupled in a disjoined way a > pretty bad idea. Look at the generated code, and realise we flip the > preempt flag on each access. > > Can we do better? You bet. The vcpu_{set,clear}_flags infrastructure > is capable of dealing with multiple flags at once, as demonstrated by > the way we deal with exception encoding. > Oops yeah I didn't realize that this was more than a bit set/clear. I will combine them. I think I could probably combine the TRBE/TRF set as well. Agree with the rest of the comments too. Thanks James > Something like: > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index addf79ba8fa0..3e50e535fdd4 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -885,6 +885,10 @@ struct kvm_vcpu_arch { > #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) > /* Save TRBE context if active */ > #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) > +/* Save Trace Filter Controls */ > +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(7)) > +/* Global debug mask */ > +#define DEBUG_STATE_SAVE_MASK __vcpu_single_flag(iflags, GENMASK(7, 5)) > > /* SVE enabled for host EL0 */ > #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) > diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c > index 8725291cb00a..f9b197a00582 100644 > --- a/arch/arm64/kvm/debug.c > +++ b/arch/arm64/kvm/debug.c > @@ -339,6 +339,6 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) > > void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) > { > - vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE); > - vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); > + if (!has_vhe()) > + vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_MASK); > } > > Thanks, > > M. >

1 year, 10 months

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