CoreSight

coresight@lists.linaro.org

5 participants
2611 discussions

by Mathieu Poirier

On 19 December 2016 at 07:45, Yehuda Yitschak <yehuday(a)marvell.com> wrote: > Hi Mathieu > > > > After some more debug I was able to resolve the trace issue I had on > Linux-4.9-rc1 > > If you remember I only got trace for CPU2 out of 4 CPUs which was really > strange > > > > Turns out the issue comes from some quirk in our busses > > Our internal fabric is not able to write 64bit data to registers, only to > memory > > So the address comparators in the ETM got corrupted values and there wasn’t > any match on address for most CPUs. > > For some cryptic reason only CPU2 got somewhat reasonable comparator value > (still not the intended, but a working one) and so it could generate trace > > > > Now I am able to generate proper trace consistently. > Very good. > > > I was wondering how can I add latency or timing information to the trace > > I noticed the cs_etm event can accept an option of “cycacc” and “timestamp“ > > How can I view this information later ? > > Should I use perf script –f ? That information, when configured on the cmd line, will end up in the perf.data file. From there it will be decoded and rendered by the openCSD library. Mike, can you comment on the format of the information that will be found in the packet? Perhaps you have an example somewhere of traces generated by the "cycacc" and "timestamp" option? You will definitely need to create your own scripts as nothing we have done so far uses those configuration parameters. Thanks, Mathieu > > > > Thanks a lot > > > > ------------------- > > Yehuda Yitschak > > Marvell Semiconductor Ltd. > >

8 years, 11 months

[PATCH v3 0/3] arm64: dts: juno: CoreSight support updates

by Sudeep Holla

Hi Mike, I just did some refactoring to reduced thge churn and duplication. Can you check if this work for you ? I could not give it much testing. Regards, Sudeep --->8 Juno r1/r2 boards have different CoreSight infrastructure outside the CPU clusters. This patchset adds the additional coreSight components to separate .dtsi files to support these differences. v1->v2: - moved the addition of the STM component into a separate patch v2->v3: - moved the back the common coreSight components back into juno-base.dtsi Mike Leach (2): arm64: dts: juno: fix CoreSight support for Juno r1/r2 variants arm64: dts: juno: add missing CoreSight STM component Sudeep Holla (1): arm64: dts: juno: refactor CoreSight support on Juno r0 arch/arm64/boot/dts/arm/juno-base.dtsi | 31 ++++++--- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 102 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 13 ++++ arch/arm64/boot/dts/arm/juno-r2.dts | 13 ++++ arch/arm64/boot/dts/arm/juno.dts | 24 +++++++ 5 files changed, 175 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi -- 2.7.4

9 years

Re: [PATCH v4 4/4] arm64: dts: juno: add missing CoreSight STM component

by Suzuki K Poulose

On 17/01/17 12:15, Sudeep Holla wrote: > From: Mike Leach <mike.leach(a)linaro.org> > > This patch adds the missing CoreSight STM component definition to the > device tree of all the juno variants(r0,r1,r2) > > STM component is connected to different funnels depending on Juno > platform variant. > > Reviewed-and-Tested-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Signed-off-by: Mike Leach <mike.leach(a)linaro.org> > [sudeep.holla(a)arm.com: minor changelog update and reorganising the STM > node back into juno-base.dtsi to avoid duplication] > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> > --- > arch/arm64/boot/dts/arm/juno-base.dtsi | 15 +++++++++++++++ > arch/arm64/boot/dts/arm/juno-r1.dts | 4 ++++ > arch/arm64/boot/dts/arm/juno-r2.dts | 4 ++++ > arch/arm64/boot/dts/arm/juno.dts | 16 ++++++++++++++++ > 4 files changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi > index faedf357db3b..58c1773c3aa4 100644 > --- a/arch/arm64/boot/dts/arm/juno-base.dtsi > +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi > @@ -185,6 +185,21 @@ > }; > }; > > + stm@20100000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x20100000 0 0x1000>, > + <0 0x28000000 0 0x180000>; The size of the stimulus base is 16MB (as per TRM), implies => 0x1000000. with that fixed : Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

9 years

Re: [PATCH v4 3/4] arm64: dts: juno: add CoreSight support for Juno r1/r2 variants

by Suzuki K Poulose

On 17/01/17 12:15, Sudeep Holla wrote: > From: Mike Leach <mike.leach(a)linaro.org> > > The CoreSight support added for Juno is valid for only Juno r0. > The Juno r1 and r2 variants have additional components and alternative > connection routes between trace source and sinks. > > This patch builds on top of the existing r0 support and extends it to > Juno r1/r2 variants. > > Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Signed-off-by: Mike Leach <mike.leach(a)linaro.org> > [sudeep.holla(a)arm.com: minor changelog update and major reorganisation of > the common coresight components back into juno-base.dtsi to avoid > duplication, also renamed funnel node names] > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> > --- > arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 100 ++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/arm/juno-r1.dts | 9 +++ > arch/arm64/boot/dts/arm/juno-r2.dts | 9 +++ > 3 files changed, 118 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > > diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > new file mode 100644 > index 000000000000..563463ed28c7 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > @@ -0,0 +1,100 @@ > +/ { > + funnel@20130000 { /* cssys2 */ Typo, that should be csys1. Rest looks good to me. Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

9 years

[PATCH] makefile: Support to cross compile for arm/arm64

by Chunyan Zhang

In order to support cross compile the OpenCSD for arm/arm64, this patch added two environment variables, 'CROSS_COMPILE' and 'ARCH' which can be set by users before compiling the code. Like documented in Kernel Makefile, CROSS_COMPILE specifies the prefix used for all executables used during compilation. CROSS_COMPILE can be set on the command line, as is ARCH. For example, if you want to build the libraryies for Aarch64, you can set "ARCH=arm64", the the compiled libs will be located at lib/linux-arm64/<rel\dbg>.` Signed-off-by: Chunyan Zhang <zhang.chunyan(a)linaro.org> --- decoder/build/linux/makefile | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/decoder/build/linux/makefile b/decoder/build/linux/makefile index 3b6a623..dc1f32b 100644 --- a/decoder/build/linux/makefile +++ b/decoder/build/linux/makefile @@ -47,7 +47,11 @@ export LIB_CAPI_NAME # determine base architecture, heavily borrowed from the Linux kernel v4.4's # tools/perf/config/Makefile.arch +# For example, to compile for arm64 on a X86 PC, you can issue the command: +# "export ARCH=arm64" +ifndef ARCH ARCH := $(shell uname -m 2>/dev/null || echo not) +endif # source root directories export OCSD_LIB_ROOT=$(OCSD_ROOT)/lib @@ -58,10 +62,10 @@ export OCSD_SOURCE=$(OCSD_ROOT)/source export OCSD_TESTS=$(OCSD_ROOT)/tests # tools -export MASTER_CC=gcc -export MASTER_CPP=g++ -export MASTER_LINKER=g++ -export MASTER_LIB=ar +export MASTER_CC=$(CROSS_COMPILE)gcc +export MASTER_CPP=$(CROSS_COMPILE)g++ +export MASTER_LINKER=$(CROSS_COMPILE)g++ +export MASTER_LIB=$(CROSS_COMPILE)ar # compile flags MASTER_CC_FLAGS := -c -Wall -DLINUX @@ -87,6 +91,10 @@ ifeq ($(ARCH),x86) else ifeq ($(ARCH),x86_64) MFLAG:="-m64" BIT_VARIANT=64 +else ifeq ($(ARCH),arm) + BIT_VARIANT=-arm +else ifeq ($(ARCH),arm64) + BIT_VARIANT=-arm64 endif MASTER_CC_FLAGS += $(MFLAG) -- 2.7.4

9 years

[PATCH v2 0/2] arm64: dts: juno: Updates for juno r1/r2 boards

by Mike Leach

Juno r1/r2 boards have different CoreSight infrastructure outside the clusters. This patchset moves the none cluster CoreSight to separate .dtsi files to allow for these differences. v2 moves the Addition of the STM component into a separate patch. Mike Leach (2): arm64: dts: juno: Fix CoreSight support for Juno r1/r2 variants arm64: dts: juno: Adds missing CoreSight STM component. arch/arm64/boot/dts/arm/juno-base.dtsi | 135 --------------- arch/arm64/boot/dts/arm/juno-cs-r0.dtsi | 166 +++++++++++++++++++ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 266 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 1 + arch/arm64/boot/dts/arm/juno-r2.dts | 1 + arch/arm64/boot/dts/arm/juno.dts | 1 + 6 files changed, 435 insertions(+), 135 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r0.dtsi create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi -- 2.7.4

9 years

[PATCH] arm64: dts: juno: Fix CoreSight support for Juno r1/r2 variants

by Mike Leach

The CoreSight support added for Juno is valid for only Juno r0. The Juno r1 and r2 variants have additional components and alternative connection routes between trace source and sinks. The CoreSight infrastructure external to the Cortex-Axx clusters, has been split into separate .dtsi include files for r0 and r1/r2 to correctly represent these variations. Adds missing DT entry for the CoreSight STM component in the infrastructure .dtsi files. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 135 --------------- arch/arm64/boot/dts/arm/juno-cs-r0.dtsi | 166 +++++++++++++++++++ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 266 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 1 + arch/arm64/boot/dts/arm/juno-r2.dts | 1 + arch/arm64/boot/dts/arm/juno.dts | 1 + 6 files changed, 435 insertions(+), 135 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r0.dtsi create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 7d83224..7c89000 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -83,104 +83,6 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input port */ - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&main_funnel_out_port>; - }; - }; - - /* output port */ - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - - main-funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_out_port: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - - port@1 { - reg = <0>; - main_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&cluster0_funnel_out_port>; - }; - }; - - port@2 { - reg = <1>; - main_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&cluster1_funnel_out_port>; - }; - }; - - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - iommus = <&smmu_etr 0>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - etm0: etm@22040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x22040000 0 0x1000>; @@ -351,43 +253,6 @@ }; }; - coresight-replicator { - /* - * Non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi new file mode 100644 index 0000000..4e01b0e --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi @@ -0,0 +1,166 @@ + /* + * Juno trace infrastructure. + * Trace links and sinks and interconnections + * from clusters. + * Connections for Juno r0. + */ + etf@20010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&main_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + main-funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + main_funnel_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + main_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@2 { + reg = <1>; + main_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + + port@3 { + reg = <2>; + main_funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&stm_out_port>; + }; + }; + + + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + coresight-replicator { + /* + * Non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi new file mode 100644 index 0000000..6fe8b62 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -0,0 +1,266 @@ + /* + * Juno trace infrastructure. + * Trace links and sinks and interconnections + * from clusters. + * Connections for Juno r1 and r2. + */ + etf0@20010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf0_in_port: endpoint { + slave-mode; + remote-endpoint = <&main_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf0_out_port: endpoint { + remote-endpoint = <&csys2_funnel_in_port0>; + }; + }; + }; + }; + + etf1@20140000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf1_in_port: endpoint { + slave-mode; + remote-endpoint = + <&csys1_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf1_out_port: endpoint { + remote-endpoint = + <&csys2_funnel_in_port1>; + }; + }; + }; + }; + + csys1_funnel@20130000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20130000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + csys1_funnel_out_port: endpoint { + remote-endpoint = + <&etf1_in_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + csys1_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_port>; + }; + }; + + }; + }; + + csys2_funnel@20150000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20150000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + csys2_funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + csys2_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf0_out_port>; + }; + }; + + port@2 { + reg = <1>; + csys2_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etf1_out_port>; + }; + }; + + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + /* + * This is labelled cssys0 funnel in the Juno r1/r2 TRM + * Retain the name from r0 to maintain compatibility with common + * juno-base.dtsi + */ + main-funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + main_funnel_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + main_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@2 { + reg = <1>; + main_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + coresight-replicator { + /* + * Non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&csys2_funnel_out_port>; + }; + }; + }; + }; + + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + stm_out_port: endpoint { + remote-endpoint = <&csys1_funnel_in_port0>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index eec37fe..8813395 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r1r2.dtsi" }; &memtimer { diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 28f40ec..fca3a17 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r1r2.dtsi" }; &memtimer { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index ac5ceb7..c90c37b 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r0.dtsi" }; &etm0 { -- 2.7.4

9 years

[PATCH] Add documentation on AutoFDO

by Sebastian Pop

The patch adds documentation to HOWTO.md on how to use CoreSight ETM to perform Feedback Directed Optimization. Sebastian Pop (1): HOWTO: add example of how to extract coverage files for autoFDO HOWTO.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.6.3

9 years

[PATCH v2] coresight: etm4x: Fix enabling of cycle accurate tracing in perf.

by Mike Leach

Using perf record 'cyclacc' option in cs_etm event was not setting up cycle accurate trace correctly. Corrects bit set in TRCCONFIGR to enable cycle accurate trace. Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4db8d6a..c5a65d1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) - config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_CYCACC)) { + config->cfg |= BIT(4); + /* TRM: Must program this for cycacc to work */ + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } if (attr->config & BIT(ETM_OPT_TS)) config->cfg |= ETMv4_MODE_TIMESTAMP; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ba8d3f8..b3b5ea7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -146,6 +146,7 @@ #define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETM_CYC_THRESHOLD_DEFAULT 0x100 #define ETMv4_EVENT_MASK 0xFF #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f -- 2.7.4

9 years

Fwd: [PATCH] coresight: etm4x: Fix enabling of cycle accurate tracing in perf.

by Mike Leach

---------- Forwarded message ---------- From: Mike Leach <mike.leach(a)linaro.org> Date: 2 January 2017 at 22:55 Subject: [PATCH] coresight: etm4x: Fix enabling of cycle accurate tracing in perf. To: mathieu.poirier(a)linaro.org Cc: linux-arm-kernel(a)lists.infradead.org, coresignt(a)lists.linaro.org, Mike Leach <mike.leach(a)linaro.org> Using perf record 'cyclacc' option in cs_etm event was not setting up cycle accurate trace correctly. Corrects bit set in TRCCONFIGR to enable cycle accurate trace. Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4db8d6a..07be032 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) - config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_CYCACC)) { + config->cfg |= BIT(4); + /* TRM: Must program this for cycacc to work */ + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } if (attr->config & BIT(ETM_OPT_TS)) config->cfg |= ETMv4_MODE_TIMESTAMP; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ba8d3f8..8a62c6c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -146,6 +146,7 @@ #define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETM_CYC_THRESHOLD_DEFAULT 256 #define ETMv4_EVENT_MASK 0xFF #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f -- 2.7.4 -- Mike Leach Principal Engineer, ARM Ltd. Blackburn Design Centre. UK

9 years

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight