Please ignore this message. I'm testing the mailing list.
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Hi Team,
When trying to boot-up BeagleBoneBlack Platform using UEFI with below
procedure (instead of U-boot), ran into following issue.
Followed Web link :
https://github.com/tianocore/tianocore.github.io/wiki/BeagleBoardPkg#Beagle…
I had a doubt on the provided git repository in this procedure. Does this
repo supports BeagelBoneBlack Platform?
*Error when Tried in Qemu: *
EhcCreateUsb2Hc: capability length 0
EhcDriverBindingStart: failed to create USB2_HC
ERROR: Did not find Linux kernel.
[1] Linux from SD
-
VenHw(B615F1F5-5088-43CD-809C-A16E52487D00)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/zImage
- Arguments: console=tty0 console=ttyS2,115200n8
root=UUID=a4af765b-c2b5-48f4-9564-7a4e9104c4f6 rootwait ro earlyprintk
- LoaderType: Linux kernel with ATAG support
[2] Shell
[3] Boot Manager
Start: qemu: terminating on signal 2
*Error ; sd Card : **DATA abort Error coming when tried booting thru
sd-card*
Could you please help in debug this issue?
Regards,
Mohan.
Hi,
Is there any way I can bring cpu-1 while cpu-0 is running bootloader ?
Need help with setting up C-environment for cpu-1.
Was able to set up PSCI framework.
Regards,
Atul
For people who does not know me I have been the EDK2 maintainer of the ARM Packages for the last 4 years. I took over the excellent work Andrew Fish and Eugene Cohen started few years before.
This week was my last week at ARM - my last day would be on Friday 17th (UK time). I have been learning a lot thanks to the UEFI community.
Being the ARM maintainer has been a great opportunity. I also had the chance to go to few conferences to discuss and present my work and meet few of you as part of my job.
I have been asked last week what is the new exciting place that makes me leave ARM. The answer is my own future start-up... I love challenges and I think this one is definitely one of the highest one I could find. It is actually quite scary but I am quite excited!
I could potentially have kept my role of EDK2 ARM maintainer with me but I would prefer to give the task to Leif Lindholm who has been a co-maintainer for almost two months. So I could fully focus on my new adventure.
Leif has been seating not far from me in the ARM office. We have also had regular meetings about UEFI. He has been at ARM Ltd longer than me and been involved in different Open Source projects. He has also been working on UEFI for Linaro for few (three?) years now.
I have been trying to publish as much work as I can on the work I have done on UEFI for the last 5 years and half at ARM Ltd in the last two weeks. Unfortunately, I am not sure I will have time to publish everything. But I will do my best to publish the most important bits...
Unfortunately, it is still too early to share more details about my future product, so I created a quick website (and found a neutral name) last week-end to allow people to follow the adventure: http://labapart.com/ (can either be pronounced as "Lab apart" or "Lab à Part").
If you would like to contact me, email me here: olivier.martin.fr(a)gmail.com and/or linkedin me: http://www.linkedin.com/in/olivierm.
Cheers,
Olivier
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Hi,
This is my first query on this list. I apologize for any mistake.
I have some queries on following patch :
https://lists.linaro.org/pipermail/boot-architecture/2013-June/000325.html
I am not able to see this patch in master branch.
Is this patch tested?
Also I want to know the underline firmware volume on which this patch has been tested?
Thanks & regards
Meenakshi Aggarwal
Hi Laszlo,
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Saturday, June 13, 2015 5:59 PM
> To: Sharma Bhupesh-B45370; edk2-devel(a)lists.sourceforge.net;
> olivier.martin(a)arm.com; Leif Lindholm; boot-architecture(a)lists.linaro.org
> Subject: Re: AARCH64: Timer Dxe
>
> On 06/13/15 10:52, Sharma Bhupesh wrote:
> > Hi,
> >
> > Can some ARM expert help me with my queries below.
> >
> > The overall context is that I cannot get the 'ArmPlatformPkg/Bds/Bds.c'
> auto-timeout to trigger.
> >
> > The following snippet of code shows how the timeout is created as a
> event using the CreateEvent and SetTimer APIs.
> >
> > However I cannot the SetTimer API triggering a call to the
> corresponding TimerDriverSetTimerPeriod API inside
> 'ArmPkg/Drivers/TimerDxe/TimerDxe.c'
>
> Do you reach the gBS->SetTimer() call at all? For example, if there was a
> non-volatile variable called Timeout, with value 0xFFFF or 0, that could
> prevent it.
Yes, via debugger tracing I can see that the gBS->SetTimer() call is indeed invoked and
calls DXE Core's respective CoreTimerXXXX() APIs
Regards,
Bhupesh
>
> >
> > if (Timeout != 0xFFFF) {
> > if (Timeout > 0) {
> > // Create the waiting events (keystroke and 1sec timer)
> > gBS->CreateEvent (EVT_TIMER, 0, NULL, NULL, &WaitList[0]);
> > gBS->SetTimer (WaitList[0], TimerPeriodic,
> EFI_SET_TIMER_TO_SECOND);
> > WaitList[1] = gST->ConIn->WaitForKey;
> >
> > // Start the timer
> > WaitIndex = 0;
> > Print(L"The default boot selection will start in ");
> > while ((Timeout > 0) && (WaitIndex == 0)) {
> > Print(L"%3d seconds",Timeout);
> > gBS->WaitForEvent (2, WaitList, &WaitIndex);
> > if (WaitIndex == 0) {
> > Print(L"\b\b\b\b\b\b\b\b\b\b\b");
> > Timeout--;
> > }
> > }
> >
> > So, I just wanted to understand if the auto-timeout during boot works
> > on Juno-Rev1 and if yes, how does it connect to the underlying
> > ArmArchTimerLib
> >
> > Please help.
> >
> >> -----Original Message-----
> >> From: Sharma Bhupesh-B45370
> >> Sent: Wednesday, June 10, 2015 4:01 PM
> >> To: edk2-devel(a)lists.sourceforge.net; 'olivier.martin(a)arm.com'
> >> Subject: AARCH64: Timer Dxe
> >>
> >> Hi Olivier,
> >>
> >> 1. I am looking at the 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' DXE
> >> driver and seeing how the timer interrupts are registered:
> >>
> >> // Install secure and Non-secure interrupt handlers
> >> // Note: Because it is not possible to determine the security state
> >> of the
> >> // CPU dynamically, we just install interrupt handler for both sec
> >> and non-sec
> >> // timer PPI
> >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> >> (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler);
> >> ASSERT_EFI_ERROR (Status);
> >>
> >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> >> (PcdArmArchTimerHypIntrNum), TimerInterruptHandler);
> >> ASSERT_EFI_ERROR (Status);
> >>
> >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> >> (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
> >> ASSERT_EFI_ERROR (Status);
> >>
> >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> >> (PcdArmArchTimerIntrNum), TimerInterruptHandler);
> >> ASSERT_EFI_ERROR (Status);
> >>
> >> I wanted to understand how the Interrupt registration changes for PPI
> >> or SPI interrupt sources.
> >> As usually the Virtual, Hypervisor, Physical and Physical Non-Secure
> >> interrupts are PPI does the PPI number need to be defined as the PCD
> >> values in the same way as linux. The Linux gicv3 documentation says
> >> (Documentation/devicetree/bindings/arm/gic-v3.txt):
> >>
> >> SPI interrupts are in the range [0-987]. PPI interrupts are in the
> >> range [0-15].
> >>
> >> 2. Also one related question is whether on Juno Rev1, you are able to
> >> get the BootDelay to work via timer based events? If yes, can you
> >> please share if you achieve this by using the ARMv8 generic timer or
> >> the SP804 timer.
> >>
> >
> > Regards,
> > Bhupesh
> >
Hi,
Can some ARM expert help me with my queries below.
The overall context is that I cannot get the 'ArmPlatformPkg/Bds/Bds.c' auto-timeout to trigger.
The following snippet of code shows how the timeout is created as a event using the CreateEvent and SetTimer APIs.
However I cannot the SetTimer API triggering a call to the corresponding TimerDriverSetTimerPeriod API inside 'ArmPkg/Drivers/TimerDxe/TimerDxe.c'
if (Timeout != 0xFFFF) {
if (Timeout > 0) {
// Create the waiting events (keystroke and 1sec timer)
gBS->CreateEvent (EVT_TIMER, 0, NULL, NULL, &WaitList[0]);
gBS->SetTimer (WaitList[0], TimerPeriodic, EFI_SET_TIMER_TO_SECOND);
WaitList[1] = gST->ConIn->WaitForKey;
// Start the timer
WaitIndex = 0;
Print(L"The default boot selection will start in ");
while ((Timeout > 0) && (WaitIndex == 0)) {
Print(L"%3d seconds",Timeout);
gBS->WaitForEvent (2, WaitList, &WaitIndex);
if (WaitIndex == 0) {
Print(L"\b\b\b\b\b\b\b\b\b\b\b");
Timeout--;
}
}
So, I just wanted to understand if the auto-timeout during boot works on Juno-Rev1 and if yes, how does it connect to the underlying ArmArchTimerLib
Please help.
> -----Original Message-----
> From: Sharma Bhupesh-B45370
> Sent: Wednesday, June 10, 2015 4:01 PM
> To: edk2-devel(a)lists.sourceforge.net; 'olivier.martin(a)arm.com'
> Subject: AARCH64: Timer Dxe
>
> Hi Olivier,
>
> 1. I am looking at the 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' DXE driver
> and seeing how the timer interrupts are registered:
>
> // Install secure and Non-secure interrupt handlers
> // Note: Because it is not possible to determine the security state of
> the
> // CPU dynamically, we just install interrupt handler for both sec and
> non-sec
> // timer PPI
> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler);
> ASSERT_EFI_ERROR (Status);
>
> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> (PcdArmArchTimerHypIntrNum), TimerInterruptHandler);
> ASSERT_EFI_ERROR (Status);
>
> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
> ASSERT_EFI_ERROR (Status);
>
> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32
> (PcdArmArchTimerIntrNum), TimerInterruptHandler);
> ASSERT_EFI_ERROR (Status);
>
> I wanted to understand how the Interrupt registration changes for PPI or
> SPI interrupt sources.
> As usually the Virtual, Hypervisor, Physical and Physical Non-Secure
> interrupts are PPI does the PPI number need to be defined as the PCD
> values in the same way as linux. The Linux gicv3 documentation says
> (Documentation/devicetree/bindings/arm/gic-v3.txt):
>
> SPI interrupts are in the range [0-987]. PPI interrupts are in the range
> [0-15].
>
> 2. Also one related question is whether on Juno Rev1, you are able to get
> the BootDelay to work via timer based events? If yes, can you please
> share if you achieve this by using the ARMv8 generic timer or the SP804
> timer.
>
Regards,
Bhupesh
Hello i am trying to boot linaro(12.11) filesystem over nfs on my soc;
Configured the tftp/dhcp/nfs-export/ + recompiled the kernel with nfs_root
and practically have the system working with other root fileSystem;
Have some problem to boot on linaro fs over nfs; any help will be
appreciated;
Current error i got is after kernel booting and succeeded to mount the fs:
....
VFS: Mounted root (nfs filesystem) on device 0:11.
Freeing unsued kernel memory...
init: ureadahead main process (596) terminated with status 5
then it hang forever...pls advice...
thnks vlad
Hi,
The current AARCH64 UEFI is designed to run entirely in EL2 with the assumption that the ARM Trusted FW (ATF) running in EL3 and launching
UEFI in EL2.
As a result if we try to use the UEFI bootloader as a bare-metal debug tool (w/o the ATF, BootROM and so on..), we get an assertion failure in
ArmConfigureMmu call (PEI phase).
"UEFI should not run in EL3".
However when I look at 'ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S', I see some function implementations support UEFI running in EL3...
ASM_PFX(ArmSetTTBR0):
EL1_OR_EL2_OR_EL3(x1)
1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
b 4f
2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
b 4f
3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
4:isb
ret
...But others in the same file, don't seem to support UEFI running in EL3:
ASM_PFX(ArmGetTTBR0BaseAddress):
EL1_OR_EL2(x1)
1:mrs x0, ttbr0_el1
b 3f
2:mrs x0, ttbr0_el2
3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
and x0, x0, x1
isb
ret
Does UEFI provide some placeholders to make vendor specific changes in the SEC or PEI phase to enable execution in EL3 mode?
Last I gathered from the discussions on the UEFI mailing lists, it seems that the some changes in PEI specs is required to accommodate ARM
Trusted Firmware (ATF) and UEFI running in EL2. Where can I get more information on the same
Regards,
Bhupesh
