boot-architecture

boot-architecture@lists.linaro.org

7 participants
651 discussions

[PSCI] CPU 1 bring up while CPU 0 loading bootloader

by Atul Raut

Hi, Is there any way I can bring cpu-1 while cpu-0 is running bootloader ? Need help with setting up C-environment for cpu-1. Was able to set up PSCI framework. Regards, Atul

9 years, 10 months

Farewell - last days at ARM Ltd

by Olivier Martin

For people who does not know me I have been the EDK2 maintainer of the ARM Packages for the last 4 years. I took over the excellent work Andrew Fish and Eugene Cohen started few years before. This week was my last week at ARM - my last day would be on Friday 17th (UK time). I have been learning a lot thanks to the UEFI community. Being the ARM maintainer has been a great opportunity. I also had the chance to go to few conferences to discuss and present my work and meet few of you as part of my job. I have been asked last week what is the new exciting place that makes me leave ARM. The answer is my own future start-up... I love challenges and I think this one is definitely one of the highest one I could find. It is actually quite scary but I am quite excited! I could potentially have kept my role of EDK2 ARM maintainer with me but I would prefer to give the task to Leif Lindholm who has been a co-maintainer for almost two months. So I could fully focus on my new adventure. Leif has been seating not far from me in the ARM office. We have also had regular meetings about UEFI. He has been at ARM Ltd longer than me and been involved in different Open Source projects. He has also been working on UEFI for Linaro for few (three?) years now. I have been trying to publish as much work as I can on the work I have done on UEFI for the last 5 years and half at ARM Ltd in the last two weeks. Unfortunately, I am not sure I will have time to publish everything. But I will do my best to publish the most important bits... Unfortunately, it is still too early to share more details about my future product, so I created a quick website (and found a neutral name) last week-end to allow people to follow the adventure: http://labapart.com/ (can either be pronounced as "Lab apart" or "Lab à Part"). If you would like to contact me, email me here: olivier.martin.fr(a)gmail.com and/or linkedin me: http://www.linkedin.com/in/olivierm. Cheers, Olivier -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

10 years, 2 months

Ext2/Ext3 filesystem support

by Meenakshi Aggarwal

Hi, This is my first query on this list. I apologize for any mistake. I have some queries on following patch : https://lists.linaro.org/pipermail/boot-architecture/2013-June/000325.html I am not able to see this patch in master branch. Is this patch tested? Also I want to know the underline firmware volume on which this patch has been tested? Thanks & regards Meenakshi Aggarwal

10 years, 2 months

RE: AARCH64: Timer Dxe

by Sharma Bhupesh

Hi Laszlo, > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Saturday, June 13, 2015 5:59 PM > To: Sharma Bhupesh-B45370; edk2-devel(a)lists.sourceforge.net; > olivier.martin(a)arm.com; Leif Lindholm; boot-architecture(a)lists.linaro.org > Subject: Re: AARCH64: Timer Dxe > > On 06/13/15 10:52, Sharma Bhupesh wrote: > > Hi, > > > > Can some ARM expert help me with my queries below. > > > > The overall context is that I cannot get the 'ArmPlatformPkg/Bds/Bds.c' > auto-timeout to trigger. > > > > The following snippet of code shows how the timeout is created as a > event using the CreateEvent and SetTimer APIs. > > > > However I cannot the SetTimer API triggering a call to the > corresponding TimerDriverSetTimerPeriod API inside > 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' > > Do you reach the gBS->SetTimer() call at all? For example, if there was a > non-volatile variable called Timeout, with value 0xFFFF or 0, that could > prevent it. Yes, via debugger tracing I can see that the gBS->SetTimer() call is indeed invoked and calls DXE Core's respective CoreTimerXXXX() APIs Regards, Bhupesh > > > > > if (Timeout != 0xFFFF) { > > if (Timeout > 0) { > > // Create the waiting events (keystroke and 1sec timer) > > gBS->CreateEvent (EVT_TIMER, 0, NULL, NULL, &WaitList[0]); > > gBS->SetTimer (WaitList[0], TimerPeriodic, > EFI_SET_TIMER_TO_SECOND); > > WaitList[1] = gST->ConIn->WaitForKey; > > > > // Start the timer > > WaitIndex = 0; > > Print(L"The default boot selection will start in "); > > while ((Timeout > 0) && (WaitIndex == 0)) { > > Print(L"%3d seconds",Timeout); > > gBS->WaitForEvent (2, WaitList, &WaitIndex); > > if (WaitIndex == 0) { > > Print(L"\b\b\b\b\b\b\b\b\b\b\b"); > > Timeout--; > > } > > } > > > > So, I just wanted to understand if the auto-timeout during boot works > > on Juno-Rev1 and if yes, how does it connect to the underlying > > ArmArchTimerLib > > > > Please help. > > > >> -----Original Message----- > >> From: Sharma Bhupesh-B45370 > >> Sent: Wednesday, June 10, 2015 4:01 PM > >> To: edk2-devel(a)lists.sourceforge.net; 'olivier.martin(a)arm.com' > >> Subject: AARCH64: Timer Dxe > >> > >> Hi Olivier, > >> > >> 1. I am looking at the 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' DXE > >> driver and seeing how the timer interrupts are registered: > >> > >> // Install secure and Non-secure interrupt handlers > >> // Note: Because it is not possible to determine the security state > >> of the > >> // CPU dynamically, we just install interrupt handler for both sec > >> and non-sec > >> // timer PPI > >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > >> (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler); > >> ASSERT_EFI_ERROR (Status); > >> > >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > >> (PcdArmArchTimerHypIntrNum), TimerInterruptHandler); > >> ASSERT_EFI_ERROR (Status); > >> > >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > >> (PcdArmArchTimerSecIntrNum), TimerInterruptHandler); > >> ASSERT_EFI_ERROR (Status); > >> > >> Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > >> (PcdArmArchTimerIntrNum), TimerInterruptHandler); > >> ASSERT_EFI_ERROR (Status); > >> > >> I wanted to understand how the Interrupt registration changes for PPI > >> or SPI interrupt sources. > >> As usually the Virtual, Hypervisor, Physical and Physical Non-Secure > >> interrupts are PPI does the PPI number need to be defined as the PCD > >> values in the same way as linux. The Linux gicv3 documentation says > >> (Documentation/devicetree/bindings/arm/gic-v3.txt): > >> > >> SPI interrupts are in the range [0-987]. PPI interrupts are in the > >> range [0-15]. > >> > >> 2. Also one related question is whether on Juno Rev1, you are able to > >> get the BootDelay to work via timer based events? If yes, can you > >> please share if you achieve this by using the ARMv8 generic timer or > >> the SP804 timer. > >> > > > > Regards, > > Bhupesh > >

10 years, 3 months

RE: AARCH64: Timer Dxe

by Sharma Bhupesh

Hi, Can some ARM expert help me with my queries below. The overall context is that I cannot get the 'ArmPlatformPkg/Bds/Bds.c' auto-timeout to trigger. The following snippet of code shows how the timeout is created as a event using the CreateEvent and SetTimer APIs. However I cannot the SetTimer API triggering a call to the corresponding TimerDriverSetTimerPeriod API inside 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' if (Timeout != 0xFFFF) { if (Timeout > 0) { // Create the waiting events (keystroke and 1sec timer) gBS->CreateEvent (EVT_TIMER, 0, NULL, NULL, &WaitList[0]); gBS->SetTimer (WaitList[0], TimerPeriodic, EFI_SET_TIMER_TO_SECOND); WaitList[1] = gST->ConIn->WaitForKey; // Start the timer WaitIndex = 0; Print(L"The default boot selection will start in "); while ((Timeout > 0) && (WaitIndex == 0)) { Print(L"%3d seconds",Timeout); gBS->WaitForEvent (2, WaitList, &WaitIndex); if (WaitIndex == 0) { Print(L"\b\b\b\b\b\b\b\b\b\b\b"); Timeout--; } } So, I just wanted to understand if the auto-timeout during boot works on Juno-Rev1 and if yes, how does it connect to the underlying ArmArchTimerLib Please help. > -----Original Message----- > From: Sharma Bhupesh-B45370 > Sent: Wednesday, June 10, 2015 4:01 PM > To: edk2-devel(a)lists.sourceforge.net; 'olivier.martin(a)arm.com' > Subject: AARCH64: Timer Dxe > > Hi Olivier, > > 1. I am looking at the 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' DXE driver > and seeing how the timer interrupts are registered: > > // Install secure and Non-secure interrupt handlers > // Note: Because it is not possible to determine the security state of > the > // CPU dynamically, we just install interrupt handler for both sec and > non-sec > // timer PPI > Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler); > ASSERT_EFI_ERROR (Status); > > Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > (PcdArmArchTimerHypIntrNum), TimerInterruptHandler); > ASSERT_EFI_ERROR (Status); > > Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > (PcdArmArchTimerSecIntrNum), TimerInterruptHandler); > ASSERT_EFI_ERROR (Status); > > Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 > (PcdArmArchTimerIntrNum), TimerInterruptHandler); > ASSERT_EFI_ERROR (Status); > > I wanted to understand how the Interrupt registration changes for PPI or > SPI interrupt sources. > As usually the Virtual, Hypervisor, Physical and Physical Non-Secure > interrupts are PPI does the PPI number need to be defined as the PCD > values in the same way as linux. The Linux gicv3 documentation says > (Documentation/devicetree/bindings/arm/gic-v3.txt): > > SPI interrupts are in the range [0-987]. PPI interrupts are in the range > [0-15]. > > 2. Also one related question is whether on Juno Rev1, you are able to get > the BootDelay to work via timer based events? If yes, can you please > share if you achieve this by using the ARMv8 generic timer or the SP804 > timer. > Regards, Bhupesh

10 years, 3 months

boot over nfs;

by vladi solov

Hello i am trying to boot linaro(12.11) filesystem over nfs on my soc; Configured the tftp/dhcp/nfs-export/ + recompiled the kernel with nfs_root and practically have the system working with other root fileSystem; Have some problem to boot on linaro fs over nfs; any help will be appreciated; Current error i got is after kernel booting and succeeded to mount the fs: .... VFS: Mounted root (nfs filesystem) on device 0:11. Freeing unsued kernel memory... init: ureadahead main process (596) terminated with status 5 then it hang forever...pls advice... thnks vlad

10 years, 7 months

AARCH64 UEFI and EL3

by bhupesh.sharma＠freescale.com

Hi, The current AARCH64 UEFI is designed to run entirely in EL2 with the assumption that the ARM Trusted FW (ATF) running in EL3 and launching UEFI in EL2. As a result if we try to use the UEFI bootloader as a bare-metal debug tool (w/o the ATF, BootROM and so on..), we get an assertion failure in ArmConfigureMmu call (PEI phase). "UEFI should not run in EL3". However when I look at 'ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S', I see some function implementations support UEFI running in EL3... ASM_PFX(ArmSetTTBR0): EL1_OR_EL2_OR_EL3(x1) 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0) b 4f 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0) b 4f 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0) 4:isb ret ...But others in the same file, don't seem to support UEFI running in EL3: ASM_PFX(ArmGetTTBR0BaseAddress): EL1_OR_EL2(x1) 1:mrs x0, ttbr0_el1 b 3f 2:mrs x0, ttbr0_el2 3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */ and x0, x0, x1 isb ret Does UEFI provide some placeholders to make vendor specific changes in the SEC or PEI phase to enable execution in EL3 mode? Last I gathered from the discussions on the UEFI mailing lists, it seems that the some changes in PEI specs is required to accommodate ARM Trusted Firmware (ATF) and UEFI running in EL2. Where can I get more information on the same Regards, Bhupesh

11 years, 1 month

[HOWTO] Implement / Validate / Debug / Tune UEFI Runtime drivers

by Olivier Martin

I have just finished to write a wikipage to help people to implement and debug UEFI Runtime drivers based on the Tianocore project (Open Source implementation of the UEFI spec). To validate the UEFI Runtime drivers, I have been using the Linux kernel with EFI Stub support (https://wiki.linaro.org/LEG/Engineering/Kernel/UEFI/EFIstub): Linux kernel available here: https://git.linaro.org/people/leif.lindholm/linux.git/shortlog/refs/heads/ue fi-for-next The wikipage: https://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPkg/Runt ime

11 years, 4 months

Tianocore now supports Android FastBoot

by Olivier Martin

Dear all, Android FastBoot support has been added to Tianocore into SVN 15317 (2014-03-05). Android Fastboot is a protocol to update the flash and/or boot filesystem on Android devices from a host over USB. The fastboot utility is part of the Android SDK. This support is architecture independent. An abstraction layer has been added to allow devices that do not have USB client support to use another transport mechanism (eg: TCP). We actually have support internally for this TCP transport layer we are planning to send upstream soon (after the internal review has been completed). These patches are available on request. The support has been validated on ARM Versatile Express using USB (and ethernet). A tutorial is available here: http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=EmbeddedPkg/ AndroidFastBoot Regards, Olivier

11 years, 6 months

Re: [edk2] ARM UEFI BIOS & Trusted firmware (SMM / Trustzone similitudes)

by Andrew fish

Eugene and I usually attend, and it is Andrew Sloss running it on the ARM side. Sent from my iPhone > On Dec 6, 2013, at 2:14 PM, "Pant, Alok" <Alok.Pant(a)amd.com> wrote: > > >>. But as suggested Eugene, a discussion can be started in the UEFI Forum working groups. ABST (ARM Binding Sub-Team) might be a good place to get the initial feedbacks. > Hi Olivier, > Thanks. Would you be able to bring this to ABST? Or what do you suggest the next steps? > > From: Olivier Martin [mailto:olivier.martin@arm.com] > Sent: Friday, December 06, 2013 2:05 PM > To: Pant, Alok; Cohen, Eugene; 'Tim Lewis'; edk2-devel(a)lists.sourceforge.net > Cc: boot-architecture(a)lists.linaro.org > Subject: RE: ARM UEFI BIOS & Trusted firmware (SMM / Trustzone similitudes) > > I have not necessary got the background and the full picture of the industry in term of production firmware compare to some of you. But I have tried to give some answers to your questions. > > # Alok, two directions for Secure Monitor implementation? > The ARM recommendation is everything concerning secure world (EL3, Secure-EL1, Secure-EL0) should be implemented as part of the Trusted Firmware project. > ArmPlatformPkg/Sec has been ported to AArch64 as a temporary solution while waiting for an appropriate Trusted Firmware implementation. There is no plan to have a Secure Monitor implementation (BL31) in Tianocore project. > And I will not accept any patch that implements such feature in Tianocore. The reason is I do not think it is good thing to duplicate code between both projects supported by ARM. And the Trusted Firmware project is a better place for such features. > > # Alok, some implementation starts the Trusted Firmware (in EL3) that launches SEC in El1/2 mode > ArmPlatformPkg/Sec should not run in EL2/EL1. As I said earlier, this is only a temporary solution that should be replaced by the Trusted Firmware project on most ARMv8 platforms. > The Trusted Firmware should launch UEFI that starts with either ArmPlatformPkg/PrePeiCore (if the UEFI firmware in XIP ROM) or ArmPlatformPkg/PrePi (if the UEFI firmware is started from DRAM). > > # Alok, Should secure monitor (bl31) be launched before or during SEC phase? > Secure Monitor (BL31) is one of the first components loaded by the Trusted Firmware. The Secure Monitor will be available before the UEFI firmware starts. > > # Alok/Eugene, Extending the PI SMM specification (Volume 4) for Trustzone > I had a look at the SMM PI spec. I can see a lot of similitude to the UEFI spec (an architecture and implementation agnostic interface). > I can also see some similitude between SMM and Trustzone technology (based on the ARM Secure Extension). And I am sure some SMM drivers will be ported to ARM Secure components (eg: authentification variable for secure boot). > > One notable difference between SMM and ‘Trustzone’ is the initialization. SMM seems to be initialized during the DXE phase while the ARM Secure/Trusted environment is initialized prior to start the Non Secure/Non Trusted environment (including UEFI, u-boot bootloaders). And I do not see this initialization phase to be changed for the reason that the secure environment (Trusted Firmware, Trusted OS, SiP/ODM/OEM secure components) will setup the appropriate hardware privileges and initialize their environment prior to switch to the Non-Secure environment. > > The concept of ‘extending the PI SMM spec to Trustzone’ or 'some form of SMM foundation glue code' is interesting. But it might be difficult to implement in the current situation (most of the solutions seem to be highly integrated without much interoperability). The level of standardization of the Secure/Trusted environment has not reached the API yet. > Obviously, to create a standard an initiative has to be started. I am probably not the best person (due to my limited knowledge of SMM and their real use cases) to start this initiative. But as suggested Eugene, a discussion can be started in the UEFI Forum working groups. ABST (ARM Binding Sub-Team) might be a good place to get the initial feedbacks. > > # Tim, What happens when the secure OS is performing a secure task, but the other OS asks for a shutdown? > As you know PSCI (Power State Coordination Interface) is recommended by ARM for OS Power Management (OSPM). In this case, the Secure world is aware of the shutdown. > But the PSCI spec says 'a Trusted OS must not rely on the use of any notification, and must be resistant to any sudden loss of context'. > Trusted OS vendors are expected to provide a Rich OS driver to invoke their services. There are probably ways to signal a Rich OS shutdown to the Trusted OS using this driver. > > Thanks, > Olivier > > > From: Pant, Alok [mailto:Alok.Pant@amd.com] > Sent: 05 December 2013 18:08 > To: edk2-devel(a)lists.sourceforge.net; Olivier Martin > Subject: RE: ARM UEFI BIOS & Trusted firmware > > Hi Tim & Eugene, > Thanks for the response. I agree current SMM foundation code gas some IA specific and there are various gotchas around SMM entry/exit (sync core , save restore etc, base protocol), however most of SMM foundation is generic and it provides a nice framework of independent driver and interaction via protocol and use common services; granted the DXE SMMipl role of launching and building initial SMM environment does not mesh well on ARM. In parallel there is separate work on ARM trusted firmware and seems there is no common ground between two. I am very must interested to hear how others are attempting to address such feature porting issue and the direction from industry toward runtime EL3 support (single monolithic TF binary+some proprietary form of RTOS “vs.” attempt to integrate UEFI SMM with trusted fw core). I am sure I am not the first one stumbling on this question and seeking how others attempted to solve the above and if this a broader issue that need to be further discussed in this forum. > > Thanks > -Alok > > > > From: Tim Lewis [mailto:tim.lewis@insyde.com] > Sent: Thursday, December 05, 2013 11:39 AM > To: edk2-devel(a)lists.sourceforge.net; olivier.martin(a)arm.com > Subject: Re: [edk2] ARM UEFI BIOS & Trusted firmware > > Eugene – > > One of the issues for the SMM specification and TZ is the single-threaded nature. While most of ARM’s TrustZone infrastructure can be mapped easily to SMM, the possibility of having cores in TZ and out of TZ simultaneously, or more than one core in TZ at the same time raises some interesting issues (resource contention, etc.) > > Tim > > From: Cohen, Eugene [mailto:eugene@hp.com] > Sent: Thursday, December 05, 2013 9:29 AM > To: edk2-devel(a)lists.sourceforge.net; olivier.martin(a)arm.com > Subject: Re: [edk2] ARM UEFI BIOS & Trusted firmware > > Alok, > > I agree -- there is value in the modular nature of the PI component approach extending to the ARM trusted firmware environment. > > For SMM this is supported in the PI spec’s SMM core interface specification and in edk2 by the PiSmmCore module and accompanying libraries. Unlike DXE and PEI, the SMM core, at least in name, is IA-specific as it refers to SMM, SMIs, SMRAM, etc. When you look past the names though you can see that the functions it is providing is really architecture independent -- IO protocols, secure memory allocation, protocol management, and handler registration. Given the current IA-specific naming, it would be difficult to recommend that ARM should simply adopt the “SMM” core architecture for the TZ/EL3/SecureMonitor implementation. > > Perhaps this should be raised in the PI working group, specifically “is the SMM core interface spec really an IA-specific concept or something that should become architecture agnostic?” > > Eugene > > From: Pant, Alok [mailto:Alok.Pant@amd.com] > Sent: Thursday, December 05, 2013 8:42 AM > To: edk2-devel(a)lists.sourceforge.net; olivier.martin(a)arm.com > Subject: [edk2] ARM UEFI BIOS & Trusted firmware > > Changing topic.. > > Hi Oliver, Thanks. I also I have few separate questions wrt to Trusted firmware & UEFI ARM code and hope you/others can help answer > > · It seems there are two direction for SecureMonitor implementation. In one implementation the SEC code (ArmPlatformPkg\Sec\Sec.c) install the secure monitor ( when SEC start in El3) ; In other implementation the Trusted firmware start first install secure monitor (bl31) and launch SEC in El1/2 mode. My question is what is the preferred direction when both are possible? Should secure monitor (bl31) be launched before or during SEC phase? > · Historically in x86 implementation the SMM mode hosts various runtime platform BIOS driver for feature such as authentication variable (for secure boot), platform runtime handing handling etc. EDKII has a good framework for SMM kernel and loading various independent SMM driver and interaction among those driver via protocol etc. In ARM based UEFI/Trusted firmware implementation what may be preferred way to deal with such need. Should all those UEFI SMM driver be ported to Trusted firmware which "today" is in primitive framework compare to SMM EDKII foundation code, or some form of SMM foundation can gel with trusted firmware design to allow independent platform el3 code be developed at independent driver. Curious how others have attempted to solve this problem and if there can be standard way for all of us to adopt here. Before creating yet another method I was hoping to hear from experts on any common ground for such feature implementation > > Thanks again for all your help and comments > -Alok > > -----Original Message----- > From: Olivier Martin [mailto:olivier.martin@arm.com] > Sent: Wednesday, December 04, 2013 7:40 AM > To: TigerLiu(a)viatech.com.cn; edk2-devel(a)lists.sourceforge.net > Subject: Re: [edk2] SEC code support big.LITTLE tech? > > Hi Tiger, > > The ARM recommendation to manage secondary CPUs (the primary CPU is the CPU that runs UEFI and starts your OS kernel) is to use PSCI (Power State Coordination Interface - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0022b/index.h > tml). > PSCI uses SMCs (Secure Memory Calls) to bring up secondary CPUs (CPU_UP / CPU_DOWN). This code runs in Secure World while UEFI runs in Non-Secure World. > > For the story... I started to implement PSCI support in Tianocore source code (in ArmPlatformPkg/Sec). But the EDK2 framework (PCD/Library/INF/FDF > etc) had made the code quite hard to maintain. > So, I wrote a new secure firmware framework project to handle this support. > This firmware is not Open Source (available in binary format for TC2 only). > A new project has been started by ARM Ltd last month. It is an Open Source implementation of the Trusted/Secure Firmware: > https://github.com/ARM-software/arm-trusted-firmware > Unfortunately at this stage, 32bit is not supported (only AArch64 is supported). And as far as I know there is no plan to add 32bit support by ARM Ltd in the short term. > > The current ArmPlatformPkg/Sec has support to hold the secondary cores in WFI. But it does not support PSCI. The current support might be sufficient enough for you at this stage. > > Thanks, > Olivier > > > -----Original Message----- > > From: TigerLiu(a)viatech.com.cn [mailto:TigerLiu@viatech.com.cn] > > Sent: 04 December 2013 01:51 > > To: edk2-devel(a)lists.sourceforge.net > > Cc: Olivier Martin > > Subject: [edk2] SEC code support big.LITTLE tech? > > > > Hi, Oliver: > > Does current ArmPlatformPackage's sec code support big.LITTLE tech? > > Such as : > > An ARM SOC --- with 4 Cores Cortex-A15, 4 Cores Cortex-A7 > > > > So, if sec code support big.LITTLE tech, how does it let one core as > > boot strap cpu, others go into wfe(or other sleeping state)? > > > > Best wishes, > > > > > > ------------------------------------------------------------------------------ > Sponsored by Intel(R) XDK > Develop, test and display web and hybrid apps with a single code base. > Download it for free now! > http://pubads.g.doubleclick.net/gampad/clk?id=111408631&iu=/4140/ostg.clktrk > _______________________________________________ > edk2-devel mailing list > edk2-devel(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/edk2-devel > > > ------------------------------------------------------------------------------ > Sponsored by Intel(R) XDK > Develop, test and display web and hybrid apps with a single code base. > Download it for free now! > http://pubads.g.doubleclick.net/gampad/clk?id=111408631&iu=/4140/ostg.clktrk > _______________________________________________ > edk2-devel mailing list > edk2-devel(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/edk2-devel

11 years, 9 months

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