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from e3a2fff0402 AArch64: tweak inner-loop penalty when doing outer-loop vec [...] new 1f7bb5c73d5 Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 to 3 new 43ec8ef603f RISC-V: Adjust the asm check of vx_vf due to middle-end change

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Summary of changes: .../gcc.target/riscv/rvv/autovec/sat_add-cost-1.c | 59 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 5 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 5 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 +- gcc/tree-vect-slp.cc | 2 +- 6 files changed, 70 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat_add-cost-1.c