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from d9a375eafa5 [PATCH] testsuite: Check for effective-target ctz [PR123192]. new e8937196b2b vect: Use type precision in reduction epilogue [PR123097]. new 9bf25e44243 optabs: Fix creation of length and bias operands. new 427c695b66e RISC-V: Implement cbranch_all/any. new 2fd0ba5e5ee docs: Use unicode quotation for else value. new e8fd095091e forwprop: Check type conversion in pack/unpack [PR123117]. new 3c2b6906fb4 vect: Fix scale-only pass in vect_gather_scatter_fn_p [PR123118]. new f34869f8cd6 RISC-V: Change gather/scatter iterators. new dd781e4c1cb RISC-V: Rename vector-mode related functions. new f5ddd4ba0ba RISC-V: Add VLS modes to autovec iterators. new 92edf176fff RISC-V: Generic vec_extract via subreg. new 23a2cab0e68 RISC-V: Testsuite fixes. new d4e6fc510f9 RISC-V: Fix overflow check in interleave pattern [PR122970].

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Summary of changes: gcc/config/riscv/autovec-opt.md | 22 +- gcc/config/riscv/autovec.md | 387 +++-- gcc/config/riscv/predicates.md | 7 + gcc/config/riscv/riscv-avlprop.cc | 2 +- gcc/config/riscv/riscv-protos.h | 6 +- gcc/config/riscv/riscv-selftests.cc | 8 +- gcc/config/riscv/riscv-v.cc | 256 +++- gcc/config/riscv/riscv-vector-builtins-bases.cc | 66 +- gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv-vector-costs.cc | 22 +- gcc/config/riscv/riscv.cc | 104 +- gcc/config/riscv/vector-crypto.md | 172 +-- gcc/config/riscv/vector-iterators.md | 1535 +++++++++++++++++++- gcc/config/riscv/vector.md | 186 +-- gcc/doc/md.texi | 2 +- gcc/optabs.cc | 11 +- .../g++.target/riscv/rvv/autovec/pr123118.C | 19 + .../gcc.target/loongarch/vector/lsx/pr123117.c | 16 + .../gcc.target/riscv/rvv/autovec/early-break-3.c | 70 + .../gcc.target/riscv/rvv/autovec/early-break-4.c | 68 + .../rvv/autovec/early-break-5.c} | 25 +- .../rvv/autovec/gather-scatter/strided_store-2.c | 3 +- .../riscv/rvv/autovec/param-autovec-mode.c | 2 +- .../riscv/rvv/autovec/partial/select_vl-2.c | 4 +- .../gcc.target/riscv/rvv/autovec/pr120378-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr121510.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr122970.c | 71 + .../gcc.target/riscv/rvv/autovec/pr123097-run.c | 19 + .../gcc.target/riscv/rvv/autovec/pr123097.c | 20 + .../riscv/rvv/autovec/subreg-extract.c} | 16 +- .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 5 +- .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 5 +- .../gcc.target/riscv/rvv/base/pr112431-21.c | 2 +- gcc/testsuite/lib/target-supports.exp | 18 + gcc/tree-ssa-forwprop.cc | 12 + gcc/tree-vect-data-refs.cc | 10 +- gcc/tree-vect-loop.cc | 12 +- 37 files changed, 2563 insertions(+), 628 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/pr123118.C create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/pr123117.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-4.c copy gcc/testsuite/gcc.target/{aarch64/sve/vect-early-break-cbranch_3.c => riscv/r [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122970.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123097-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123097.c copy gcc/testsuite/{gcc.dg/vect/pr101445.c => gcc.target/riscv/rvv/autovec/subreg- [...]