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from e3a60357520 target/123027 - handle min/max expansion when -ffinite-math-only new 0b129b8b368 RISC-V: Implement mask reduction. new c139a4c9182 RISC-V: Pragma target [PR115325]. new 195471cc076 RISC-V: Add more mode_idx attributes [PR123022]. new 7068b2e1900 RISC-V: -mmax-vectorization. new a82f188449c optabs: Add else operand to LEN_LOAD. new cee0a9dd270 fold: Elide MASK_LEN_LOAD/STORE with zero length [PR122635].

The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/autovec.md | 31 +++ gcc/config/riscv/riscv-c.cc | 44 ++++ gcc/config/riscv/riscv-protos.h | 4 + gcc/config/riscv/riscv-target-attr.cc | 96 ++++++--- gcc/config/riscv/riscv-v.cc | 48 +++++ gcc/config/riscv/riscv.cc | 47 ++++- gcc/config/riscv/riscv.opt | 4 + gcc/config/riscv/vector.md | 8 + gcc/config/rs6000/predicates.md | 5 + gcc/config/rs6000/vsx.md | 7 +- gcc/config/s390/predicates.md | 5 + gcc/config/s390/vector.md | 7 +- gcc/doc/extend.texi | 12 +- gcc/doc/invoke.texi | 6 + gcc/doc/md.texi | 20 +- gcc/gimple-fold.cc | 225 +++++++++++++++------ gcc/internal-fn.cc | 13 +- gcc/optabs-tree.cc | 31 ++- .../gcc.target/aarch64/sve/pfalse-store.c | 5 +- .../gcc.target/powerpc/p9-vec-length-epil-8.c | 2 +- gcc/testsuite/gcc.target/riscv/pragma-target-1.c | 59 ++++++ gcc/testsuite/gcc.target/riscv/pragma-target-2.c | 26 +++ .../gcc.target/riscv/rvv/autovec/max-vect-1.c | 21 ++ .../gcc.target/riscv/rvv/autovec/max-vect-2.c | 21 ++ .../gcc.target/riscv/rvv/autovec/pr122635-1.c | 20 ++ .../gcc.target/riscv/rvv/autovec/pr122635-2.c | 18 ++ .../gcc.target/riscv/rvv/autovec/pr123022-2.c | 6 + .../gcc.target/riscv/rvv/autovec/pr123022.c | 21 ++ .../rvv/autovec/reduc/reduc-bool-1-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-1.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-2-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-2.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-3-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-3.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-4-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-4.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-5-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-5.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-6-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-6.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-7-run.c} | 4 +- .../riscv/rvv/autovec/reduc/reduc-bool-7.c | 25 +++ .../rvv/autovec/reduc/reduc-bool-8-run.c} | 6 +- .../riscv/rvv/autovec/reduc/reduc-bool-8.c | 25 +++ gcc/tree-vect-stmts.cc | 17 +- 45 files changed, 901 insertions(+), 162 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pragma-target-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pragma-target-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-1.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-2.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-3.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-4.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-5.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-6.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-7.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c copy gcc/testsuite/gcc.target/{aarch64/vect-reduc-bool-7.c => riscv/rvv/autovec/re [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c