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from 2c2a07e31cd tree-optimization/123755 - properly register loop mask for [...] new 3a05a375def RISC-V: Correct builtin registration order [PR123279]. new ca5a68ac280 RISC-V: Fix intrinsic FoF load at -O0 [PR122869]. new badd64289a4 forwprop: More nop-conversion handling [PR123731].

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Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 64 +----- .../riscv/riscv-vector-builtins-functions.def | 136 ++++++----- gcc/config/riscv/riscv-vector-builtins.cc | 256 ++++++++++++++++++--- gcc/config/riscv/riscv-vector-builtins.h | 63 ++++- gcc/config/riscv/riscv-vector-switch.def | 150 ++++++------ gcc/config/riscv/riscv.cc | 28 ++- gcc/testsuite/gcc.dg/vect/pr123731.c | 28 +++ .../gcc.target/riscv/rvv/base/pr122656-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c | 22 ++ .../gcc.target/riscv/rvv/vsetvl/ffload-3.c | 3 +- gcc/tree-ssa-forwprop.cc | 19 +- 11 files changed, 531 insertions(+), 240 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/pr123731.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c