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from a3e97daf1f7 [RISC-V] Fix trivial bootstrap failure on RISC-V new 3027010d8bc AArch64: expand extractions of Adv.SIMD registers from SVE [...]
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Summary of changes: gcc/config/aarch64/aarch64-sve.md | 42 +++ gcc/config/aarch64/iterators.md | 12 + gcc/config/aarch64/predicates.md | 4 + .../gcc.target/aarch64/simd/fold_to_highpart_6.c | 9 +- .../gcc.target/aarch64/sve/fold_to_highpart_1.c | 19 ++ .../gcc.target/aarch64/sve/fold_to_highpart_2.c | 295 +++++++++++++++++++++ 6 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/fold_to_highpart_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/fold_to_highpart_2.c