[Tcwg-commits] [gcc] branch master updated (2c762cd8892 -> d931a182471)

5 Feb 2026


      This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master
in repository gcc.
from  2c762cd8892 Daily bump.
       new  166da15d1fe RISC-V: Introduce vr2gpr-cost= for customizing the cost whe [...]
       new  da392652f2d RISC-V: Adjust the vx-[456]* testcase by param=vr2gpr-cost
       new  25d819a6e4d RISC-V: Introduce vr2fpr-cost= for customizing the cost whe [...]
       new  ff07e354bae RISC-V: Adjust the vf-[378]* testcase by param=vr2fpr-cost
       new  6d78bdac52b RISC-V: Add test case for PR123916
       new  d931a182471 RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c
The 6 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/riscv-opts.h                      |  7 +++--
 gcc/config/riscv/riscv-protos.h                    |  2 ++
 gcc/config/riscv/riscv-vector-costs.cc             |  4 +--
 gcc/config/riscv/riscv.cc                          | 34 +++++++++++++++++++--
 gcc/config/riscv/riscv.opt                         |  8 +++++
 .../rvv/autovec/{sat_add-cost-1.c => pr123916.c}   | 35 ++++++++--------------
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c  |  6 ++--
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c   |  6 ++--
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c  |  6 ++--
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c   |  6 ++--
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c   |  2 +-
 39 files changed, 102 insertions(+), 70 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{sat_add-cost-1.c => pr123916.c} (52%)
-- 
To stop receiving notification emails like this one, please contact
the administrator of this repository.

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

[Tcwg-commits] [gcc] branch master updated (2c762cd8892 -> d931a182471)