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from 808fc71d15a Add TARGET_MMX_WITH_SSE to the condition of all 64-bit _Flo [...] new e6470a44a25 pr122458.c: Replace .quad with .dc.a new 808b684172c RISC-V: Add support for _BitInt [PR117581] new cbb9d381520 VN: Fix VN ICE for large _BitInt types
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Summary of changes: gcc/config/riscv/riscv.cc | 34 ++++++++++++++ gcc/testsuite/gcc.dg/ipa/pr122458.c | 2 +- gcc/testsuite/gcc.dg/torture/bitint-64.c | 1 + gcc/testsuite/gcc.dg/torture/bitint-82.c | 1 + gcc/testsuite/gcc.dg/torture/bitint-84.c | 1 + gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c | 47 +++++++++++++++++++ .../{aarch64 => riscv}/bitint-alignments.c | 2 + .../{loongarch/la64 => riscv}/bitint-args.c | 53 +++++++++++----------- .../gcc.target/{aarch64 => riscv}/bitint-sizes.c | 5 ++ gcc/tree-ssa-sccvn.cc | 8 +++- .../libgcc-riscv.ver} | 3 +- libgcc/config/riscv/t-elf | 2 + libgcc/config/riscv/t-softfp32 | 5 +- 13 files changed, 134 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c copy gcc/testsuite/gcc.target/{aarch64 => riscv}/bitint-alignments.c (97%) copy gcc/testsuite/gcc.target/{loongarch/la64 => riscv}/bitint-args.c (50%) copy gcc/testsuite/gcc.target/{aarch64 => riscv}/bitint-sizes.c (90%) copy libgcc/config/{loongarch/libgcc-loongarch.ver => riscv/libgcc-riscv.ver} (91%)