;; Function peak_loop (peak_loop, funcdef_no=7, decl_uid=5366, cgraph_uid=7) try_optimize_cfg iteration 1 Redirecting fallthru edge 6->7 to 19 deleting insn with uid = 298. deleting insn with uid = 299. deleting block 7 Redirecting fallthru edge 16->17 to 19 deleting insn with uid = 301. deleting insn with uid = 302. deleting block 17 try_optimize_cfg iteration 2 try_optimize_cfg iteration 1 changing bb of uid 304 unscanned insn changing bb of uid 212 from 16 to 20 changing bb of uid 213 from 16 to 20 changing bb of uid 214 from 16 to 20 changing bb of uid 215 changing bb of uid 216 from 16 to 20 changing bb of uid 217 from 16 to 20 changing bb of uid 272 from 16 to 20 changing bb of uid 273 from 16 to 20 verify found no changes in insn with uid = 273. Edge 20->16 redirected to 20 Created preheader block for loop 3 ;; 4 loops found ;; ;; Loop 0 ;; header 0, latch 1 ;; depth 0, outer -1 ;; nodes: 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 20 18 19 ;; ;; Loop 3 ;; header 20, latch 20 ;; depth 1, outer 0 ;; nodes: 20 ;; ;; Loop 2 ;; header 11, latch 11 ;; depth 1, outer 0 ;; nodes: 11 ;; ;; Loop 1 ;; header 5, latch 5 ;; depth 1, outer 0 ;; nodes: 5 ;; 2 succs { 3 18 } ;; 3 succs { 4 8 } ;; 4 succs { 5 } ;; 5 succs { 5 6 } ;; 6 succs { 9 19 } ;; 8 succs { 9 } ;; 9 succs { 10 13 } ;; 10 succs { 11 } ;; 11 succs { 11 12 } ;; 12 succs { 13 19 } ;; 13 succs { 14 15 } ;; 14 succs { 16 15 } ;; 15 succs { 16 } ;; 16 succs { 20 } ;; 20 succs { 20 19 } ;; 18 succs { 19 } ;; 19 succs { 1 } Pass 0 for finding pseudo/allocno costs r355 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:19010 r354 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:19010 r353 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r352 costs: VFP_D0_D7_REGS:28530 VFP_LO_REGS:28530 VFP_REGS:3065535 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3065535 MEM:19020 r351 costs: VFP_D0_D7_REGS:2700 VFP_LO_REGS:2700 VFP_REGS:6898150 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:6898150 MEM:1800 r349 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r348 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r346 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r345 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r343 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 ALL_REGS:3645 MEM:2430 r342 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:2592 BASE_REGS:2592 HI_REGS:2592 GENERAL_REGS:2592 CORE_REGS:2592 MEM:2430 r337 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r336 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r335 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r334 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r333 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r332 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r331 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r330 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r329 costs: VFP_D0_D7_REGS:54600 VFP_LO_REGS:54600 VFP_REGS:179910550 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:179910550 MEM:36400 r328 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r327 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r324 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r323 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r322 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r321 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r318 costs: VFP_D0_D7_REGS:5400 VFP_LO_REGS:5400 VFP_REGS:18694450 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:18694450 MEM:3600 r312 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:110577 BASE_REGS:110577 HI_REGS:110577 GENERAL_REGS:110577 CORE_REGS:110577 ALL_REGS:111630 MEM:74420 r307 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r306 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r305 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r304 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r292 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r291 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r290 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:29120 BASE_REGS:29120 HI_REGS:29120 GENERAL_REGS:29120 CORE_REGS:29120 ALL_REGS:40950 MEM:27300 r287 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r285 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:27300 r279 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r278 costs: VFP_D0_D7_REGS:90420 VFP_LO_REGS:90420 VFP_REGS:130339235 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:130339235 MEM:60280 r277 costs: VFP_D0_D7_REGS:59730 VFP_LO_REGS:59730 VFP_REGS:8589815 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:8589815 MEM:39820 r276 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r275 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r274 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r270 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:27300 r267 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r262 costs: VFP_D0_D7_REGS:8535 VFP_LO_REGS:8535 VFP_REGS:7131070 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:7131070 MEM:5690 r239 costs: VFP_D0_D7_REGS:42165 VFP_LO_REGS:42165 VFP_REGS:4000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:4000000 MEM:28110 r229 costs: VFP_D0_D7_REGS:9990 VFP_LO_REGS:9990 VFP_REGS:8000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:8000000 MEM:6660 r228 costs: VFP_D0_D7_REGS:4995 VFP_LO_REGS:4995 VFP_REGS:4000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:4000000 MEM:3330 r227 costs: VFP_D0_D7_REGS:31080 VFP_LO_REGS:31080 VFP_REGS:122273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:122273700 MEM:20720 Pass 1 for finding pseudo/allocno costs r355: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r354: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r353: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r352: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r351: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r350: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r349: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r348: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r347: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r346: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r345: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r344: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r343: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r342: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r341: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r340: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r339: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r338: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r337: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r336: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r335: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r334: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r333: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r332: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r331: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r330: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r329: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r328: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r327: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r326: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r325: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r324: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r323: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r322: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r321: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r320: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r319: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r318: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r317: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r316: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r315: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r314: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r313: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r312: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r311: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r310: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r309: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r308: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r307: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r306: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r305: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r304: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r303: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r302: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r301: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r300: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r299: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r298: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r297: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r296: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r295: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r294: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r293: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r292: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r291: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r290: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r289: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r288: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r287: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r286: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r285: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r284: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r283: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r282: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r281: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r280: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r279: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r278: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r277: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r276: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r275: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r274: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r273: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r272: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r271: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r270: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r269: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r268: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r267: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r266: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r265: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r264: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r263: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r262: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r261: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r260: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r259: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r258: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r257: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r256: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r255: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r254: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r253: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r252: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r251: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r250: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r249: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r248: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r247: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r246: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r245: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r244: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r243: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r242: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r241: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r240: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r239: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r238: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r237: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r236: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r235: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r234: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r233: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r232: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r231: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r230: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r229: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r228: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r227: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r226: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r225: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r224: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r223: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r222: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r221: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r220: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r219: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r218: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r217: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r216: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r215: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r214: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r213: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r212: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r211: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r210: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r209: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r208: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r207: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r206: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r205: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r204: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r203: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r202: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r201: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r200: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r199: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r198: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r197: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r196: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r195: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r194: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r193: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r192: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r191: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r190: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r189: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r188: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r187: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r186: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r185: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r184: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r183: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r182: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r181: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r180: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r179: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r178: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r177: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r176: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r175: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r174: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r173: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r172: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r171: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r170: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r169: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r168: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r167: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r166: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r165: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r164: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r163: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r162: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r161: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r160: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r159: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r158: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r157: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r156: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r155: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r154: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r153: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r152: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r151: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r150: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r149: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r148: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r147: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r146: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r145: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r144: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r143: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r142: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r141: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r140: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r139: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r138: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r137: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r136: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r135: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r134: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r133: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r132: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r131: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r130: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r129: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r128: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r355 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:19010 r354 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:19010 r353 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r352 costs: VFP_D0_D7_REGS:28530 VFP_LO_REGS:28530 VFP_REGS:3065535 GENERAL_REGS:0 ALL_REGS:3065535 MEM:19020 r351 costs: VFP_D0_D7_REGS:2700 VFP_LO_REGS:2700 VFP_REGS:6898150 GENERAL_REGS:0 ALL_REGS:6898150 MEM:1800 r349 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r348 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r346 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r345 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r343 costs: VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 ALL_REGS:3645 MEM:2430 r342 costs: VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 MEM:2430 r337 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r336 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r335 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r334 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r333 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r332 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r331 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r330 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r329 costs: VFP_D0_D7_REGS:54600 VFP_LO_REGS:54600 VFP_REGS:179910550 GENERAL_REGS:0 ALL_REGS:179910550 MEM:36400 r328 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r327 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r324 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r323 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r322 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r321 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r318 costs: VFP_D0_D7_REGS:5400 VFP_LO_REGS:5400 VFP_REGS:18694450 GENERAL_REGS:0 ALL_REGS:18694450 MEM:3600 r312 costs: VFP_REGS:0 LO_REGS:111630 BASE_REGS:111630 HI_REGS:111630 GENERAL_REGS:111630 CORE_REGS:111630 ALL_REGS:111630 MEM:74420 r307 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r306 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r305 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r304 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r292 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r291 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r290 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r287 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r285 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:27300 r279 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r278 costs: VFP_D0_D7_REGS:90420 VFP_LO_REGS:90420 VFP_REGS:130339235 GENERAL_REGS:0 ALL_REGS:130339235 MEM:60280 r277 costs: VFP_D0_D7_REGS:59730 VFP_LO_REGS:59730 VFP_REGS:8589815 GENERAL_REGS:0 ALL_REGS:8589815 MEM:39820 r276 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r275 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r274 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r270 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:27300 r267 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r262 costs: VFP_D0_D7_REGS:8535 VFP_LO_REGS:8535 VFP_REGS:7131070 GENERAL_REGS:0 ALL_REGS:7131070 MEM:5690 r239 costs: VFP_D0_D7_REGS:42165 VFP_LO_REGS:42165 VFP_REGS:4000000 GENERAL_REGS:0 ALL_REGS:4000000 MEM:28110 r229 costs: VFP_D0_D7_REGS:9990 VFP_LO_REGS:9990 VFP_REGS:8000000 GENERAL_REGS:0 ALL_REGS:8000000 MEM:6660 r228 costs: VFP_D0_D7_REGS:4995 VFP_LO_REGS:4995 VFP_REGS:4000000 GENERAL_REGS:0 ALL_REGS:4000000 MEM:3330 r227 costs: VFP_D0_D7_REGS:31080 VFP_LO_REGS:31080 VFP_REGS:122273700 GENERAL_REGS:0 ALL_REGS:122273700 MEM:20720 starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 19 n_edges 28 count 22 ( 1.2) peak_loop Dataflow summary: def_info->table_size = 118, use_info->table_size = 198 ;; invalidated by call 0 [r0] 1 [r1] 2 [r2] 3 [r3] 12 [ip] 14 [lr] 15 [pc] 16 [f0] 17 [f1] 18 [f2] 19 [f3] 20 [f4] 21 [f5] 22 [f6] 23 [f7] 24 [cc] 27 [mv0] 28 [mv1] 29 [mv2] 30 [mv3] 31 [mv4] 32 [mv5] 33 [mv6] 34 [mv7] 35 [mv8] 36 [mv9] 37 [mv10] 38 [mv11] 39 [mv12] 40 [mv13] 41 [mv14] 42 [mv15] 43 [wcgr0] 44 [wcgr1] 45 [wcgr2] 46 [wcgr3] 47 [wr0] 48 [wr1] 49 [wr2] 50 [wr3] 51 [wr4] 52 [wr5] 53 [wr6] 54 [wr7] 55 [wr8] 56 [wr9] 57 [wr10] 58 [wr11] 59 [wr12] 60 [wr13] 61 [wr14] 62 [wr15] 63 [s0] 64 [s1] 65 [s2] 66 [s3] 67 [s4] 68 [s5] 69 [s6] 70 [s7] 71 [s8] 72 [s9] 73 [s10] 74 [s11] 75 [s12] 76 [s13] 77 [s14] 78 [s15] 95 [d16] 96 [?16] 97 [d17] 98 [?17] 99 [d18] 100 [?18] 101 [d19] 102 [?19] 103 [d20] 104 [?20] 105 [d21] 106 [?21] 107 [d22] 108 [?22] 109 [d23] 110 [?23] 111 [d24] 112 [?24] 113 [d25] 114 [?25] 115 [d26] 116 [?26] 117 [d27] 118 [?27] 119 [d28] 120 [?28] 121 [d29] 122 [?29] 123 [d30] 124 [?30] 125 [d31] 126 [?31] 127 [vfpcc] ;; hardware regs used 13 [sp] 25 [sfp] 26 [afp] ;; regular block artificial uses 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; eh block artificial uses 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; entry block defs 0 [r0] 1 [r1] 2 [r2] 3 [r3] 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 63 [s0] 64 [s1] 65 [s2] 66 [s3] 67 [s4] 68 [s5] 69 [s6] 70 [s7] 71 [s8] 72 [s9] 73 [s10] 74 [s11] 75 [s12] 76 [s13] 77 [s14] 78 [s15] ;; exit block uses 11 [fp] 13 [sp] 14 [lr] 25 [sfp] ;; regs ever live 24[cc] ;; ref usage r0={1d} r1={1d} r2={1d} r3={1d} r11={1d,18u} r13={1d,18u} r14={1d,1u} r24={11d,10u} r25={1d,18u} r26={1d,17u} r63={1d} r64={1d} r65={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r78={1d} r227={1d,4u} r228={1d,3u} r229={1d,7u} r239={2d,2u} r262={1d,8u} r267={2d,1u} r270={1d,2u} r274={1d,2u} r275={1d,3u} r276={1d,2u} r277={6d,4u} r278={5d,9u} r279={2d,1u} r285={1d,2u} r287={2d,1u} r290={1d,2u} r291={1d,2u} r292={1d,2u} r304={1d,2u} r305={1d,2u} r306={1d,2u} r307={1d,2u} r312={5d,6u} r318={1d,3u} r321={1d,1u} r322={1d,1u} r323={1d,1u} r324={1d,1u} r327={1d,2u} r328={1d,2u} r329={2d,2u} r330={1d,1u} r331={1d,1u} r332={1d,1u} r333={1d,1u} r334={1d,1u} r335={1d,1u} r336={1d,1u} r337={1d,1u} r342={2d,2u} r343={1d,2u} r345={1d,1u} r346={1d,1u} r348={1d,1u} r349={1d,1u} r351={1d,1u} r352={3d,2u} r353={1d,1u} r354={2d,2u} r355={2d,2u} ;; total ref usage 299{109d,190u,0e} in 86{86 regular + 0 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d0(0){ }d1(1){ }d2(2){ }d3(3){ }d4(11){ }d5(13){ }d6(14){ }d18(25){ }d19(26){ }d20(63){ }d21(64){ }d22(65){ }d23(66){ }d24(67){ }d25(68){ }d26(69){ }d27(70){ }d28(71){ }d29(72){ }d30(73){ }d31(74){ }d32(75){ }d33(76){ }d34(77){ }d35(78){ }} ;; bb 0 artificial_uses: { } ;; lr in ;; lr use ;; lr def 0 [r0] 1 [r1] 2 [r2] 3 [r3] 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 63 [s0] 64 [s1] 65 [s2] 66 [s3] 67 [s4] 68 [s5] 69 [s6] 70 [s7] 71 [s8] 72 [s9] 73 [s10] 74 [s11] 75 [s12] 76 [s13] 77 [s14] 78 [s15] ;; live in ;; live gen 0 [r0] 1 [r1] 2 [r2] 3 [r3] 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 63 [s0] 64 [s1] 65 [s2] 66 [s3] 67 [s4] 68 [s5] 69 [s6] 70 [s7] 71 [s8] 72 [s9] 73 [s10] 74 [s11] 75 [s12] 76 [s13] 77 [s14] 78 [s15] ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ( 0 )->[2]->( 3 18 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u0(11){ }u1(13){ }u2(25){ }u3(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; lr def 24 [cc] 227 228 229 318 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; live gen 24 [cc] 227 228 229 318 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 ( 2 )->[3]->( 4 8 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u9(11){ }u10(13){ }u11(25){ }u12(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 227 229 ;; lr def 24 [cc] 262 321 322 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 ;; live gen 24 [cc] 262 321 322 ;; live kill 24 [cc] ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ( 3 )->[4]->( 5 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u19(11){ }u20(13){ }u21(25){ }u22(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 228 262 ;; lr def 277 278 279 355 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ;; live gen 277 278 279 355 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ( 4 5 )->[5]->( 5 6 ) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u26(11){ }u27(13){ }u28(25){ }u29(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 227 277 278 279 355 ;; lr def 24 [cc] 270 277 278 279 323 324 355 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ;; live gen 24 [cc] 270 277 278 279 323 324 355 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 ( 5 )->[6]->( 9 19 ) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u44(11){ }u45(13){ }u46(25){ }u47(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 229 262 ;; lr def 24 [cc] ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; live gen 24 [cc] ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ( 3 )->[8]->( 9 ) ;; bb 8 artificial_defs: { } ;; bb 8 artificial_uses: { u51(11){ }u52(13){ }u53(25){ }u54(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 262 ;; lr def 277 278 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 ;; live gen 277 278 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ( 8 6 )->[9]->( 10 13 ) ;; bb 9 artificial_defs: { } ;; bb 9 artificial_uses: { u57(11){ }u58(13){ }u59(25){ }u60(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 229 262 ;; lr def 24 [cc] 274 275 276 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 ;; live gen 24 [cc] 274 275 276 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 274 275 276 277 278 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 274 275 276 277 278 ( 9 )->[10]->( 11 ) ;; bb 10 artificial_defs: { } ;; bb 10 artificial_uses: { u67(11){ }u68(13){ }u69(25){ }u70(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 274 275 276 277 278 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 227 228 262 275 ;; lr def 239 267 312 354 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 274 275 276 277 278 ;; live gen 239 267 312 354 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ( 11 10 )->[11]->( 11 12 ) ;; bb 11 artificial_defs: { } ;; bb 11 artificial_uses: { u77(11){ }u78(13){ }u79(25){ }u80(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 239 267 312 354 ;; lr def 24 [cc] 239 267 290 291 292 304 305 306 307 312 327 328 329 330 331 332 333 334 335 336 337 354 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ;; live gen 24 [cc] 239 267 290 291 292 304 305 306 307 312 327 328 329 330 331 332 333 334 335 336 337 354 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 ( 11 )->[12]->( 13 19 ) ;; bb 12 artificial_defs: { } ;; bb 12 artificial_uses: { u124(11){ }u125(13){ }u126(25){ }u127(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 274 276 277 278 312 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 274 276 277 278 312 ;; lr def 24 [cc] 277 278 342 343 345 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 274 276 277 278 312 ;; live gen 24 [cc] 277 278 342 343 345 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 277 278 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 277 278 ( 12 9 )->[13]->( 14 15 ) ;; bb 13 artificial_defs: { } ;; bb 13 artificial_uses: { u142(11){ }u143(13){ }u144(25){ }u145(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 277 278 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 228 229 278 ;; lr def 24 [cc] 287 346 352 353 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 277 278 ;; live gen 24 [cc] 287 346 352 353 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 229 277 278 287 352 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 229 277 278 287 352 ( 13 )->[14]->( 16 15 ) ;; bb 14 artificial_defs: { } ;; bb 14 artificial_uses: { u156(11){ }u157(13){ }u158(25){ }u159(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 229 277 278 287 352 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 229 ;; lr def 24 [cc] ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 229 277 278 287 352 ;; live gen 24 [cc] ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ( 13 14 )->[15]->( 16 ) ;; bb 15 artificial_defs: { } ;; bb 15 artificial_uses: { u162(11){ }u163(13){ }u164(25){ }u165(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; lr def 352 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 ;; live gen 352 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ( 14 15 )->[16]->( 20 ) ;; bb 16 artificial_defs: { } ;; bb 16 artificial_uses: { u166(11){ }u167(13){ }u168(25){ }u169(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; lr def ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; live gen 24 [cc] 277 278 285 287 348 349 352 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ( 16 20 )->[20]->( 20 19 ) ;; bb 20 artificial_defs: { } ;; bb 20 artificial_uses: { u-1(11){ }u-1(13){ }u-1(25){ }u-1(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; lr def 24 [cc] 277 278 285 287 348 349 352 ;; live in ;; live gen ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 ;; live out ( 2 )->[18]->( 19 ) ;; bb 18 artificial_defs: { } ;; bb 18 artificial_uses: { u184(11){ }u185(13){ }u186(25){ }u187(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] ;; lr def 277 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; live gen 277 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 277 ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 277 ( 18 6 12 20 )->[19]->( 1 ) ;; bb 19 artificial_defs: { } ;; bb 19 artificial_uses: { u188(11){ }u189(13){ }u190(25){ }u191(26){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 277 ;; lr use 11 [fp] 13 [sp] 25 [sfp] 26 [afp] 277 ;; lr def 351 ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 277 ;; live gen 351 ;; live kill ;; lr out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ;; live out 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] ( 19 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u194(11){ }u195(13){ }u196(14){ }u197(25){ }} ;; lr in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] ;; lr use 11 [fp] 13 [sp] 14 [lr] 25 [sfp] ;; lr def ;; live in 11 [fp] 13 [sp] 14 [lr] 25 [sfp] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 125 to worklist Adding insn 123 to worklist Adding insn 120 to worklist Adding insn 117 to worklist Adding insn 132 to worklist Adding insn 290 to worklist Adding insn 148 to worklist Adding insn 155 to worklist Adding insn 287 to worklist Adding insn 204 to worklist Adding insn 280 to worklist Adding insn 283 to worklist Adding insn 273 to worklist Adding insn 229 to worklist Finished finding needed instructions: processing block 19 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] Adding insn 228 to worklist processing block 20 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 Adding insn 272 to worklist Adding insn 217 to worklist Adding insn 216 to worklist Adding insn 214 to worklist Adding insn 213 to worklist Adding insn 212 to worklist processing block 16 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 processing block 15 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 Adding insn 285 to worklist processing block 14 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 277 278 287 352 Adding insn 282 to worklist processing block 13 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 229 277 278 287 352 Adding insn 279 to worklist Adding insn 277 to worklist Adding insn 274 to worklist Adding insn 209 to worklist Adding insn 207 to worklist processing block 12 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 277 278 Adding insn 203 to worklist Adding insn 202 to worklist Adding insn 201 to worklist Adding insn 200 to worklist Adding insn 199 to worklist Adding insn 297 to worklist Adding insn 197 to worklist processing block 11 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 Adding insn 286 to worklist Adding insn 191 to worklist Adding insn 190 to worklist Adding insn 188 to worklist Adding insn 186 to worklist Adding insn 184 to worklist Adding insn 182 to worklist Adding insn 181 to worklist Adding insn 180 to worklist Adding insn 179 to worklist Adding insn 178 to worklist Adding insn 177 to worklist Adding insn 176 to worklist Adding insn 175 to worklist Adding insn 174 to worklist Adding insn 173 to worklist Adding insn 172 to worklist Adding insn 171 to worklist Adding insn 169 to worklist Adding insn 165 to worklist Adding insn 296 to worklist Adding insn 164 to worklist Adding insn 163 to worklist Adding insn 161 to worklist processing block 10 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 239 267 274 276 277 278 312 354 Adding insn 288 to worklist Adding insn 111 to worklist Adding insn 159 to worklist Adding insn 158 to worklist processing block 9 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 274 275 276 277 278 Adding insn 154 to worklist Adding insn 152 to worklist Adding insn 151 to worklist processing block 6 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 Adding insn 147 to worklist processing block 5 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 Adding insn 289 to worklist Adding insn 142 to worklist Adding insn 141 to worklist Adding insn 139 to worklist Adding insn 138 to worklist Adding insn 137 to worklist processing block 4 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 279 355 Adding insn 291 to worklist Adding insn 107 to worklist Adding insn 106 to worklist Adding insn 134 to worklist processing block 8 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 277 278 Adding insn 109 to worklist Adding insn 108 to worklist processing block 3 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 262 Adding insn 131 to worklist Adding insn 130 to worklist Adding insn 129 to worklist Adding insn 128 to worklist processing block 18 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 277 Adding insn 112 to worklist processing block 2 lr out = 11 [fp] 13 [sp] 14 [lr] 25 [sfp] 26 [afp] 227 228 229 Adding insn 124 to worklist Adding insn 116 to worklist df_worklist_dataflow_doublequeue:n_basic_blocks 19 n_edges 28 count 22 ( 1.2) df_worklist_dataflow_doublequeue:n_basic_blocks 19 n_edges 28 count 22 ( 1.2) SMS analysis phase =================== SMS loop num: 3, file: autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c, line: 26 ...OK SMS loop num: 2, file: (null), line: 0 ...OK SMS loop num: 1, file: (null), line: 0 SMS transformation phase ========================= SMS loop num: 3, file: autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c, line: 26 Node num: 0 (insn 212 304 213 20 (set (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg/v:SI 278 [ i ])) [0 MEM[base: pix1_3, index: D.7175_19, offset: 0B]+0 S1 A8]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 175 {*arm_extendqisi_v6} (nil)) OUT ARCS: [212 -(T,3,0)-> 214] IN ARCS: [217 -(T,1,1)-> 212] Node num: 1 (insn 213 212 214 20 (set (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 287 [ ivtmp.61 ])) [2 MEM[base: D.7176_20, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 287 [ ivtmp.61 ]) (nil))) OUT ARCS: [213 -(T,3,1)-> 213] [213 -(T,3,0)-> 214] IN ARCS: [213 -(T,3,1)-> 213] Node num: 2 (insn 214 213 215 20 (set (reg:SI 285 [ D.7092 ]) (minus:SI (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 31 {*arm_subsi3_insn} (expr_list:REG_DEAD (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (expr_list:REG_DEAD (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (nil)))) OUT ARCS: [214 -(T,1,0)-> 216] IN ARCS: [212 -(T,3,0)-> 214] [213 -(T,3,0)-> 214] Node num: 3 (insn 216 215 217 20 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 285 [ D.7092 ]) (reg:SI 285 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 285 [ D.7092 ]) (nil))) OUT ARCS: [216 -(T,4,1)-> 216] IN ARCS: [216 -(T,4,1)-> 216] [214 -(T,1,0)-> 216] Node num: 4 (insn 217 216 272 20 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) OUT ARCS: [217 -(T,1,1)-> 212] [217 -(T,1,1)-> 217] IN ARCS: [217 -(T,1,1)-> 217] Node num: 5 (insn 272 217 273 20 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 352) (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff]))) ]) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 6 {addsi3_compare0} (nil)) OUT ARCS: [272 -(T,1,1)-> 272] [272 -(T,1,1)-> 272] [272 -(T,2,0)-> 273] IN ARCS: [272 -(T,1,1)-> 272] [272 -(T,1,1)-> 272] [273 -(A,0,1)-> 272] Node num: 6 (jump_insn 273 272 235 20 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 305) (pc))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 305) OUT ARCS: [273 -(A,0,1)-> 272] IN ARCS: [272 -(T,2,0)-> 273] autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c 26 (file, line) SMS single-bb-loop SMS doloop SMS built-ddg 7 SMS num-loads 2 SMS num-stores 0 Order params node 0, ASAP: 0, ALAP: 0, HEIGHT: 4 node 1, ASAP: 0, ALAP: 0, HEIGHT: 4 node 2, ASAP: 3, ALAP: 3, HEIGHT: 1 node 3, ASAP: 4, ALAP: 4, HEIGHT: 0 node 4, ASAP: 0, ALAP: 4, HEIGHT: 0 node 5, ASAP: 0, ALAP: 2, HEIGHT: 2 node 6, ASAP: 2, ALAP: 4, HEIGHT: 0 ;; Number of SCC nodes - 4 SCC number: 0 insn num 3 (insn 216 215 217 20 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 285 [ D.7092 ]) (reg:SI 285 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 285 [ D.7092 ]) (nil))) SCC number: 1 insn num 1 (insn 213 212 214 20 (set (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 287 [ ivtmp.61 ])) [2 MEM[base: D.7176_20, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 287 [ ivtmp.61 ]) (nil))) SCC number: 2 insn num 5 (insn 272 217 273 20 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 352) (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff]))) ]) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 6 {addsi3_compare0} (nil)) insn num 6 (jump_insn 273 272 235 20 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 305) (pc))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 305) SCC number: 3 insn num 4 (insn 217 216 272 20 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) SMS final nodes order: 3 2 1 6 5 0 4 SMS iis 4 4 8 (rec_mii, mii, maxii) Starting with ii=4 Trying to schedule node 3 INSN = 216 in (4 .. 8) step 1 must_precede: must_follow: Scheduled w/o split in 4 Analyzing dependencies for node 2 (INSN 214); ii = 4 start early start late start end time =========== =========== =========== =========== ===== -2147483648 3 4 [214 -(T,1,0)-> 216] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 3 2147483647 (max, max, min, min) 0 3 final window Trying to schedule node 2 INSN = 214 in (3 .. -1) step -1 must_precede: must_follow: Scheduled w/o split in 3 Analyzing dependencies for node 1 (INSN 213); ii = 4 start early start late start end time =========== =========== =========== =========== ===== -2147483648 0 3 [213 -(T,3,0)-> 214] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 0 2147483647 (max, max, min, min) -3 0 final window Trying to schedule node 1 INSN = 213 in (0 .. -4) step -1 must_precede: must_follow: Scheduled w/o split in 0 Trying to schedule node 6 INSN = 273 in (2 .. 6) step 1 must_precede: must_follow: Scheduled w/o split in 2 Analyzing dependencies for node 5 (INSN 272); ii = 4 start early start late start end time =========== =========== =========== =========== ===== -2 2147483647 2 [273 -(A,0,1)-> 272] -2147483648 0 2 [272 -(T,2,0)-> 273] ----------- ----------- ----------- ----------- ----- -2147483648 -2 0 2147483647 (max, max, min, min) -2 0 final window Trying to schedule node 5 INSN = 272 in (0 .. -3) step -1 must_precede: 6 must_follow: Scheduled w/o split in -1 Analyzing dependencies for node 0 (INSN 212); ii = 4 start early start late start end time =========== =========== =========== =========== ===== -2147483648 0 3 [212 -(T,3,0)-> 214] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 0 2147483647 (max, max, min, min) -3 0 final window Trying to schedule node 0 INSN = 212 in (0 .. -4) step -1 must_precede: must_follow: Scheduled w/o split in -2 Analyzing dependencies for node 4 (INSN 217); ii = 4 start early start late start end time =========== =========== =========== =========== ===== -2147483648 1 -2 [217 -(T,1,1)-> 212] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 1 2147483647 (max, max, min, min) -2 1 final window Trying to schedule node 4 INSN = 217 in (1 .. -3) step -1 must_precede: must_follow: Scheduled w/o split in 1 SMS Trying to optimize branch location SMS partial schedule before trial: [ROW 0 ]: 213, 216, [ROW 1 ]: 217, [ROW 2 ]: 212, 273 (branch), [ROW 3 ]: 272, 214, crr_insn->node=1 (insn id 213), crr_insn->cycle=2, min_cycle=0 crr_insn->node=3 (insn id 216), crr_insn->cycle=6, min_cycle=0 crr_insn->node=4 (insn id 217), crr_insn->cycle=3, min_cycle=0 crr_insn->node=0 (insn id 212), crr_insn->cycle=0, min_cycle=0 crr_insn->node=6 (insn id 273), crr_insn->cycle=4, min_cycle=0 (branch) crr_insn->node=5 (insn id 272), crr_insn->cycle=1, min_cycle=0 crr_insn->node=2 (insn id 214), crr_insn->cycle=5, min_cycle=0 SMS partial schedule after normalization (ii, 4, SC 2): [ROW 0 ]: 212, 273 (branch), [ROW 1 ]: 272, 214, [ROW 2 ]: 213, 216, [ROW 3 ]: 217, Analyzing dependencies for node 6 (INSN 273); ii = 4 start early start late start end time =========== =========== =========== =========== ===== 3 2147483647 1 [272 -(T,2,0)-> 273] -2147483648 5 1 [273 -(A,0,1)-> 272] ----------- ----------- ----------- ----------- ----- -2147483648 3 5 2147483647 (max, max, min, min) 3 5 final window Trying to schedule node 6 INSN = 273 in (3 .. 6) step 1 must_precede: must_follow: 5 Scheduled w/o split in 3 SMS success in moving branch to cycle 3 Scheduling register move INSN 307; ii = 4, min cycle = 0 (insn 307 0 0 (set (reg:SI 356) (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ])) -1 (nil)) start end time =========== =========== ===== 3 4 0 212 --(T,3,0)--> 307 1 4 5 307 --(T,1,0)--> 214 ----------- ----------- ----- 3 4 (max, min) Scheduled register move INSN 307 at time 4, row 0 Pass 0 for finding pseudo/allocno costs r355 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:19010 r354 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:19010 r353 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r352 costs: VFP_D0_D7_REGS:28530 VFP_LO_REGS:28530 VFP_REGS:3065535 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3065535 MEM:19020 r351 costs: VFP_D0_D7_REGS:2700 VFP_LO_REGS:2700 VFP_REGS:6898150 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:6898150 MEM:1800 r349 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r348 costs: VFP_D0_D7_REGS:13650 VFP_LO_REGS:13650 VFP_REGS:1000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:1000000 MEM:9100 r346 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r345 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r343 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 ALL_REGS:3645 MEM:2430 r342 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:2592 BASE_REGS:2592 HI_REGS:2592 GENERAL_REGS:2592 CORE_REGS:2592 MEM:2430 r337 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r336 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r335 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r334 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r333 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r332 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r331 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r330 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r329 costs: VFP_D0_D7_REGS:54600 VFP_LO_REGS:54600 VFP_REGS:179910550 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:179910550 MEM:36400 r328 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r327 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r324 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r323 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:18200 r322 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r321 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:2000000 MEM:1620 r318 costs: VFP_D0_D7_REGS:5400 VFP_LO_REGS:5400 VFP_REGS:18694450 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:18694450 MEM:3600 r312 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:110577 BASE_REGS:110577 HI_REGS:110577 GENERAL_REGS:110577 CORE_REGS:110577 ALL_REGS:111630 MEM:74420 r307 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r306 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r305 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r304 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r292 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r291 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r290 costs: VFP_D0_D7_REGS:0 VFP_LO_REGS:0 VFP_HI_REGS:0 VFP_REGS:0 LO_REGS:29120 BASE_REGS:29120 HI_REGS:29120 GENERAL_REGS:29120 CORE_REGS:29120 ALL_REGS:40950 MEM:27300 r287 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r285 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:27300 r279 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r278 costs: VFP_D0_D7_REGS:90420 VFP_LO_REGS:90420 VFP_REGS:130339235 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:130339235 MEM:60280 r277 costs: VFP_D0_D7_REGS:59730 VFP_LO_REGS:59730 VFP_REGS:8589815 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:8589815 MEM:39820 r276 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r275 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r274 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:2430 r270 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:3000000 MEM:27300 r267 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:120273700 MEM:19010 r262 costs: VFP_D0_D7_REGS:8535 VFP_LO_REGS:8535 VFP_REGS:7131070 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:7131070 MEM:5690 r239 costs: VFP_D0_D7_REGS:42165 VFP_LO_REGS:42165 VFP_REGS:4000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:4000000 MEM:28110 r229 costs: VFP_D0_D7_REGS:9990 VFP_LO_REGS:9990 VFP_REGS:8000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:8000000 MEM:6660 r228 costs: VFP_D0_D7_REGS:4995 VFP_LO_REGS:4995 VFP_REGS:4000000 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:4000000 MEM:3330 r227 costs: VFP_D0_D7_REGS:31080 VFP_LO_REGS:31080 VFP_REGS:122273700 LO_REGS:0 BASE_REGS:0 HI_REGS:0 GENERAL_REGS:0 CORE_REGS:0 ALL_REGS:122273700 MEM:20720 Pass 1 for finding pseudo/allocno costs r356: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r355: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r354: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r353: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r352: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r351: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r350: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r349: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r348: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r347: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r346: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r345: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r344: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r343: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r342: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r341: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r340: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r339: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r338: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r337: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r336: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r335: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r334: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r333: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r332: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r331: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r330: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r329: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r328: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r327: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r326: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r325: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r324: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r323: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r322: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r321: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r320: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r319: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r318: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r317: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r316: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r315: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r314: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r313: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r312: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r311: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r310: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r309: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r308: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r307: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r306: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r305: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r304: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r303: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r302: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r301: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r300: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r299: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r298: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r297: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r296: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r295: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r294: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r293: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r292: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r291: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r290: preferred VFP_REGS, alternative NO_REGS, allocno VFP_REGS r289: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r288: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r287: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r286: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r285: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r284: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r283: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r282: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r281: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r280: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r279: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r278: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r277: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r276: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r275: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r274: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r273: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r272: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r271: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r270: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r269: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r268: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r267: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r266: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r265: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r264: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r263: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r262: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r261: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r260: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r259: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r258: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r257: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r256: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r255: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r254: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r253: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r252: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r251: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r250: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r249: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r248: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r247: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r246: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r245: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r244: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r243: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r242: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r241: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r240: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r239: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r238: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r237: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r236: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r235: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r234: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r233: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r232: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r231: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r230: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r229: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r228: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r227: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r226: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r225: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r224: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r223: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r222: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r221: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r220: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r219: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r218: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r217: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r216: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r215: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r214: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r213: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r212: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r211: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r210: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r209: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r208: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r207: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r206: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r205: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r204: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r203: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r202: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r201: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r200: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r199: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r198: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r197: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r196: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r195: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r194: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r193: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r192: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r191: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r190: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r189: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r188: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r187: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r186: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r185: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r184: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r183: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r182: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r181: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r180: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r179: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r178: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r177: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r176: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r175: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r174: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r173: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r172: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r171: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r170: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r169: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r168: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r167: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r166: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r165: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r164: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r163: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r162: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r161: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r160: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r159: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r158: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r157: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r156: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r155: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r154: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r153: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r152: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r151: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r150: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r149: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r148: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r147: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r146: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r145: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r144: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r143: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r142: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r141: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r140: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r139: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r138: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r137: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r136: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r135: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r134: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r133: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r132: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r131: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r130: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r129: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r128: preferred ALL_REGS, alternative NO_REGS, allocno ALL_REGS r355 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:19010 r354 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:19010 r353 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r352 costs: VFP_D0_D7_REGS:28530 VFP_LO_REGS:28530 VFP_REGS:3065535 GENERAL_REGS:0 ALL_REGS:3065535 MEM:19020 r351 costs: VFP_D0_D7_REGS:2700 VFP_LO_REGS:2700 VFP_REGS:6898150 GENERAL_REGS:0 ALL_REGS:6898150 MEM:1800 r349 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r348 costs: VFP_D0_D7_REGS:13650 VFP_LO_REGS:13650 VFP_REGS:1000000 GENERAL_REGS:0 ALL_REGS:1000000 MEM:9100 r346 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r345 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r343 costs: VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 ALL_REGS:3645 MEM:2430 r342 costs: VFP_REGS:0 LO_REGS:3645 BASE_REGS:3645 HI_REGS:3645 GENERAL_REGS:3645 CORE_REGS:3645 MEM:2430 r337 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r336 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r335 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r334 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r333 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r332 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r331 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r330 costs: VFP_REGS:0 LO_REGS:27300 BASE_REGS:27300 HI_REGS:27300 GENERAL_REGS:27300 CORE_REGS:27300 ALL_REGS:27300 MEM:18200 r329 costs: VFP_D0_D7_REGS:54600 VFP_LO_REGS:54600 VFP_REGS:179910550 GENERAL_REGS:0 ALL_REGS:179910550 MEM:36400 r328 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r327 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r324 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r323 costs: VFP_D0_D7_REGS:27300 VFP_LO_REGS:27300 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:18200 r322 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r321 costs: VFP_D0_D7_REGS:2430 VFP_LO_REGS:2430 VFP_REGS:2000000 GENERAL_REGS:0 ALL_REGS:2000000 MEM:1620 r318 costs: VFP_D0_D7_REGS:5400 VFP_LO_REGS:5400 VFP_REGS:18694450 GENERAL_REGS:0 ALL_REGS:18694450 MEM:3600 r312 costs: VFP_REGS:0 LO_REGS:111630 BASE_REGS:111630 HI_REGS:111630 GENERAL_REGS:111630 CORE_REGS:111630 ALL_REGS:111630 MEM:74420 r307 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r306 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r305 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r304 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r292 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r291 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r290 costs: VFP_REGS:0 LO_REGS:40950 BASE_REGS:40950 HI_REGS:40950 GENERAL_REGS:40950 CORE_REGS:40950 ALL_REGS:40950 MEM:27300 r287 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r285 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:27300 r279 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r278 costs: VFP_D0_D7_REGS:90420 VFP_LO_REGS:90420 VFP_REGS:130339235 GENERAL_REGS:0 ALL_REGS:130339235 MEM:60280 r277 costs: VFP_D0_D7_REGS:59730 VFP_LO_REGS:59730 VFP_REGS:8589815 GENERAL_REGS:0 ALL_REGS:8589815 MEM:39820 r276 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r275 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r274 costs: VFP_D0_D7_REGS:3645 VFP_LO_REGS:3645 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:2430 r270 costs: VFP_D0_D7_REGS:40950 VFP_LO_REGS:40950 VFP_REGS:3000000 GENERAL_REGS:0 ALL_REGS:3000000 MEM:27300 r267 costs: VFP_D0_D7_REGS:28515 VFP_LO_REGS:28515 VFP_REGS:120273700 GENERAL_REGS:0 ALL_REGS:120273700 MEM:19010 r262 costs: VFP_D0_D7_REGS:8535 VFP_LO_REGS:8535 VFP_REGS:7131070 GENERAL_REGS:0 ALL_REGS:7131070 MEM:5690 r239 costs: VFP_D0_D7_REGS:42165 VFP_LO_REGS:42165 VFP_REGS:4000000 GENERAL_REGS:0 ALL_REGS:4000000 MEM:28110 r229 costs: VFP_D0_D7_REGS:9990 VFP_LO_REGS:9990 VFP_REGS:8000000 GENERAL_REGS:0 ALL_REGS:8000000 MEM:6660 r228 costs: VFP_D0_D7_REGS:4995 VFP_LO_REGS:4995 VFP_REGS:4000000 GENERAL_REGS:0 ALL_REGS:4000000 MEM:3330 r227 costs: VFP_D0_D7_REGS:31080 VFP_LO_REGS:31080 VFP_REGS:122273700 GENERAL_REGS:0 ALL_REGS:122273700 MEM:20720 Loop 3 (parent 0, header bb20, depth 1) ref. regnos: 24 227 277 278 285 287 348 349 352 356 live regnos: 11 13 14 24 25 26 227 277 278 285 287 348 349 352 356 Pressure:GENERAL_REGS=10 14 changing bb of uid 308 unscanned insn verify found no changes in insn with uid = 273. Edge 20->20 redirected to 21 autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 SMS succeeded 4 2 (with ii, sc) [ROW 0 ]: 307, 212, [ROW 1 ]: 272, 214, [ROW 2 ]: 213, 216, [ROW 3 ]: 217, 273 (branch), deleting insn with uid = 310. changing bb of uid 318 unscanned insn changing bb of uid 311 unscanned insn scanning new insn with uid = 311. changing bb of uid 312 unscanned insn scanning new insn with uid = 312. changing bb of uid 313 unscanned insn scanning new insn with uid = 313. changing bb of uid 314 unscanned insn scanning new insn with uid = 314. changing bb of uid 315 unscanned insn scanning new insn with uid = 315. changing bb of uid 316 unscanned insn scanning new insn with uid = 316. changing bb of uid 317 unscanned insn scanning new insn with uid = 317. deleting insn with uid = 319. changing bb of uid 320 unscanned insn verify found no changes in insn with uid = 317. Edge 22->21 redirected to 23 Redirecting fallthru edge 23->20 to 22 Redirecting fallthru edge 23->22 to 20 Redirecting fallthru edge 16->20 to 22 changing bb of uid 322 unscanned insn Redirecting fallthru edge 16->22 to 24 scanning new insn with uid = 323. scanning new insn with uid = 324. Redirecting fallthru edge 23->20 to 22 changing bb of uid 325 unscanned insn verify found no changes in insn with uid = 324. Edge 24->20 redirected to 25 changing bb of uid 327 unscanned insn Redirecting fallthru edge 24->22 to 26 scanning new insn with uid = 307. rescanning insn with uid = 214. deleting insn with uid = 214. Node = 0; INSN = 212 asap = 0: time = 0: stage = 0: Node = 1; INSN = 213 asap = 0: time = 2: stage = 0: Node = 2; INSN = 214 asap = 3: time = 5: stage = 1: Node = 3; INSN = 216 asap = 4: time = 6: stage = 1: Node = 4; INSN = 217 asap = 0: time = 3: stage = 0: Node = 5; INSN = 272 asap = 0: time = 1: stage = 0: Node = 6; INSN = 273 asap = 2: time = 3: stage = 0: deleting insn with uid = 329. deleting insn with uid = 331. deleting insn with uid = 333. changing bb of uid 335 unscanned insn Redirecting fallthru edge 25->20 to 27 scanning new insn with uid = 328. scanning new insn with uid = 330. scanning new insn with uid = 332. scanning new insn with uid = 334. deleting insn with uid = 337. deleting insn with uid = 339. changing bb of uid 341 unscanned insn Redirecting fallthru edge 20->19 to 28 scanning new insn with uid = 336. scanning new insn with uid = 338. scanning new insn with uid = 340. SMS loop num: 2, file: (null), line: 0 Node num: 0 (insn 161 160 163 11 (set (reg:V16QI 290 [ vect_var_.35 ]) (mem:V16QI (post_inc:SI (reg:SI 267 [ ivtmp.89 ])) [0 MEM[base: D.7206_62, offset: 0B]+0 S16 A128])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 757 {*neon_movv16qi} (expr_list:REG_INC (reg:SI 267 [ ivtmp.89 ]) (nil))) OUT ARCS: [161 -(T,0,1)-> 161] [161 -(T,0,0)-> 164] [161 -(T,0,0)-> 163] IN ARCS: [161 -(T,0,1)-> 161] Node num: 1 (insn 163 161 164 11 (set (reg:V8HI 291 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1721 {neon_vec_unpacks_lo_v16qi} (nil)) OUT ARCS: [163 -(T,3,0)-> 174] [163 -(T,3,0)-> 171] IN ARCS: [161 -(T,0,0)-> 163] Node num: 2 (insn 164 163 296 11 (set (reg:V8HI 292 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 8 [0x8]) (const_int 9 [0x9]) (const_int 10 [0xa]) (const_int 11 [0xb]) (const_int 12 [0xc]) (const_int 13 [0xd]) (const_int 14 [0xe]) (const_int 15 [0xf]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1727 {neon_vec_unpacks_hi_v16qi} (expr_list:REG_DEAD (reg:V16QI 290 [ vect_var_.35 ]) (nil))) OUT ARCS: [164 -(T,3,0)-> 180] [164 -(T,3,0)-> 177] IN ARCS: [161 -(T,0,0)-> 164] Node num: 3 (insn 296 164 165 11 (set (reg/f:SI 329) (reg/f:SI 239 [ vect_p.38 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 639 {*arm_movsi_vfp} (nil)) OUT ARCS: [296 -(T,2,0)-> 169] [296 -(T,2,0)-> 165] IN ARCS: [169 -(A,0,1)-> 296] [191 -(T,1,1)-> 296] Node num: 4 (insn 165 296 169 11 (set (reg:V8HI 327) (unspec:V8HI [ (mem:V8HI (post_inc:SI (reg/f:SI 329)) [2 MEM[(int16_t *)vect_p.38_128]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_INC (reg/f:SI 329) (nil))) OUT ARCS: [165 -(T,2,0)-> 175] [165 -(T,2,0)-> 172] [165 -(T,2,0)-> 169] IN ARCS: [296 -(T,2,0)-> 165] Node num: 5 (insn 169 165 171 11 (set (reg:V8HI 328) (unspec:V8HI [ (mem:V8HI (reg/f:SI 329) [2 MEM[(int16_t *)D.7209_27]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_DEAD (reg/f:SI 329) (nil))) OUT ARCS: [169 -(A,0,1)-> 296] [169 -(T,2,0)-> 181] [169 -(T,2,0)-> 178] IN ARCS: [296 -(T,2,0)-> 169] [165 -(T,2,0)-> 169] Node num: 6 (insn 171 169 172 11 (set (reg:V4SI 330) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) OUT ARCS: [171 -(T,3,0)-> 173] IN ARCS: [163 -(T,3,0)-> 171] Node num: 7 (insn 172 171 173 11 (set (reg:V4SI 331) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) OUT ARCS: [172 -(T,3,0)-> 173] IN ARCS: [165 -(T,2,0)-> 172] Node num: 8 (insn 173 172 174 11 (set (reg:V4SI 304 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 330) (reg:V4SI 331))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 331) (expr_list:REG_DEAD (reg:V4SI 330) (nil)))) OUT ARCS: [173 -(T,3,0)-> 184] IN ARCS: [171 -(T,3,0)-> 173] [172 -(T,3,0)-> 173] Node num: 9 (insn 174 173 175 11 (set (reg:V4SI 332) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 291 [ vect_var_.37 ]) (nil))) OUT ARCS: [174 -(T,3,0)-> 176] IN ARCS: [163 -(T,3,0)-> 174] Node num: 10 (insn 175 174 176 11 (set (reg:V4SI 333) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 327) (nil))) OUT ARCS: [175 -(T,3,0)-> 176] IN ARCS: [165 -(T,2,0)-> 175] Node num: 11 (insn 176 175 177 11 (set (reg:V4SI 305 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 332) (reg:V4SI 333))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 333) (expr_list:REG_DEAD (reg:V4SI 332) (nil)))) OUT ARCS: [176 -(T,3,0)-> 186] IN ARCS: [174 -(T,3,0)-> 176] [175 -(T,3,0)-> 176] Node num: 12 (insn 177 176 178 11 (set (reg:V4SI 334) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) OUT ARCS: [177 -(T,3,0)-> 179] IN ARCS: [164 -(T,3,0)-> 177] Node num: 13 (insn 178 177 179 11 (set (reg:V4SI 335) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) OUT ARCS: [178 -(T,3,0)-> 179] IN ARCS: [169 -(T,2,0)-> 178] Node num: 14 (insn 179 178 180 11 (set (reg:V4SI 306 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 334) (reg:V4SI 335))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 335) (expr_list:REG_DEAD (reg:V4SI 334) (nil)))) OUT ARCS: [179 -(T,3,0)-> 188] IN ARCS: [177 -(T,3,0)-> 179] [178 -(T,3,0)-> 179] Node num: 15 (insn 180 179 181 11 (set (reg:V4SI 336) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 292 [ vect_var_.37 ]) (nil))) OUT ARCS: [180 -(T,3,0)-> 182] IN ARCS: [164 -(T,3,0)-> 180] Node num: 16 (insn 181 180 182 11 (set (reg:V4SI 337) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 328) (nil))) OUT ARCS: [181 -(T,3,0)-> 182] IN ARCS: [169 -(T,2,0)-> 181] Node num: 17 (insn 182 181 183 11 (set (reg:V4SI 307 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 336) (reg:V4SI 337))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 337) (expr_list:REG_DEAD (reg:V4SI 336) (nil)))) OUT ARCS: [182 -(T,3,0)-> 190] IN ARCS: [180 -(T,3,0)-> 182] [181 -(T,3,0)-> 182] Node num: 18 (insn 184 183 185 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 304 [ vect_var_.45 ]) (reg:V4SI 304 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 304 [ vect_var_.45 ]) (nil))) OUT ARCS: [184 -(T,9,0)-> 186] IN ARCS: [190 -(T,9,1)-> 184] [173 -(T,3,0)-> 184] Node num: 19 (insn 186 185 187 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 305 [ vect_var_.45 ]) (reg:V4SI 305 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 305 [ vect_var_.45 ]) (nil))) OUT ARCS: [186 -(T,9,0)-> 188] IN ARCS: [176 -(T,3,0)-> 186] [184 -(T,9,0)-> 186] Node num: 20 (insn 188 187 189 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 306 [ vect_var_.45 ]) (reg:V4SI 306 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 306 [ vect_var_.45 ]) (nil))) OUT ARCS: [188 -(T,9,0)-> 190] IN ARCS: [179 -(T,3,0)-> 188] [186 -(T,9,0)-> 188] Node num: 21 (insn 190 189 191 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 307 [ vect_var_.45 ]) (reg:V4SI 307 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 307 [ vect_var_.45 ]) (nil))) OUT ARCS: [190 -(T,9,1)-> 184] IN ARCS: [182 -(T,3,0)-> 190] [188 -(T,9,0)-> 190] Node num: 22 (insn 191 190 286 11 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (reg/f:SI 239 [ vect_p.38 ]) (const_int 32 [0x20]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) OUT ARCS: [191 -(T,1,1)-> 296] [191 -(T,1,1)-> 191] IN ARCS: [191 -(T,1,1)-> 191] Node num: 23 (insn 286 191 287 11 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 354 [ bnd.28 ]) (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff]))) ]) 6 {addsi3_compare0} (nil)) OUT ARCS: [286 -(T,1,1)-> 286] [286 -(T,1,1)-> 286] [286 -(T,2,0)-> 287] IN ARCS: [286 -(T,1,1)-> 286] [286 -(T,1,1)-> 286] [287 -(A,0,1)-> 286] Node num: 24 (jump_insn 287 286 196 11 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 193) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 193) OUT ARCS: [287 -(A,0,1)-> 286] IN ARCS: [286 -(T,2,0)-> 287] (null) 0 (file, line) SMS single-bb-loop SMS doloop SMS built-ddg 25 SMS num-loads 3 SMS num-stores 0 Order params node 0, ASAP: 0, ALAP: 1, HEIGHT: 36 node 1, ASAP: 0, ALAP: 1, HEIGHT: 36 node 2, ASAP: 0, ALAP: 19, HEIGHT: 18 node 3, ASAP: 0, ALAP: 0, HEIGHT: 37 node 4, ASAP: 2, ALAP: 2, HEIGHT: 35 node 5, ASAP: 4, ALAP: 20, HEIGHT: 17 node 6, ASAP: 3, ALAP: 4, HEIGHT: 33 node 7, ASAP: 4, ALAP: 4, HEIGHT: 33 node 8, ASAP: 7, ALAP: 7, HEIGHT: 30 node 9, ASAP: 3, ALAP: 13, HEIGHT: 24 node 10, ASAP: 4, ALAP: 13, HEIGHT: 24 node 11, ASAP: 7, ALAP: 16, HEIGHT: 21 node 12, ASAP: 3, ALAP: 22, HEIGHT: 15 node 13, ASAP: 6, ALAP: 22, HEIGHT: 15 node 14, ASAP: 9, ALAP: 25, HEIGHT: 12 node 15, ASAP: 3, ALAP: 31, HEIGHT: 6 node 16, ASAP: 6, ALAP: 31, HEIGHT: 6 node 17, ASAP: 9, ALAP: 34, HEIGHT: 3 node 18, ASAP: 10, ALAP: 10, HEIGHT: 27 node 19, ASAP: 19, ALAP: 19, HEIGHT: 18 node 20, ASAP: 28, ALAP: 28, HEIGHT: 9 node 21, ASAP: 37, ALAP: 37, HEIGHT: 0 node 22, ASAP: 0, ALAP: 37, HEIGHT: 0 node 23, ASAP: 0, ALAP: 35, HEIGHT: 2 node 24, ASAP: 2, ALAP: 37, HEIGHT: 0 ;; Number of SCC nodes - 5 SCC number: 0 insn num 18 (insn 184 183 185 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 304 [ vect_var_.45 ]) (reg:V4SI 304 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 304 [ vect_var_.45 ]) (nil))) insn num 19 (insn 186 185 187 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 305 [ vect_var_.45 ]) (reg:V4SI 305 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 305 [ vect_var_.45 ]) (nil))) insn num 20 (insn 188 187 189 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 306 [ vect_var_.45 ]) (reg:V4SI 306 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 306 [ vect_var_.45 ]) (nil))) insn num 21 (insn 190 189 191 11 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 307 [ vect_var_.45 ]) (reg:V4SI 307 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 307 [ vect_var_.45 ]) (nil))) SCC number: 1 insn num 3 (insn 296 164 165 11 (set (reg/f:SI 329) (reg/f:SI 239 [ vect_p.38 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 639 {*arm_movsi_vfp} (nil)) insn num 4 (insn 165 296 169 11 (set (reg:V8HI 327) (unspec:V8HI [ (mem:V8HI (post_inc:SI (reg/f:SI 329)) [2 MEM[(int16_t *)vect_p.38_128]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_INC (reg/f:SI 329) (nil))) insn num 5 (insn 169 165 171 11 (set (reg:V8HI 328) (unspec:V8HI [ (mem:V8HI (reg/f:SI 329) [2 MEM[(int16_t *)D.7209_27]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_DEAD (reg/f:SI 329) (nil))) SCC number: 2 insn num 23 (insn 286 191 287 11 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 354 [ bnd.28 ]) (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff]))) ]) 6 {addsi3_compare0} (nil)) insn num 24 (jump_insn 287 286 196 11 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 193) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 193) SCC number: 3 insn num 22 (insn 191 190 286 11 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (reg/f:SI 239 [ vect_p.38 ]) (const_int 32 [0x20]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) SCC number: 4 insn num 0 (insn 161 160 163 11 (set (reg:V16QI 290 [ vect_var_.35 ]) (mem:V16QI (post_inc:SI (reg:SI 267 [ ivtmp.89 ])) [0 MEM[base: D.7206_62, offset: 0B]+0 S16 A128])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 757 {*neon_movv16qi} (expr_list:REG_INC (reg:SI 267 [ ivtmp.89 ]) (nil))) SMS final nodes order: 21 20 19 18 14 17 8 11 13 16 7 10 5 4 3 24 23 22 6 9 12 15 1 0 2 SMS iis 36 36 72 (rec_mii, mii, maxii) Starting with ii=36 Trying to schedule node 21 INSN = 190 in (37 .. 73) step 1 must_precede: must_follow: Scheduled w/o split in 37 Analyzing dependencies for node 20 (INSN 188); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 28 37 [188 -(T,9,0)-> 190] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 28 2147483647 (max, max, min, min) -7 28 final window Trying to schedule node 20 INSN = 188 in (28 .. -8) step -1 must_precede: must_follow: Scheduled w/o split in 28 Analyzing dependencies for node 19 (INSN 186); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 19 28 [186 -(T,9,0)-> 188] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 19 2147483647 (max, max, min, min) -16 19 final window Trying to schedule node 19 INSN = 186 in (19 .. -17) step -1 must_precede: must_follow: Scheduled w/o split in 19 Analyzing dependencies for node 18 (INSN 184); ii = 36 start early start late start end time =========== =========== =========== =========== ===== 10 2147483647 37 [190 -(T,9,1)-> 184] -2147483648 10 19 [184 -(T,9,0)-> 186] ----------- ----------- ----------- ----------- ----- -2147483648 10 10 2147483647 (max, max, min, min) 10 10 final window Trying to schedule node 18 INSN = 184 in (10 .. 9) step -1 must_precede: must_follow: Scheduled w/o split in 10 Analyzing dependencies for node 14 (INSN 179); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 25 28 [179 -(T,3,0)-> 188] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 25 2147483647 (max, max, min, min) -10 25 final window Trying to schedule node 14 INSN = 179 in (25 .. -11) step -1 must_precede: must_follow: Scheduled w/o split in 25 Analyzing dependencies for node 17 (INSN 182); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 34 37 [182 -(T,3,0)-> 190] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 34 2147483647 (max, max, min, min) -1 34 final window Trying to schedule node 17 INSN = 182 in (34 .. -2) step -1 must_precede: must_follow: Scheduled w/o split in 34 Analyzing dependencies for node 8 (INSN 173); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 7 10 [173 -(T,3,0)-> 184] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 7 2147483647 (max, max, min, min) -28 7 final window Trying to schedule node 8 INSN = 173 in (7 .. -29) step -1 must_precede: must_follow: Scheduled w/o split in 7 Analyzing dependencies for node 11 (INSN 176); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 16 19 [176 -(T,3,0)-> 186] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 16 2147483647 (max, max, min, min) -19 16 final window Trying to schedule node 11 INSN = 176 in (16 .. -20) step -1 must_precede: must_follow: Scheduled w/o split in 16 Analyzing dependencies for node 13 (INSN 178); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 22 25 [178 -(T,3,0)-> 179] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 22 2147483647 (max, max, min, min) -13 22 final window Trying to schedule node 13 INSN = 178 in (22 .. -14) step -1 must_precede: must_follow: Scheduled w/o split in 22 Analyzing dependencies for node 16 (INSN 181); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 31 34 [181 -(T,3,0)-> 182] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 31 2147483647 (max, max, min, min) -4 31 final window Trying to schedule node 16 INSN = 181 in (31 .. -5) step -1 must_precede: must_follow: Scheduled w/o split in 31 Analyzing dependencies for node 7 (INSN 172); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 4 7 [172 -(T,3,0)-> 173] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 4 2147483647 (max, max, min, min) -31 4 final window Trying to schedule node 7 INSN = 172 in (4 .. -32) step -1 must_precede: must_follow: Scheduled w/o split in 4 Analyzing dependencies for node 10 (INSN 175); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 13 16 [175 -(T,3,0)-> 176] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 13 2147483647 (max, max, min, min) -22 13 final window Trying to schedule node 10 INSN = 175 in (13 .. -23) step -1 must_precede: must_follow: Scheduled w/o split in 13 Analyzing dependencies for node 5 (INSN 169); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 29 31 [169 -(T,2,0)-> 181] -2147483648 20 22 [169 -(T,2,0)-> 178] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 20 2147483647 (max, max, min, min) -15 20 final window Trying to schedule node 5 INSN = 169 in (20 .. -16) step -1 must_precede: must_follow: Scheduled w/o split in 20 Analyzing dependencies for node 4 (INSN 165); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 11 13 [165 -(T,2,0)-> 175] -2147483648 2 4 [165 -(T,2,0)-> 172] -15 18 20 [165 -(T,2,0)-> 169] ----------- ----------- ----------- ----------- ----- -15 -2147483648 2 2147483647 (max, max, min, min) -15 2 final window Trying to schedule node 4 INSN = 165 in (2 .. -16) step -1 must_precede: must_follow: Scheduled w/o split in 2 Analyzing dependencies for node 3 (INSN 296); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -16 2147483647 20 [169 -(A,0,1)-> 296] -2147483648 18 20 [296 -(T,2,0)-> 169] -2147483648 0 2 [296 -(T,2,0)-> 165] ----------- ----------- ----------- ----------- ----- -2147483648 -16 0 2147483647 (max, max, min, min) -16 0 final window Trying to schedule node 3 INSN = 296 in (0 .. -17) step -1 must_precede: 5 must_follow: Scheduled w/o split in 0 Trying to schedule node 24 INSN = 287 in (2 .. 38) step 1 must_precede: must_follow: Scheduled w/o split in 2 Analyzing dependencies for node 23 (INSN 286); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -34 2147483647 2 [287 -(A,0,1)-> 286] -2147483648 0 2 [286 -(T,2,0)-> 287] ----------- ----------- ----------- ----------- ----- -2147483648 -34 0 2147483647 (max, max, min, min) -34 0 final window Trying to schedule node 23 INSN = 286 in (0 .. -35) step -1 must_precede: 24 must_follow: Scheduled w/o split in 0 Analyzing dependencies for node 22 (INSN 191); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 35 0 [191 -(T,1,1)-> 296] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 35 2147483647 (max, max, min, min) 0 35 final window Trying to schedule node 22 INSN = 191 in (35 .. -1) step -1 must_precede: must_follow: Scheduled w/o split in 35 Analyzing dependencies for node 6 (INSN 171); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 4 7 [171 -(T,3,0)-> 173] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 4 2147483647 (max, max, min, min) -31 4 final window Trying to schedule node 6 INSN = 171 in (4 .. -32) step -1 must_precede: must_follow: Scheduled w/o split in 3 Analyzing dependencies for node 9 (INSN 174); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 13 16 [174 -(T,3,0)-> 176] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 13 2147483647 (max, max, min, min) -22 13 final window Trying to schedule node 9 INSN = 174 in (13 .. -23) step -1 must_precede: must_follow: Scheduled w/o split in 12 Analyzing dependencies for node 12 (INSN 177); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 22 25 [177 -(T,3,0)-> 179] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 22 2147483647 (max, max, min, min) -13 22 final window Trying to schedule node 12 INSN = 177 in (22 .. -14) step -1 must_precede: must_follow: Scheduled w/o split in 21 Analyzing dependencies for node 15 (INSN 180); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 31 34 [180 -(T,3,0)-> 182] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 31 2147483647 (max, max, min, min) -4 31 final window Trying to schedule node 15 INSN = 180 in (31 .. -5) step -1 must_precede: must_follow: Scheduled w/o split in 30 Analyzing dependencies for node 1 (INSN 163); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 9 12 [163 -(T,3,0)-> 174] -2147483648 0 3 [163 -(T,3,0)-> 171] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 0 2147483647 (max, max, min, min) -35 0 final window Trying to schedule node 1 INSN = 163 in (0 .. -36) step -1 must_precede: must_follow: Scheduled w/o split in -1 Analyzing dependencies for node 0 (INSN 161); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2147483648 -1 -1 [161 -(T,0,0)-> 163] ----------- ----------- ----------- ----------- ----- -2147483648 -2147483648 -1 2147483647 (max, max, min, min) -36 -1 final window Trying to schedule node 0 INSN = 161 in (-1 .. -37) step -1 must_precede: must_follow: 1 Scheduled w/o split in -2 Analyzing dependencies for node 2 (INSN 164); ii = 36 start early start late start end time =========== =========== =========== =========== ===== -2 2147483647 -2 [161 -(T,0,0)-> 164] -2147483648 27 30 [164 -(T,3,0)-> 180] -2147483648 18 21 [164 -(T,3,0)-> 177] ----------- ----------- ----------- ----------- ----- -2147483648 -2 18 2147483647 (max, max, min, min) -2 18 final window Trying to schedule node 2 INSN = 164 in (18 .. -3) step -1 must_precede: 0 must_follow: Scheduled w/o split in 18 SMS SC already optimized. SMS schedule branch at cycle ii-1 crr_insn->node=23 (insn id 286), crr_insn->cycle=33, min_cycle=31 crr_insn->node=3 (insn id 296), crr_insn->cycle=33, min_cycle=31 crr_insn->node=21 (insn id 190), crr_insn->cycle=70, min_cycle=31 crr_insn->node=4 (insn id 165), crr_insn->cycle=35, min_cycle=31 crr_insn->node=24 (insn id 287), crr_insn->cycle=35, min_cycle=31 (branch) crr_insn->node=6 (insn id 171), crr_insn->cycle=36, min_cycle=31 crr_insn->node=7 (insn id 172), crr_insn->cycle=37, min_cycle=31 crr_insn->node=8 (insn id 173), crr_insn->cycle=40, min_cycle=31 crr_insn->node=18 (insn id 184), crr_insn->cycle=43, min_cycle=31 crr_insn->node=9 (insn id 174), crr_insn->cycle=45, min_cycle=31 crr_insn->node=10 (insn id 175), crr_insn->cycle=46, min_cycle=31 crr_insn->node=11 (insn id 176), crr_insn->cycle=49, min_cycle=31 crr_insn->node=2 (insn id 164), crr_insn->cycle=51, min_cycle=31 crr_insn->node=19 (insn id 186), crr_insn->cycle=52, min_cycle=31 crr_insn->node=5 (insn id 169), crr_insn->cycle=53, min_cycle=31 crr_insn->node=12 (insn id 177), crr_insn->cycle=54, min_cycle=31 crr_insn->node=13 (insn id 178), crr_insn->cycle=55, min_cycle=31 crr_insn->node=14 (insn id 179), crr_insn->cycle=58, min_cycle=31 crr_insn->node=20 (insn id 188), crr_insn->cycle=61, min_cycle=31 crr_insn->node=15 (insn id 180), crr_insn->cycle=63, min_cycle=31 crr_insn->node=16 (insn id 181), crr_insn->cycle=64, min_cycle=31 crr_insn->node=0 (insn id 161), crr_insn->cycle=31, min_cycle=31 crr_insn->node=17 (insn id 182), crr_insn->cycle=67, min_cycle=31 crr_insn->node=1 (insn id 163), crr_insn->cycle=32, min_cycle=31 crr_insn->node=22 (insn id 191), crr_insn->cycle=68, min_cycle=31 Loop 2 (parent 0, header bb11, depth 1) ref. regnos: 24 239 267 290 291 292 304 305 306 307 312 327 328 329 330 331 332 333 334 335 336 337 354 live regnos: 11 13 14 24 25 26 227 228 229 239 267 274 276 277 278 290 291 292 304 305 306 307 312 327 328 329 330 331 332 333 334 335 336 337 354 Pressure:VFP_REGS=28 64 GENERAL_REGS=12 14 changing bb of uid 342 unscanned insn verify found no changes in insn with uid = 287. Edge 11->11 redirected to 29 (null):0 SMS succeeded 36 2 (with ii, sc) [ROW 0 ]: 171, [ROW 1 ]: 172, [ROW 2 ]: [ROW 3 ]: [ROW 4 ]: 173, [ROW 5 ]: [ROW 6 ]: [ROW 7 ]: 184, [ROW 8 ]: [ROW 9 ]: 174, [ROW 10 ]: 175, [ROW 11 ]: [ROW 12 ]: [ROW 13 ]: 176, [ROW 14 ]: [ROW 15 ]: 164, [ROW 16 ]: 186, [ROW 17 ]: 169, [ROW 18 ]: 177, [ROW 19 ]: 178, [ROW 20 ]: [ROW 21 ]: [ROW 22 ]: 179, [ROW 23 ]: [ROW 24 ]: [ROW 25 ]: 188, [ROW 26 ]: [ROW 27 ]: 180, [ROW 28 ]: 181, [ROW 29 ]: [ROW 30 ]: [ROW 31 ]: 161, 182, [ROW 32 ]: 163, 191, [ROW 33 ]: 286, 296, [ROW 34 ]: 190, [ROW 35 ]: 165, 287 (branch), deleting insn with uid = 344. changing bb of uid 370 unscanned insn changing bb of uid 345 unscanned insn scanning new insn with uid = 345. changing bb of uid 346 unscanned insn scanning new insn with uid = 346. changing bb of uid 347 unscanned insn scanning new insn with uid = 347. changing bb of uid 348 unscanned insn scanning new insn with uid = 348. changing bb of uid 349 unscanned insn scanning new insn with uid = 349. changing bb of uid 350 unscanned insn scanning new insn with uid = 350. changing bb of uid 351 unscanned insn scanning new insn with uid = 351. changing bb of uid 352 unscanned insn scanning new insn with uid = 352. changing bb of uid 353 unscanned insn scanning new insn with uid = 353. changing bb of uid 354 unscanned insn scanning new insn with uid = 354. changing bb of uid 355 unscanned insn scanning new insn with uid = 355. changing bb of uid 356 unscanned insn scanning new insn with uid = 356. changing bb of uid 357 unscanned insn scanning new insn with uid = 357. changing bb of uid 358 unscanned insn scanning new insn with uid = 358. changing bb of uid 359 unscanned insn scanning new insn with uid = 359. changing bb of uid 360 unscanned insn scanning new insn with uid = 360. changing bb of uid 361 unscanned insn scanning new insn with uid = 361. changing bb of uid 362 unscanned insn scanning new insn with uid = 362. changing bb of uid 363 unscanned insn scanning new insn with uid = 363. changing bb of uid 364 unscanned insn scanning new insn with uid = 364. changing bb of uid 365 unscanned insn scanning new insn with uid = 365. changing bb of uid 366 unscanned insn scanning new insn with uid = 366. changing bb of uid 367 unscanned insn scanning new insn with uid = 367. changing bb of uid 368 unscanned insn scanning new insn with uid = 368. changing bb of uid 369 unscanned insn scanning new insn with uid = 369. deleting insn with uid = 371. changing bb of uid 372 unscanned insn verify found no changes in insn with uid = 369. Edge 30->29 redirected to 31 Redirecting fallthru edge 31->11 to 30 Redirecting fallthru edge 31->30 to 11 Redirecting fallthru edge 10->11 to 30 changing bb of uid 374 unscanned insn Redirecting fallthru edge 10->30 to 32 scanning new insn with uid = 375. scanning new insn with uid = 376. Redirecting fallthru edge 31->11 to 30 changing bb of uid 377 unscanned insn verify found no changes in insn with uid = 376. Edge 32->11 redirected to 33 changing bb of uid 379 unscanned insn Redirecting fallthru edge 32->30 to 34 Node = 0; INSN = 161 asap = 0: time = 31: stage = 0: Node = 1; INSN = 163 asap = 0: time = 32: stage = 0: Node = 2; INSN = 164 asap = 0: time = 51: stage = 1: Node = 3; INSN = 296 asap = 0: time = 33: stage = 0: Node = 4; INSN = 165 asap = 2: time = 35: stage = 0: Node = 5; INSN = 169 asap = 4: time = 53: stage = 1: Node = 6; INSN = 171 asap = 3: time = 36: stage = 1: Node = 7; INSN = 172 asap = 4: time = 37: stage = 1: Node = 8; INSN = 173 asap = 7: time = 40: stage = 1: Node = 9; INSN = 174 asap = 3: time = 45: stage = 1: Node = 10; INSN = 175 asap = 4: time = 46: stage = 1: Node = 11; INSN = 176 asap = 7: time = 49: stage = 1: Node = 12; INSN = 177 asap = 3: time = 54: stage = 1: Node = 13; INSN = 178 asap = 6: time = 55: stage = 1: Node = 14; INSN = 179 asap = 9: time = 58: stage = 1: Node = 15; INSN = 180 asap = 3: time = 63: stage = 1: Node = 16; INSN = 181 asap = 6: time = 64: stage = 1: Node = 17; INSN = 182 asap = 9: time = 67: stage = 1: Node = 18; INSN = 184 asap = 10: time = 43: stage = 1: Node = 19; INSN = 186 asap = 19: time = 52: stage = 1: Node = 20; INSN = 188 asap = 28: time = 61: stage = 1: Node = 21; INSN = 190 asap = 37: time = 70: stage = 1: Node = 22; INSN = 191 asap = 0: time = 68: stage = 1: Node = 23; INSN = 286 asap = 0: time = 33: stage = 0: Node = 24; INSN = 287 asap = 2: time = 35: stage = 0: deleting insn with uid = 381. deleting insn with uid = 383. deleting insn with uid = 385. deleting insn with uid = 387. changing bb of uid 389 unscanned insn Redirecting fallthru edge 33->11 to 35 scanning new insn with uid = 380. scanning new insn with uid = 382. scanning new insn with uid = 384. scanning new insn with uid = 386. scanning new insn with uid = 388. deleting insn with uid = 390. deleting insn with uid = 392. deleting insn with uid = 394. deleting insn with uid = 396. deleting insn with uid = 398. deleting insn with uid = 400. deleting insn with uid = 402. deleting insn with uid = 404. deleting insn with uid = 406. deleting insn with uid = 408. deleting insn with uid = 410. deleting insn with uid = 412. deleting insn with uid = 414. deleting insn with uid = 416. deleting insn with uid = 418. deleting insn with uid = 420. deleting insn with uid = 422. deleting insn with uid = 424. deleting insn with uid = 426. changing bb of uid 428 unscanned insn Redirecting fallthru edge 11->12 to 36 scanning new insn with uid = 391. scanning new insn with uid = 393. scanning new insn with uid = 395. scanning new insn with uid = 397. scanning new insn with uid = 399. scanning new insn with uid = 401. scanning new insn with uid = 403. scanning new insn with uid = 405. scanning new insn with uid = 407. scanning new insn with uid = 409. scanning new insn with uid = 411. scanning new insn with uid = 413. scanning new insn with uid = 415. scanning new insn with uid = 417. scanning new insn with uid = 419. scanning new insn with uid = 421. scanning new insn with uid = 423. scanning new insn with uid = 425. scanning new insn with uid = 427. changing bb of uid 429 unscanned insn scanning new insn with uid = 430. scanning new insn with uid = 433. scanning new insn with uid = 436. scanning new insn with uid = 438. scanning new insn with uid = 441. scanning new insn with uid = 443. scanning new insn with uid = 445. rescanning insn with uid = 317. deleting insn with uid = 317. scanning new insn with uid = 447. rescanning insn with uid = 369. deleting insn with uid = 369. scanning new insn with uid = 449. Reordered sequence: 2 bb 2 [900] 3 bb 3 [819] 4 bb 4 [819] 5 bb 5 [9100] 6 bb 6 [819] 7 compensation [0] 8 bb 8 [0] 9 bb 9 [819] 10 bb 10 [819] 11 bb 32 [819] 12 compensation [164] 13 bb 33 [655] 14 bb 35 [655] 15 bb 11 [7280] 16 bb 36 [655] 17 bb 29 [6625] 18 bb 12 [819] 19 bb 13 [819] 20 bb 14 [819] 21 bb 15 [0] 22 bb 16 [819] 23 bb 24 [819] 24 compensation [164] 25 bb 25 [655] 26 bb 27 [655] 27 bb 20 [7280] 28 bb 28 [655] 29 bb 21 [6625] 30 bb 18 [81] 31 bb 19 [900] 32 duplicate of 20 [1820] 33 duplicate of 21 [1656] 34 duplicate of 11 [1820] 35 duplicate of 29 [1656] starting the processing of deferred insns ending the processing of deferred insns (note 104 0 113 NOTE_INSN_DELETED) (note 113 104 105 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 105 113 116 2 NOTE_INSN_FUNCTION_BEG) (insn 116 105 117 2 (set (reg/f:SI 318) (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:19 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]) (nil))) (insn 117 116 120 2 (set (reg/v/f:SI 227 [ pix1 ]) (mem/v/f/c/i:SI (reg/f:SI 318) [4 vol_pix1+0 S4 A32])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:19 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (mem/v/f/c/i:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]) [4 vol_pix1+0 S4 A32]) (nil))) (insn 120 117 123 2 (set (reg/v/f:SI 228 [ pix2 ]) (mem/v/f/c/i:SI (plus:SI (reg/f:SI 318) (const_int 4 [0x4])) [4 vol_pix2+0 S4 A32])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:20 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (mem/v/f/c/i:SI (const:SI (plus:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]) (const_int 4 [0x4]))) [4 vol_pix2+0 S4 A32]) (nil))) (insn 123 120 124 2 (set (reg/v:SI 229 [ size ]) (mem/v/c/i:SI (plus:SI (reg/f:SI 318) (const_int 8 [0x8])) [3 vol_size+0 S4 A32])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:21 639 {*arm_movsi_vfp} (expr_list:REG_DEAD (reg/f:SI 318) (expr_list:REG_EQUAL (mem/v/c/i:SI (const:SI (plus:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]) (const_int 8 [0x8]))) [3 vol_size+0 S4 A32]) (nil)))) (insn 124 123 125 2 (set (reg:CC 24 cc) (compare:CC (reg/v:SI 229 [ size ]) (const_int 0 [0]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 211 {*arm_cmpsi_insn} (nil)) (jump_insn 125 124 126 2 (set (pc) (if_then_else (le (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 235) (pc))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 900 [0x384]) (nil))) -> 235) (note 126 125 128 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 128 126 129 3 (set (reg:SI 321) (neg:SI (reg/v/f:SI 227 [ pix1 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 142 {*arm_negsi2} (nil)) (insn 129 128 130 3 (set (reg:SI 322) (and:SI (reg:SI 321) (const_int 15 [0xf]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 75 {*arm_andsi3_insn} (expr_list:REG_DEAD (reg:SI 321) (nil))) (insn 130 129 131 3 (parallel [ (set (reg:SI 262 [ prolog_loop_niters.24 ]) (umin:SI (reg:SI 322) (reg/v:SI 229 [ size ]))) (clobber (reg:CC 24 cc)) ]) 115 {*arm_uminsi3} (expr_list:REG_DEAD (reg:SI 322) (expr_list:REG_UNUSED (reg:CC 24 cc) (nil)))) (insn 131 130 132 3 (set (reg:CC 24 cc) (compare:CC (reg:SI 262 [ prolog_loop_niters.24 ]) (const_int 0 [0]))) 211 {*arm_cmpsi_insn} (nil)) (jump_insn 132 131 133 3 (set (pc) (if_then_else (eq (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 240) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 0 [0]) (nil))) -> 240) (note 133 132 134 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 134 133 106 4 (set (reg:SI 279 [ ivtmp.75 ]) (plus:SI (reg/v/f:SI 228 [ pix2 ]) (const_int -2 [0xfffffffffffffffe]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) (insn 106 134 107 4 (set (reg/v:SI 278 [ i ]) (const_int 0 [0])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 639 {*arm_movsi_vfp} (nil)) (insn 107 106 291 4 (set (reg/v:SI 277 [ score ]) (reg/v:SI 278 [ i ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (insn 291 107 143 4 (set (reg:SI 355 [ prolog_loop_niters.24 ]) (reg:SI 262 [ prolog_loop_niters.24 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 639 {*arm_movsi_vfp} (nil)) (code_label 143 291 135 5 4 "" [1 uses]) (note 135 143 137 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (insn 137 135 138 5 (set (reg:SI 323 [ MEM[base: pix1_3, index: D.7191_21, offset: 0B] ]) (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg/v:SI 278 [ i ])) [0 MEM[base: pix1_3, index: D.7191_21, offset: 0B]+0 S1 A8]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 175 {*arm_extendqisi_v6} (nil)) (insn 138 137 139 5 (set (reg:SI 324 [ MEM[base: D.7192_23, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 279 [ ivtmp.75 ])) [2 MEM[base: D.7192_23, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 279 [ ivtmp.75 ]) (nil))) (insn 139 138 140 5 (set (reg:SI 270 [ D.7092 ]) (minus:SI (reg:SI 323 [ MEM[base: pix1_3, index: D.7191_21, offset: 0B] ]) (reg:SI 324 [ MEM[base: D.7192_23, offset: 0B] ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 31 {*arm_subsi3_insn} (expr_list:REG_DEAD (reg:SI 324 [ MEM[base: D.7192_23, offset: 0B] ]) (expr_list:REG_DEAD (reg:SI 323 [ MEM[base: pix1_3, index: D.7191_21, offset: 0B] ]) (nil)))) (note 140 139 141 5 NOTE_INSN_DELETED) (insn 141 140 142 5 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 270 [ D.7092 ]) (reg:SI 270 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 270 [ D.7092 ]) (nil))) (insn 142 141 289 5 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) (insn 289 142 290 5 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 355 [ prolog_loop_niters.24 ]) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 355 [ prolog_loop_niters.24 ]) (plus:SI (reg:SI 355 [ prolog_loop_niters.24 ]) (const_int -1 [0xffffffffffffffff]))) ]) 6 {addsi3_compare0} (nil)) (jump_insn 290 289 146 5 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 143) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 143) (note 146 290 147 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (insn 147 146 148 6 (set (reg:CC 24 cc) (compare:CC (reg/v:SI 229 [ size ]) (reg:SI 262 [ prolog_loop_niters.24 ]))) 211 {*arm_cmpsi_insn} (nil)) (jump_insn 148 147 429 6 (set (pc) (if_then_else (ne (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 149) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 10000 [0x2710]) (nil))) -> 149) (note 429 148 430 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (jump_insn 430 429 431 7 (set (pc) (label_ref 225)) -1 (nil) -> 225) (barrier 431 430 240) (code_label 240 431 239 8 11 "" [1 uses]) (note 239 240 108 8 [bb 8] NOTE_INSN_BASIC_BLOCK) (insn 108 239 109 8 (set (reg/v:SI 278 [ i ]) (reg:SI 262 [ prolog_loop_niters.24 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (insn 109 108 149 8 (set (reg/v:SI 277 [ score ]) (reg:SI 262 [ prolog_loop_niters.24 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:23 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (code_label 149 109 150 9 3 "" [1 uses]) (note 150 149 151 9 [bb 9] NOTE_INSN_BASIC_BLOCK) (insn 151 150 152 9 (set (reg:SI 274 [ niters.27 ]) (minus:SI (reg/v:SI 229 [ size ]) (reg:SI 262 [ prolog_loop_niters.24 ]))) 31 {*arm_subsi3_insn} (nil)) (insn 152 151 153 9 (set (reg:SI 275 [ bnd.28 ]) (lshiftrt:SI (reg:SI 274 [ niters.27 ]) (const_int 4 [0x4]))) 125 {*arm_shiftsi3} (nil)) (note 153 152 154 9 NOTE_INSN_DELETED) (insn 154 153 155 9 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (ashift:SI (reg:SI 275 [ bnd.28 ]) (const_int 4 [0x4])) (const_int 0 [0]))) (set (reg:SI 276 [ ratio_mult_vf.29 ]) (ashift:SI (reg:SI 275 [ bnd.28 ]) (const_int 4 [0x4]))) ]) 126 {*shiftsi3_compare0} (nil)) (jump_insn 155 154 156 9 (set (pc) (if_then_else (eq (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 205) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 0 [0]) (nil))) -> 205) (note 156 155 157 10 [bb 10] NOTE_INSN_BASIC_BLOCK) (note 157 156 158 10 NOTE_INSN_DELETED) (insn 158 157 159 10 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (mult:SI (reg:SI 262 [ prolog_loop_niters.24 ]) (const_int 2 [0x2])) (reg/v/f:SI 228 [ pix2 ]))) 264 {*arith_shiftsi} (nil)) (insn 159 158 111 10 (set (reg:SI 267 [ ivtmp.89 ]) (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg:SI 262 [ prolog_loop_niters.24 ]))) 4 {*arm_addsi3} (expr_list:REG_DEAD (reg:SI 262 [ prolog_loop_niters.24 ]) (nil))) (insn 111 159 288 10 (set (reg:V4SI 312 [ vect_var_.47 ]) (const_vector:V4SI [ (const_int 0 [0]) (const_int 0 [0]) (const_int 0 [0]) (const_int 0 [0]) ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:23 759 {*neon_movv4si} (nil)) (insn 288 111 374 10 (set (reg:SI 354 [ bnd.28 ]) (reg:SI 275 [ bnd.28 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:23 639 {*arm_movsi_vfp} (expr_list:REG_DEAD (reg:SI 275 [ bnd.28 ]) (nil))) (note 374 288 375 11 [bb 11] NOTE_INSN_BASIC_BLOCK) (insn 375 374 376 11 (set (reg:CC 24 cc) (compare:CC (reg:SI 354 [ bnd.28 ]) (const_int 2 [0x2]))) -1 (nil)) (jump_insn 376 375 379 11 (set (pc) (if_then_else (gt (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 378) (pc))) 223 {*arm_cond_branch} (nil) -> 378) (note 379 376 433 12 [bb 12] NOTE_INSN_BASIC_BLOCK) (jump_insn 433 379 434 12 (set (pc) (label_ref 432)) -1 (nil) -> 432) (barrier 434 433 378) (code_label 378 434 377 13 26 "" [1 uses]) (note 377 378 389 13 [bb 13] NOTE_INSN_BASIC_BLOCK) (note 389 377 380 14 [bb 14] NOTE_INSN_BASIC_BLOCK) (insn 380 389 382 14 (set (reg:SI 354 [ bnd.28 ]) (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff]))) -1 (nil)) (insn 382 380 384 14 (set (reg:V16QI 290 [ vect_var_.35 ]) (mem:V16QI (post_inc:SI (reg:SI 267 [ ivtmp.89 ])) [0 MEM[base: D.7206_62, offset: 0B]+0 S16 A128])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 757 {*neon_movv16qi} (expr_list:REG_INC (reg:SI 267 [ ivtmp.89 ]) (nil))) (insn 384 382 386 14 (set (reg:V8HI 291 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1721 {neon_vec_unpacks_lo_v16qi} (nil)) (insn 386 384 388 14 (set (reg/f:SI 329) (reg/f:SI 239 [ vect_p.38 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 639 {*arm_movsi_vfp} (nil)) (insn 388 386 193 14 (set (reg:V8HI 327) (unspec:V8HI [ (mem:V8HI (post_inc:SI (reg/f:SI 329)) [2 MEM[(int16_t *)vect_p.38_128]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_INC (reg/f:SI 329) (nil))) (code_label 193 388 160 15 7 "" [1 uses]) (note 160 193 171 15 [bb 15] NOTE_INSN_BASIC_BLOCK) (insn 171 160 172 15 (set (reg:V4SI 330) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 172 171 173 15 (set (reg:V4SI 331) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 173 172 183 15 (set (reg:V4SI 304 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 330) (reg:V4SI 331))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 331) (expr_list:REG_DEAD (reg:V4SI 330) (nil)))) (note 183 173 184 15 NOTE_INSN_DELETED) (insn 184 183 174 15 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 304 [ vect_var_.45 ]) (reg:V4SI 304 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 304 [ vect_var_.45 ]) (nil))) (insn 174 184 175 15 (set (reg:V4SI 332) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 291 [ vect_var_.37 ]) (nil))) (insn 175 174 176 15 (set (reg:V4SI 333) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 327) (nil))) (insn 176 175 164 15 (set (reg:V4SI 305 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 332) (reg:V4SI 333))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 333) (expr_list:REG_DEAD (reg:V4SI 332) (nil)))) (insn 164 176 185 15 (set (reg:V8HI 292 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 8 [0x8]) (const_int 9 [0x9]) (const_int 10 [0xa]) (const_int 11 [0xb]) (const_int 12 [0xc]) (const_int 13 [0xd]) (const_int 14 [0xe]) (const_int 15 [0xf]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1727 {neon_vec_unpacks_hi_v16qi} (expr_list:REG_DEAD (reg:V16QI 290 [ vect_var_.35 ]) (nil))) (note 185 164 186 15 NOTE_INSN_DELETED) (insn 186 185 169 15 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 305 [ vect_var_.45 ]) (reg:V4SI 305 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 305 [ vect_var_.45 ]) (nil))) (insn 169 186 177 15 (set (reg:V8HI 328) (unspec:V8HI [ (mem:V8HI (reg/f:SI 329) [2 MEM[(int16_t *)D.7209_27]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_DEAD (reg/f:SI 329) (nil))) (insn 177 169 178 15 (set (reg:V4SI 334) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 178 177 179 15 (set (reg:V4SI 335) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 179 178 187 15 (set (reg:V4SI 306 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 334) (reg:V4SI 335))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 335) (expr_list:REG_DEAD (reg:V4SI 334) (nil)))) (note 187 179 188 15 NOTE_INSN_DELETED) (insn 188 187 180 15 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 306 [ vect_var_.45 ]) (reg:V4SI 306 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 306 [ vect_var_.45 ]) (nil))) (insn 180 188 181 15 (set (reg:V4SI 336) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 292 [ vect_var_.37 ]) (nil))) (insn 181 180 161 15 (set (reg:V4SI 337) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 328) (nil))) (insn 161 181 182 15 (set (reg:V16QI 290 [ vect_var_.35 ]) (mem:V16QI (post_inc:SI (reg:SI 267 [ ivtmp.89 ])) [0 MEM[base: D.7206_62, offset: 0B]+0 S16 A128])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 757 {*neon_movv16qi} (expr_list:REG_INC (reg:SI 267 [ ivtmp.89 ]) (nil))) (insn 182 161 163 15 (set (reg:V4SI 307 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 336) (reg:V4SI 337))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 337) (expr_list:REG_DEAD (reg:V4SI 336) (nil)))) (insn 163 182 191 15 (set (reg:V8HI 291 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1721 {neon_vec_unpacks_lo_v16qi} (nil)) (insn 191 163 286 15 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (reg/f:SI 239 [ vect_p.38 ]) (const_int 32 [0x20]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) (insn 286 191 296 15 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 354 [ bnd.28 ]) (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff]))) ]) 6 {addsi3_compare0} (nil)) (insn 296 286 189 15 (set (reg/f:SI 329) (reg/f:SI 239 [ vect_p.38 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 639 {*arm_movsi_vfp} (nil)) (note 189 296 190 15 NOTE_INSN_DELETED) (insn 190 189 165 15 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 307 [ vect_var_.45 ]) (reg:V4SI 307 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 307 [ vect_var_.45 ]) (nil))) (insn 165 190 287 15 (set (reg:V8HI 327) (unspec:V8HI [ (mem:V8HI (post_inc:SI (reg/f:SI 329)) [2 MEM[(int16_t *)vect_p.38_128]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_INC (reg/f:SI 329) (nil))) (jump_insn 287 165 428 15 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 343) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 343) (note 428 287 391 16 [bb 16] NOTE_INSN_BASIC_BLOCK) (insn 391 428 393 16 (set (reg:V4SI 330) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 393 391 395 16 (set (reg:V4SI 331) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 395 393 397 16 (set (reg:V4SI 304 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 330) (reg:V4SI 331))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 330) (expr_list:REG_DEAD (reg:V4SI 331) (nil)))) (insn 397 395 399 16 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 304 [ vect_var_.45 ]) (reg:V4SI 304 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 304 [ vect_var_.45 ]) (nil))) (insn 399 397 401 16 (set (reg:V4SI 332) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 291 [ vect_var_.37 ]) (nil))) (insn 401 399 403 16 (set (reg:V4SI 333) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 327) (nil))) (insn 403 401 405 16 (set (reg:V4SI 305 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 332) (reg:V4SI 333))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 332) (expr_list:REG_DEAD (reg:V4SI 333) (nil)))) (insn 405 403 407 16 (set (reg:V8HI 292 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 8 [0x8]) (const_int 9 [0x9]) (const_int 10 [0xa]) (const_int 11 [0xb]) (const_int 12 [0xc]) (const_int 13 [0xd]) (const_int 14 [0xe]) (const_int 15 [0xf]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1727 {neon_vec_unpacks_hi_v16qi} (expr_list:REG_DEAD (reg:V16QI 290 [ vect_var_.35 ]) (nil))) (insn 407 405 409 16 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 305 [ vect_var_.45 ]) (reg:V4SI 305 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 305 [ vect_var_.45 ]) (nil))) (insn 409 407 411 16 (set (reg:V8HI 328) (unspec:V8HI [ (mem:V8HI (reg/f:SI 329) [2 MEM[(int16_t *)D.7209_27]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_DEAD (reg/f:SI 329) (nil))) (insn 411 409 413 16 (set (reg:V4SI 334) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 413 411 415 16 (set (reg:V4SI 335) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 415 413 417 16 (set (reg:V4SI 306 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 334) (reg:V4SI 335))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 334) (expr_list:REG_DEAD (reg:V4SI 335) (nil)))) (insn 417 415 419 16 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 306 [ vect_var_.45 ]) (reg:V4SI 306 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 306 [ vect_var_.45 ]) (nil))) (insn 419 417 421 16 (set (reg:V4SI 336) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 292 [ vect_var_.37 ]) (nil))) (insn 421 419 423 16 (set (reg:V4SI 337) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 328) (nil))) (insn 423 421 425 16 (set (reg:V4SI 307 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 336) (reg:V4SI 337))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 336) (expr_list:REG_DEAD (reg:V4SI 337) (nil)))) (insn 425 423 427 16 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (reg/f:SI 239 [ vect_p.38 ]) (const_int 32 [0x20]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) (insn 427 425 436 16 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 307 [ vect_var_.45 ]) (reg:V4SI 307 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 307 [ vect_var_.45 ]) (nil))) (jump_insn 436 427 437 16 (set (pc) (label_ref 435)) -1 (nil) -> 435) (barrier 437 436 343) (code_label 343 437 342 17 24 "" [1 uses]) (note 342 343 438 17 [bb 17] NOTE_INSN_BASIC_BLOCK) (jump_insn 438 342 439 17 (set (pc) (label_ref 193)) -1 (nil) -> 193) (barrier 439 438 435) (code_label 435 439 196 18 28 "" [2 uses]) (note 196 435 197 18 [bb 18] NOTE_INSN_BASIC_BLOCK) (insn 197 196 198 18 (set (reg:V2SI 343) (plus:V2SI (vec_select:V2SI (reg:V4SI 312 [ vect_var_.47 ]) (parallel [ (const_int 0 [0]) (const_int 1 [0x1]) ])) (vec_select:V2SI (reg:V4SI 312 [ vect_var_.47 ]) (parallel [ (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) 993 {quad_halves_plusv4si} (expr_list:REG_DEAD (reg:V4SI 312 [ vect_var_.47 ]) (nil))) (note 198 197 297 18 NOTE_INSN_DELETED) (insn 297 198 199 18 (set (reg:V4SI 342) (const_vector:V4SI [ (const_int 0 [0]) (const_int 0 [0]) (const_int 0 [0]) (const_int 0 [0]) ])) 759 {*neon_movv4si} (nil)) (insn 199 297 200 18 (set (subreg:V2SI (reg:V4SI 342) 0) (unspec:V2SI [ (reg:V2SI 343) (reg:V2SI 343) ] UNSPEC_VPADD)) 1014 {neon_vpadd_internalv2si} (expr_list:REG_DEAD (reg:V2SI 343) (nil))) (insn 200 199 201 18 (set (reg:SI 345) (vec_select:SI (reg:V4SI 342) (parallel [ (const_int 0 [0]) ]))) 802 {vec_extractv4si} (expr_list:REG_DEAD (reg:V4SI 342) (nil))) (insn 201 200 202 18 (set (reg/v:SI 277 [ score ]) (plus:SI (reg/v:SI 277 [ score ]) (reg:SI 345))) 4 {*arm_addsi3} (expr_list:REG_DEAD (reg:SI 345) (nil))) (insn 202 201 203 18 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (reg:SI 276 [ ratio_mult_vf.29 ]))) 4 {*arm_addsi3} (nil)) (insn 203 202 204 18 (set (reg:CC 24 cc) (compare:CC (reg:SI 274 [ niters.27 ]) (reg:SI 276 [ ratio_mult_vf.29 ]))) 211 {*arm_cmpsi_insn} (expr_list:REG_DEAD (reg:SI 276 [ ratio_mult_vf.29 ]) (expr_list:REG_DEAD (reg:SI 274 [ niters.27 ]) (nil)))) (jump_insn 204 203 205 18 (set (pc) (if_then_else (eq (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 225) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 0 [0]) (nil))) -> 225) (code_label 205 204 206 19 6 "" [1 uses]) (note 206 205 207 19 [bb 19] NOTE_INSN_BASIC_BLOCK) (insn 207 206 208 19 (set (reg:SI 346) (plus:SI (reg/v:SI 278 [ i ]) (const_int -1 [0xffffffffffffffff]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) (note 208 207 209 19 NOTE_INSN_DELETED) (insn 209 208 274 19 (set (reg:SI 287 [ ivtmp.61 ]) (plus:SI (mult:SI (reg:SI 346) (const_int 2 [0x2])) (reg/v/f:SI 228 [ pix2 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 264 {*arith_shiftsi} (expr_list:REG_DEAD (reg:SI 346) (expr_list:REG_DEAD (reg/v/f:SI 228 [ pix2 ]) (nil)))) (insn 274 209 277 19 (set (reg:SI 352) (minus:SI (reg/v:SI 229 [ size ]) (reg/v:SI 278 [ i ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 31 {*arm_subsi3_insn} (nil)) (insn 277 274 279 19 (set (reg:SI 353) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) 4 {*arm_addsi3} (nil)) (insn 279 277 280 19 (set (reg:CC 24 cc) (compare:CC (reg:SI 353) (reg/v:SI 229 [ size ]))) 211 {*arm_cmpsi_insn} (expr_list:REG_DEAD (reg:SI 353) (nil))) (jump_insn 280 279 284 19 (set (pc) (if_then_else (gt (reg:CC 24 cc) (const_int 0 [0])) (label_ref 278) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 0 [0]) (nil))) -> 278) (note 284 280 282 20 [bb 20] NOTE_INSN_BASIC_BLOCK) (insn 282 284 283 20 (set (reg:CC 24 cc) (compare:CC (reg/v:SI 229 [ size ]) (const_int -2147483648 [0xffffffff80000000]))) 211 {*arm_cmpsi_insn} (expr_list:REG_DEAD (reg/v:SI 229 [ size ]) (nil))) (jump_insn 283 282 278 20 (set (pc) (if_then_else (ne (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 218) (pc))) 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 10000 [0x2710]) (nil))) -> 218) (code_label 278 283 275 21 17 "" [1 uses]) (note 275 278 285 21 [bb 21] NOTE_INSN_BASIC_BLOCK) (insn 285 275 218 21 (set (reg:SI 352) (const_int 1 [0x1])) 639 {*arm_movsi_vfp} (nil)) (code_label 218 285 210 22 9 "" [1 uses]) (note 210 218 322 22 [bb 22] NOTE_INSN_BASIC_BLOCK) (note 322 210 323 23 [bb 23] NOTE_INSN_BASIC_BLOCK) (insn 323 322 324 23 (set (reg:CC 24 cc) (compare:CC (reg:SI 352) (const_int 2 [0x2]))) -1 (nil)) (jump_insn 324 323 327 23 (set (pc) (if_then_else (gt (reg:CC 24 cc) (const_int 0 [0])) (label_ref:SI 326) (pc))) 223 {*arm_cond_branch} (nil) -> 326) (note 327 324 441 24 [bb 24] NOTE_INSN_BASIC_BLOCK) (jump_insn 441 327 442 24 (set (pc) (label_ref 440)) -1 (nil) -> 440) (barrier 442 441 326) (code_label 326 442 325 25 23 "" [1 uses]) (note 325 326 335 25 [bb 25] NOTE_INSN_BASIC_BLOCK) (note 335 325 328 26 [bb 26] NOTE_INSN_BASIC_BLOCK) (insn 328 335 330 26 (set (reg:SI 352) (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff]))) -1 (nil)) (insn 330 328 332 26 (set (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg/v:SI 278 [ i ])) [0 MEM[base: pix1_3, index: D.7175_19, offset: 0B]+0 S1 A8]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 175 {*arm_extendqisi_v6} (nil)) (insn 332 330 334 26 (set (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 287 [ ivtmp.61 ])) [2 MEM[base: D.7176_20, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 287 [ ivtmp.61 ]) (nil))) (insn 334 332 305 26 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) (code_label 305 334 304 27 20 "" [1 uses]) (note 304 305 307 27 [bb 27] NOTE_INSN_BASIC_BLOCK) (insn 307 304 212 27 (set (reg:SI 356) (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ])) 639 {*arm_movsi_vfp} (nil)) (insn 212 307 272 27 (set (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg/v:SI 278 [ i ])) [0 MEM[base: pix1_3, index: D.7175_19, offset: 0B]+0 S1 A8]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 175 {*arm_extendqisi_v6} (nil)) (insn 272 212 214 27 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 352) (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff]))) ]) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 6 {addsi3_compare0} (nil)) (insn 214 272 213 27 (set (reg:SI 285 [ D.7092 ]) (minus:SI (reg:SI 356) (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 31 {*arm_subsi3_insn} (expr_list:REG_DEAD (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (expr_list:REG_DEAD (reg:SI 356) (nil)))) (insn 213 214 215 27 (set (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 287 [ ivtmp.61 ])) [2 MEM[base: D.7176_20, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 287 [ ivtmp.61 ]) (nil))) (note 215 213 216 27 NOTE_INSN_DELETED) (insn 216 215 217 27 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 285 [ D.7092 ]) (reg:SI 285 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 285 [ D.7092 ]) (nil))) (insn 217 216 273 27 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) (jump_insn 273 217 341 27 (set (pc) (if_then_else (ne (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 309) (pc))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 223 {*arm_cond_branch} (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil))) -> 309) (note 341 273 336 28 [bb 28] NOTE_INSN_BASIC_BLOCK) (insn 336 341 338 28 (set (reg:SI 356) (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ])) -1 (nil)) (insn 338 336 340 28 (set (reg:SI 285 [ D.7092 ]) (minus:SI (reg:SI 356) (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 31 {*arm_subsi3_insn} (expr_list:REG_DEAD (reg:SI 356) (expr_list:REG_DEAD (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (nil)))) (insn 340 338 443 28 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 285 [ D.7092 ]) (reg:SI 285 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 285 [ D.7092 ]) (nil))) (jump_insn 443 340 444 28 (set (pc) (label_ref 225)) -1 (nil) -> 225) (barrier 444 443 309) (code_label 309 444 308 29 21 "" [1 uses]) (note 308 309 445 29 [bb 29] NOTE_INSN_BASIC_BLOCK) (jump_insn 445 308 446 29 (set (pc) (label_ref 305)) -1 (nil) -> 305) (barrier 446 445 235) (code_label 235 446 234 30 10 "" [1 uses]) (note 234 235 112 30 [bb 30] NOTE_INSN_BASIC_BLOCK) (insn 112 234 225 30 (set (reg/v:SI 277 [ score ]) (const_int 0 [0])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:23 639 {*arm_movsi_vfp} (nil)) (code_label 225 112 226 31 2 "" [4 uses]) (note 226 225 228 31 [bb 31] NOTE_INSN_BASIC_BLOCK) (insn 228 226 229 31 (set (reg/f:SI 351) (symbol_ref:SI ("peak_score") [flags 0xc0] )) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:29 639 {*arm_movsi_vfp} (expr_list:REG_EQUAL (symbol_ref:SI ("peak_score") [flags 0xc0] ) (nil))) (insn 229 228 440 31 (set (mem/c/i:SI (reg/f:SI 351) [3 peak_score+0 S4 A32]) (reg/v:SI 277 [ score ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:29 639 {*arm_movsi_vfp} (expr_list:REG_DEAD (reg/f:SI 351) (expr_list:REG_DEAD (reg/v:SI 277 [ score ]) (nil)))) (code_label 440 229 318 32 29 "" [2 uses]) (note 318 440 311 32 [bb 32] NOTE_INSN_BASIC_BLOCK) (insn 311 318 312 32 (set (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 227 [ pix1 ]) (reg/v:SI 278 [ i ])) [0 MEM[base: pix1_3, index: D.7175_19, offset: 0B]+0 S1 A8]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 175 {*arm_extendqisi_v6} (nil)) (insn 312 311 313 32 (set (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (sign_extend:SI (mem:HI (pre_inc:SI (reg:SI 287 [ ivtmp.61 ])) [2 MEM[base: D.7176_20, offset: 0B]+0 S2 A16]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 171 {*arm_extendhisi2_v6} (expr_list:REG_INC (reg:SI 287 [ ivtmp.61 ]) (nil))) (insn 313 312 314 32 (set (reg:SI 285 [ D.7092 ]) (minus:SI (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 31 {*arm_subsi3_insn} (expr_list:REG_DEAD (reg:SI 348 [ MEM[base: pix1_3, index: D.7175_19, offset: 0B] ]) (expr_list:REG_DEAD (reg:SI 349 [ MEM[base: D.7176_20, offset: 0B] ]) (nil)))) (insn 314 313 315 32 (set (reg/v:SI 277 [ score ]) (plus:SI (mult:SI (reg:SI 285 [ D.7092 ]) (reg:SI 285 [ D.7092 ])) (reg/v:SI 277 [ score ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 44 {*mulsi3addsi_v6} (expr_list:REG_DEAD (reg:SI 285 [ D.7092 ]) (nil))) (insn 315 314 316 32 (set (reg/v:SI 278 [ i ]) (plus:SI (reg/v:SI 278 [ i ]) (const_int 1 [0x1]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 4 {*arm_addsi3} (nil)) (insn 316 315 317 32 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 352) (plus:SI (reg:SI 352) (const_int -1 [0xffffffffffffffff]))) ]) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 6 {addsi3_compare0} (nil)) (jump_insn 317 316 321 32 (set (pc) (if_then_else (eq (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 225) (pc))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:26 223 {*arm_cond_branch} (expr_list:REG_BR_PROB (const_int 900 [0x384]) (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (nil))) -> 225) (code_label 321 317 320 33 22 "" [0 uses]) (note 320 321 447 33 [bb 33] NOTE_INSN_BASIC_BLOCK) (jump_insn 447 320 448 33 (set (pc) (label_ref 440)) -1 (nil) -> 440) (barrier 448 447 432) (code_label 432 448 370 34 27 "" [2 uses]) (note 370 432 345 34 [bb 34] NOTE_INSN_BASIC_BLOCK) (insn 345 370 346 34 (set (reg:V16QI 290 [ vect_var_.35 ]) (mem:V16QI (post_inc:SI (reg:SI 267 [ ivtmp.89 ])) [0 MEM[base: D.7206_62, offset: 0B]+0 S16 A128])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 757 {*neon_movv16qi} (expr_list:REG_INC (reg:SI 267 [ ivtmp.89 ]) (nil))) (insn 346 345 347 34 (set (reg:V8HI 291 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1721 {neon_vec_unpacks_lo_v16qi} (nil)) (insn 347 346 348 34 (set (reg:V8HI 292 [ vect_var_.37 ]) (sign_extend:V8HI (vec_select:V8QI (reg:V16QI 290 [ vect_var_.35 ]) (parallel:V16QI [ (const_int 8 [0x8]) (const_int 9 [0x9]) (const_int 10 [0xa]) (const_int 11 [0xb]) (const_int 12 [0xc]) (const_int 13 [0xd]) (const_int 14 [0xe]) (const_int 15 [0xf]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1727 {neon_vec_unpacks_hi_v16qi} (expr_list:REG_DEAD (reg:V16QI 290 [ vect_var_.35 ]) (nil))) (insn 348 347 349 34 (set (reg/f:SI 329) (reg/f:SI 239 [ vect_p.38 ])) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 639 {*arm_movsi_vfp} (nil)) (insn 349 348 350 34 (set (reg:V8HI 327) (unspec:V8HI [ (mem:V8HI (post_inc:SI (reg/f:SI 329)) [2 MEM[(int16_t *)vect_p.38_128]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_INC (reg/f:SI 329) (nil))) (insn 350 349 351 34 (set (reg:V8HI 328) (unspec:V8HI [ (mem:V8HI (reg/f:SI 329) [2 MEM[(int16_t *)D.7209_27]+0 S16 A16]) ] UNSPEC_MISALIGNED_ACCESS)) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 783 {*movmisalignv8hi_neon_load} (expr_list:REG_DEAD (reg/f:SI 329) (nil))) (insn 351 350 352 34 (set (reg:V4SI 330) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 352 351 353 34 (set (reg:V4SI 331) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 353 352 354 34 (set (reg:V4SI 304 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 330) (reg:V4SI 331))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 330) (expr_list:REG_DEAD (reg:V4SI 331) (nil)))) (insn 354 353 355 34 (set (reg:V4SI 332) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 291 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 291 [ vect_var_.37 ]) (nil))) (insn 355 354 356 34 (set (reg:V4SI 333) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 327) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 327) (nil))) (insn 356 355 357 34 (set (reg:V4SI 305 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 332) (reg:V4SI 333))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 332) (expr_list:REG_DEAD (reg:V4SI 333) (nil)))) (insn 357 356 358 34 (set (reg:V4SI 334) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 358 357 359 34 (set (reg:V4SI 335) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 0 [0]) (const_int 1 [0x1]) (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1723 {neon_vec_unpacks_lo_v8hi} (nil)) (insn 359 358 360 34 (set (reg:V4SI 306 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 334) (reg:V4SI 335))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 334) (expr_list:REG_DEAD (reg:V4SI 335) (nil)))) (insn 360 359 361 34 (set (reg:V4SI 336) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 292 [ vect_var_.37 ]) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 292 [ vect_var_.37 ]) (nil))) (insn 361 360 362 34 (set (reg:V4SI 337) (sign_extend:V4SI (vec_select:V4HI (reg:V8HI 328) (parallel:V8HI [ (const_int 4 [0x4]) (const_int 5 [0x5]) (const_int 6 [0x6]) (const_int 7 [0x7]) ])))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 1729 {neon_vec_unpacks_hi_v8hi} (expr_list:REG_DEAD (reg:V8HI 328) (nil))) (insn 362 361 363 34 (set (reg:V4SI 307 [ vect_var_.45 ]) (minus:V4SI (reg:V4SI 336) (reg:V4SI 337))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 820 {*subv4si3_neon} (expr_list:REG_DEAD (reg:V4SI 336) (expr_list:REG_DEAD (reg:V4SI 337) (nil)))) (insn 363 362 364 34 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 304 [ vect_var_.45 ]) (reg:V4SI 304 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 304 [ vect_var_.45 ]) (nil))) (insn 364 363 365 34 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 305 [ vect_var_.45 ]) (reg:V4SI 305 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 305 [ vect_var_.45 ]) (nil))) (insn 365 364 366 34 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 306 [ vect_var_.45 ]) (reg:V4SI 306 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 306 [ vect_var_.45 ]) (nil))) (insn 366 365 367 34 (set (reg:V4SI 312 [ vect_var_.47 ]) (plus:V4SI (mult:V4SI (reg:V4SI 307 [ vect_var_.45 ]) (reg:V4SI 307 [ vect_var_.45 ])) (reg:V4SI 312 [ vect_var_.47 ]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:27 839 {mulv4si3addv4si_neon} (expr_list:REG_DEAD (reg:V4SI 307 [ vect_var_.45 ]) (nil))) (insn 367 366 368 34 (set (reg/f:SI 239 [ vect_p.38 ]) (plus:SI (reg/f:SI 239 [ vect_p.38 ]) (const_int 32 [0x20]))) autosrc/libav/dsputil-ssd_int8_vs_int16_c/peak.c:17 4 {*arm_addsi3} (nil)) (insn 368 367 369 34 (parallel [ (set (reg:CC_NOOV 24 cc) (compare:CC_NOOV (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff])) (const_int 0 [0]))) (set (reg:SI 354 [ bnd.28 ]) (plus:SI (reg:SI 354 [ bnd.28 ]) (const_int -1 [0xffffffffffffffff]))) ]) 6 {addsi3_compare0} (nil)) (jump_insn 369 368 373 34 (set (pc) (if_then_else (eq (reg:CC_NOOV 24 cc) (const_int 0 [0])) (label_ref:SI 435) (pc))) 223 {*arm_cond_branch} (expr_list:REG_BR_PROB (const_int 900 [0x384]) (expr_list:REG_DEAD (reg:CC_NOOV 24 cc) (nil))) -> 435) (code_label 373 369 372 35 25 "" [0 uses]) (note 372 373 449 35 [bb 35] NOTE_INSN_BASIC_BLOCK) (jump_insn 449 372 450 35 (set (pc) (label_ref 432)) -1 (nil) -> 432) (barrier 450 449 0)