== Issue ==
* none
== Progress ==
* [TCWG-762] - GCC Maintenance (9/10)
- Linaro bugzilla 1399 identified as an upstream bug (PR65647)
Now fixed on trunk and backported in FSF 4.9, will be in our
branch in the coming branch merge.
* [TCWG-699] Backports
- Committed them into our SVN FSF repo.
* Misc (1/10)
- Various meetings
== Plan ==
- FSF branch merge
- Back on a Thumb2 insn fix
== Progress ==
LLDB development
-- Completed implementation and submited native Linux register context
for Arm upstream [3/10] [TCWG-650]
-- Completed implementation and submitted POSIX register context for
Arm upstream [3/10] [TCWG-755]
-- Fixing LLDB build and dev environment issues [1/10]
Miscellaneous [3/10]
-- 3rd April Swap day for 23rd March Public Holiday
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Bug Fixing and Test result improvement.
-- Patch reviews and upstream commits.
Miscellaneous
-- Try LLDB armhf builds and figure out a way to do gcc 4.8 softfloat build.
4 day work week (03-Apr good Friday) (2/10)
* ASAN 32bit allocator failures on amd-01 (4/10)
Completed analyzing failures. Sent a patch to Address sanitizes
community for review. Applied patch to latest LLVM trunk and ran
tests. found one failure. But it was due to the test case assuming
that return value from "getpwnam_r" all is always zero. Fixed the
test case by removing the assert and all LLVM tests passes.
[ Renato tested the patch on APM (39 bit VA) ].
* Again there is some discussion in GCC bugzilla on deciding which
allocators to use for Aarch64 42 bit VA*.
I have a patches for both allocators and posted it to ASAN group
64 bit allocators wont work on juno. So for ASAN there is a need to
have some kind of dynamic address space detection mechanism. Set the
allocators type and required mappings at runtime for Aarch64.
But that needs to be decided by ASAN group whether to do that or use
my 32 bit allocator patch . I am planning to stop it here and wait as
suggested by renato.
* Get TSAN building for Aarch64 on 42-bit VMA systems. (2/10) (-pie mode only)
Applied patch that I had on GCC tree on LLVM trunk. Build failed need
to set kVdsoBeg and kMadviseRangeBeg. I set some default value to
allow TSAN build to complete. right now clang does not recognize
aarch64 target for aarch64 although I enabled it under TSAN. looking
at the issue.
* Emails, meetings. (2/10)
* Linaro 1-1 with christophe, Ryan, status meet
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
== Plan ==
* Get TSAN building for Aarch64 on 42-bit VMA systems. (-pie mode only)
* Document TSAN/ASAN work and patch details in wiki.
== Issues ==
* ASAN patch cannot be up streamed unless we decide on allocator to use.
== This week ==
* TCWG-619
- v8 LTO build with different options for x86 and aarch64.
- Reported upstream v8 LTO build failure on ARM.
- Tried to build chromium with FSF gcc, linaro binary release and
linaro-4.9-branch
* PR49551
- Not able to reproduce ICE with latest trunk (r221871).
* Misc
- College assignments submission and term end.
== Next Week ==
* TCWG-619
- Build chromium with linaro-4.9-branch and trunk.
- Prepare stats for LTO build with different options for v8 on x86 and aarch64
- Try building chromium with LTO with FSF trunk for arm
* TCWG-639:
- Add enhancement to header file flattening script.
== Progress ==
Friday holiday
* Automation Framework (CARD-1378 2/10)
- Power cut in the office
- Fixing gateway, rebooting machines
- Mob management
* LLVM ARM Maintenance (CARD-1833 2/10)
- ARMTargetParser review
* Background (4/10)
- Code review, meetings, discussions, etc.
- All LLVM buildbots broken (one still)
- Trying to merge Android round/exception
- https://android-review.googlesource.com/#/c/125910/1
- Not that easy, will need bigger changes and tests to go in
== Plan ==
* Long holidays
* EuroLLVM
* Back on the 15th
Hi,
I did some tests on the following function
--- CUT HERE ---
int fibo(int n)
{
if (n < 2) return 1;
return (fibo(n-2) + fibo(n-1));
}
--- CUT HERE ---
and I discovered that it is faster -O2 than -O3. This is with gcc 4.9.2.
Looking at the disassembly I see it is using FP registers to hold
integer values. The following is a small extract.
.L3:
fmov w0, s8
sub w25, w25, #1
cmn w25, #1
add w0, w0, w27
fmov s8, w0
bne .L19
add w0, w0, 1
b .L2
Recompiling with -mgeneral-regs-only generates a huge improvement.
The following are the times I get on various partner HW. I have
normalised the -O2 times to 1 second so that I do not disclose actual
partner performance data:
Partner 1: -O2 = 1sec, -O3 = 1.13sec, -O3 -mgeneral-regs-only = 0.72sec
Partner 2: -O2 = 1sec, -O3 = 0.68sec, -O3 -mgeneral-regs-only = 0.60sec
Partner 3: -O2 = 1sec, -O3 = 0.73sec, -O3 -mgeneral-regs-only = 0.68sec
Partner 4: -O2 = 1sec, -O3 = 0.83sec, -O3 -mgeneral-regs-only = 0.84sec
So, in general, -O3 does actually do better than -O2, but in all cases
performance is better if I stop it using FP registers for int values.
I have put a tarball of the test program along with 3 binaries and 3
disassemblies here:-
http://people.linaro.org/~edward.nevill/fibo.tar
All the best,
Ed.
Hi,
I'm seeing the following build error trying to build from the current master
branch (1ac806b) of http://git.linaro.org/toolchain/binutils-gdb.
make[3]: *** No rule to make target `-L../zlib', needed by `run'. Stop.
make[3]: *** Waiting for unfinished jobs....
make[3]: Leaving directory `gdb/sim/arm'
The following commit predating the zlib changes appears to build without error.
b19a8f8545100a08ee2a64c05631aff6f651faa1
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
catomics - TCWG-436 [5/10]
* Got pointed at a suitable set of benchmarks, results still underwhelming
* However, patches were using relaxed atomics rather than no atomics at all
* Fiddled abe into building sysroots for me (I get libstdc++ that way)
Misc - [5/10]
* Tidied up some 'perf shotgun' scripting from the juno cache
investigation, so I've got the tools for next time
* Started sorting out my backups - but didn't finish before build-01's
death destroyed a bunch of work
* Raised priority of sorting out my backups, now just a matter of
waiting on some large rysncs
* Pieced my world back together on dev-01
=Plan=
Holiday Wednesday, public holidays next Friday and Monday
See how catomics do when we're conditionally-not-atomic-at-all
Investigate a bit to see if I can see if there's a reason we were
using relaxed atomics
Resurrect Jira benchmarking on dev-01
* Will include some porting, scripts don't work out of box on dev-01
One day off on Friday. [2/10]
# Progress #
* aarch64 gdb, the number of FAIL is reduced to 26 on aarch64-linux!
there are still about 10+ FAILs can be fixed. [4/10]
** TCWG-726, fails in gdb.base/break-interp.exp. Fixed.
Remove prelink package from juno board as aarch64 isn't supported.
** TCWG-681, fails in savedregs.exp. Patch is committed.
** PR 18139. Patches are committed.
* arm gdb, 938 fails for -mfloat-abi=soft and 1014 fails for
-mfloat-abi=hard. Analysing fails. [2/10]
* GDB kernel-awareness meeting with ST. [1/10]
Understand the definition of "kernel-awareness", and will
discuss about the design upstreams later.
* TCWG-716, investigate LLDB perf testing. [1/10] Done.
** LLDB already had something about performance testing, in
lldb/test/benchmarks/ and lldb/tools/lldb-perf.
** TestCompileRunToBreakpointTurnaround.py compares the speed of LLDB
and GDB, but in an incorrect way.
# Plan #
* Take more care on arm gdb test fails.
* Fix the rest of aarch64 gdb fails.
--
Yao
