o 1 day off (2/10)
== Progress ==
o Extended validation (2/10)
* Extended validation now operational,
reporting enhancements investigations.
* Looked at gdb/guality unstable results.
* Reviewed some jobs.
o Linaro GCC (2/10)
* Scripted new Linaro development branch process.
o Upstream GCC (1/10)
* Digging in libatomic code.
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o 2 days off (Thu/Fri)
o Continue on validation and upstream work.
== This Week ==
* LTO (6/10)
a) TCWG-128 (1/10)
- committed patch for adding param lto-max-partition, which
can now be used as workaround for building chromium with minimal
number of required partitions.
- committed patch for setting default value of lto-min-partition to 10000.
b) TCWG-528 (1/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch_increase_alignment.diff
- Cross tested on arm*-*-*, aarch64*-*-* and bootstrapped and tested
on aarch64-linux-gnu
- I want to cross test once for ppc64 since that's also affected.
c) TCWG-548 (4/10)
- Patch: http://people.linaro.org/~prathamesh.kulkarni/patch-vars-3.diff
- Cross tested for arm*-*-* and aarch64*-*-*
* TCWG-319 (2/10)
- Comparing diff's of vect for arm and armeb shows, armeb not
supporting unaligned access
- Looking thru arm backend code to see why this happens.
* Validation (1/10)
- Script to build chromium
* Misc (1/10)
- Looked at PR70848, PR60172
- Meetings
== Next Week ==
LTO: section anchors, increase_alignment pass
TCWG-319: Continue investigation
Validation: Try to get the script merged to tcwg-buildapp repo.
# Progress #
* TCWG-466, ADRL pseudo instruction support in integrated assembler. I
couldn't find a way of putting ADRL into the assembler in a
maintainable way. Managed to work out a pretty close approximation of
ADRL in a macro so I added it to upstream PR. Put the results of the
my investigations into TCWG-466. Agreed with Renato's initial
diagnosis of won't fix.
* TCWG-468, Transform LDR rn, =expr pseudo instruction into MOV. I'm
more hopeful with this one. I've got a prototype that delays the
emission of the constant pool entry to a point where the
transformation can occur.
* Try out the build and push scripts. Had a frustrating day of chasing
down missing dependencies from my Ubuntu 12.04 machine while building
lldb. Should be resolved now.
# Plan #
* UK national holiday on Monday.
* Continue with TCWG-468. I've got a tablegen prototype that treats
LDR rd,= as a real pseudo instruction. Need to finish Thumb and
Thumb2. Next step after that is to do the transformation to MOV.
* Will spend any other time investigating LLD
# Progress #
* TCWG-518, range stepping on arm-linux. Rebase my patches, and choose
a different approach which is better. However, GDBserver crashes in
some cases, and I am investigating the crash. [5/10]
* TCWG-547, make some progress on the upstream discussion. We agree to
do it in a cleaner way but some GDB internal interface needs some
changes. [2/10]
* Read some articles about exception handling, this one is quite useful,
https://gcc.gnu.org/ml/gcc/2002-07/msg00391.html [1/10]
* Meeting, upstream patch review. [2/10]
# Plan #
* TCWG-518, TCWG-547
--
Yao
== Progress ==
* Rework LLVM helper scripts [TCWG-571] [4/10]
- Code review + minor improvements to the scripts
- Started a discussion about the interfaces of some of the scripts
(llvm-projs, llvm-sync)
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071
- Discovered that the assert is only triggered for
aarch64-linux-gnueabi, whereas arm-linux-gnueabi behaves as expected
(prints the error but doesn't assert afterwards). This has proven
useful for figuring out the intended behavior of the code.
* Move buildbots to CMake 3.4.3 [TCWG-573] [1/10]
- Helped move some of the bots (llvm-a15-*) to CMake 3.4.3
* Misc [2/10]
- Buildbot monitoring
- Meetings
== Plan ==
* Inline assembly constraints support for ARM [TCWG-560]
- Come up with a fix for PR24071
* Rework LLVM helper scripts [TCWG-571]
- Start a review for the new interface to llvm-projs/llvm-sync, so
we can have some concrete support for further discussion
- Investigate git worktree and how it could be factored into our
scripts (llvm-projs, llvm-build)
* Move buildbots to CMake 3.4.3 [TCWG-573]
- Help with the llvm-chrome-* bots if necessary
* OOO on Monday
== Progress ==
* Validation
- armvl8 differences between master and stable branches understood
(master defaulted to Thumb)
- updated ABE stable branch for validation
- ABE now uses linaro-local/stable DejaGnu branch
- updated ABE legacy version to use this DJ branch too, and updated
the Foundation Model path
- updated Jenkins jobs accordingly
* Backports
- created a few backports for our gcc-5 branch, to prepare handover
- slight documentation update
* GCC
- enhancements to validation harnesses to better handle
infrastructure problems
- using monitoring and regressions reports
* Cortex-strings
- updated a few aarch64 mem* routines from newlib versions
* Support
- finally reproduced the Windows-hosted toolchain bugs
by rebuilding in a properly updated Jessie chroot.
- building the next release in Trusty container should fix
these problems
* Misc (confi-calls, meetings, emails, ....)
== Next ==
* Validation: cleanup & reviews
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
As a note, all the builders we use for binary releases run Trusty still. I haven't tried Jessie (should work fine),but I know that newer Mingw releases fail to compile GCC 5.x.
- rob -
-------- Original message --------
From: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: 04/22/2016 14:00 (GMT-07:00)
To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
Subject: [ACTIVITY] 18-22 April 2016
* 3 days off
== Progress ==
* Validation:
- fixed ABE master and stable branches to use 'ssh -t' instead of
'ssh -tt' when cross-testing
- trying to assert master vs stable before the array branch merge,
noticed differences on armv8l
- created linaro-local/stable Dejagnu branch (currently a copy of
master). Prepared ABE config patches to use it.
* GCC
- infrastructure problems (ST compute farm), leading to a lot of
noise in the validations (and wrong regression reports upstream)
- enabled gcc-6-branch monitoring
- added GCC-6 tab to the backports spreadsheet
* Support
- Windows-hosted toolchain crashes: it seems the builders we use to
make the release run Jessie and not Trusty. Tried to rebuild a
toolchain in a Jessie chroot, but the script failed (works under
Trusty)
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation
- check that using linaro-local/stable Dejagnu branch works well
- create validation reference points before array branch merge
- understand/fix armv8l validation differences between master/stable
ABE branches
* GCC
- trunk monitoring, report regressions if needed
- more intrinsics tests
* Support
- Windows-hosted toolchain bug
* Snapshots
- prepare a few backports for our gcc-5 branch
* Cortex-strings update
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Failures reduced to 15 fails and 4 errors after fixing stepping bug.
-- Investigated remaining issues some of them are known issues and
others will need further investigation.
LLDB ARM Thread Stepping Problem [TCWG-566] [5/10]
-- Problems caused because incorrect reporting of PLT entry size set by linker.
-- Submitted a fix after analysis that logical size of PLT entry
should be greater than 4bytes.
-- Fix accepted and committed upstream.
LLDB Buildbot Setup [TCWG-241] [1/10]
-- Random change in results finally caught. It was due to inconsistent network.
-- Progress halted to fix arm-linux-gnueabihf bugs.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB Chromebook Test Stability [TCWG-563]
-- Continue to resolve and investigate chromebook test failures.
LLDB Buildbot Setup [TCWG-241]
-- Start AArch64 tester evaluations.
Progress:
- On holiday all week, at ACCU conference. I've put some highlights at
the end of the message.
- Did some more investigation into TCWG-466 ADRL support in integrated
assembler during breaks.
-- Not looking good, to do this properly bumps up against a lot of
design decisions and restrictions made by the LLVM assembler (designed
as compiler target, not to be user friendly).
-- There are ways it could be implemented with restrictions, but it is
debateable whether it is worth doing at all.
-- On the plus side I've got a much better idea of how the assembler
works and what restrictions exist on each stage of the journey from a
line in the .s file to emission in the object. Will add some comments
to the LDR r0, =expr TCWG as well.
-- On the negative side the :upper16: and :lower16: operators for MOVT
and MOVW don't look to be correct in the presence of addends. Will
need to investigate further to see what the scope of the problem is.
Plan:
- Dump results of TCWG-466 investigation into Jira.
- Take a look at and post a comment on Adhemerval's revised TLS patch,
even if it is just looks fine in the hope of pushing it forward a bit
more.
- Catch up with Renato's scripts and documents for LLVM sub-group.
- Work out what to do with TCWG-466, if the answer is put it down,
find something else to look at.
ACCU Highlights/Report:
Tough stuff in modern C++
A deep dive into some of the newer areas of C++ such as:
- rvalue references and forwarding (universal) references
- How to use SFINAE (mostly std::enable_if) to select algorithms
optimised for particular template instantiations
- Variadic templates. Including all sorts of strange ways to (ab)use
expansion of parameter packs.
C++ WG21 SG14 Gaming and low-latency study group
- A new study group aiming to represent the gaming (primarily), but
also embedded and high frequency trading concerns.
- Motto seemed to be make sure "Don't pay for what you don't use" is enforced.
Most interested in:
-- No exceptions configurations
-- No RTTI
-- More performance out of the STL (see EA STL
https://github.com/electronicarts/EASTL)
-- Add ring buffers and support for unitialised memory, fixed point
numbers, flat-map, standardised simd vector types
Using sentinels
- An example of how using two sentinels in an implementation of
std::partion speeds up the algorithm by saving comparisons. Can speed
up quicksort by a few percent
Constexpr in C++14
- Example showing how you could build a string to enum map, operating
entirely at compile time, and its subsequent negative effects on
compile time!
Concepts Lite
- Concepts missed the C++17 standard, this presentation went into the
current Technical Standard (optional) and how concepts would likely be
implemented in C++(20?)
- Not surprising to see that concepts still missed C++17 as there is
only one implementation and one non-trivial use case (ranges) and
there are still unresolved questions to be answered.
Introduction to Julia
- Really a comparison of Julia to the author's favoured language of common lisp.
- Was impressed at how "lispy" Julia was whilst retaining high performance.
- Liked the mathematical syntax
- Didn't like the python like parts that seemed to be added to try and
get people to migrate from python, but were non "lispy".
# Progress #
* TCWG-545, patches are committed. Done. [3/10]
* TCWG-167, ARM reverse debugging bug fixes. All test fails are
fixed. Done. [2/10].
* PR 19947. The fix is approved, but the patch triggering the bug
needs update. [2/10]
* Help to fix broken ARM GDB after C++ switch. [2/10].
GDB mainline is a C++ program in default. Exception
handling in GDB is broken on non-x86 host (ARM, AArch64, AIX, at
least) because readline (C library) calls C++ GDB code, but exception
unwinding can't cross the C function ("foreign frame"). The problem
is fixed by catching all exceptions before return to readline, and
re-throw them after return from readline back to GDB.
* Misc, [1/10]
** Hack QEMU so that I can run gdb regression testsuite with qemu-arm.
# Plan #
* TCWG-518, rebase patches on mainline, test, and post patches if
nothing wrong.
* PR 19947, TCWG-561,
* TCWG-547
--
Yao
