On 11/9/2024 8:37 AM, Namhyung Kim wrote:
> On Fri, 08 Nov 2024 12:11:19 -0700, Steve Clevenger wrote:
>
>> Changes in V11:
>> - Corrected prefix.
>> - Fixed compile-time error for perf debug build by substituting in
>> the map__pgoff macro (trace_event_python.c).
>>
>> Changes in V10:
>> - Removed errant space in patch file 0002. Passed 'git apply --check'
>> at perf-tools-next, 6.11.0-rc6.
>> - Added back missing prefixes.
>>
>> [...]
>
> Applied to perf-tools-next, thanks!
>
> Best regards,
> Namhyung
>
Thanks, Namhyung.
Steve C.
FEAT_TRF is a Coresight feature that allows trace capture to be
completely filtered at different exception levels, unlike the existing
TRCVICTLR controls which may still emit target addresses of branches,
even if the following trace is filtered.
Without FEAT_TRF, it was possible to start a trace session on a host and
also collect trace from the guest as TRCVICTLR was never programmed to
exclude guests (and it could still emit target addresses even if it
was).
With FEAT_TRF, the current behavior of trace in guests exists depends on
whether nVHE or VHE are being used. Both of the examples below are from
the host's point of view, as Coresight isn't accessible from guests.
This patchset is only relevant to when FEAT_TRF exists, otherwise there
is no change.
Current behavior:
nVHE/pKVM:
Because the host and the guest are both using TRFCR_EL1, trace will be
generated in guests depending on the same filter rules the host is
using. For example if the host is tracing userspace only, then guest
userspace trace will also be collected.
(This is further limited by whether TRBE is used because an issue
with TRBE means that it's completely disabled in nVHE guests, but it's
possible to have other tracing components.)
VHE:
With VHE, the host filters will be in TRFCR_EL2, but the filters in
TRFCR_EL1 will be active when the guest is running. Because we don't
write to TRFCR_EL1, guest trace will be completely disabled.
New behavior:
The guest filtering rules from the Perf session are now honored for both
nVHE and VHE modes. This is done by either writing to TRFCR_EL12 at the
start of the Perf session and doing nothing else further, or caching the
guest value and writing it at guest switch for nVHE. In pKVM, trace is
now be disabled for both protected and unprotected guests.
There is also an optimization where the SPE and Coresight drivers pass
their enabled state to KVM. This means in the common case KVM doesn't
have to touch any sysregs when the feature isn't in use.
Applies to kvmarm/next (25a8556b54007)
---
Changes since V6 [5]:
* Implement a better "do nothing" case where both the SPE and Coresight
drivers give the enabled state to KVM, allowing some register
reads to be dropped.
* Move the state and feature flags out of the vCPU into the per-CPU
host_debug_state.
* Simplify the switch logic by adding a new flag HOST_STATE_SWAP_TRFCR
and only storing a single TRFCR value.
* Rename vcpu flag macros to a more generic kvm_flag...
Changes since V5 [4]:
* Sort new sysreg entries by encoding
* Add a comment about sorting arch/arm64/tools/sysreg
* Warn on preemptible() before calling smp_processor_id()
* Pickup tags
* Change TRFCR_EL2 from SysregFields to Sysreg because it was only
used once
Changes since V4 [3]:
* Remove all V3 changes that made it work in pKVM and just disable
trace there instead
* Restore PMU host/hyp state sharing back to how it was
(kvm_pmu_update_vcpu_events())
* Simplify some of the duplication in the comments and function docs
* Add a WARN_ON_ONCE() if kvm_etm_set_guest_trfcr() is called when
the trace filtering feature doesn't exist.
* Split sysreg change into a tools update followed by the new register
addition
Changes since V3:
* Create a new shared area to store the host state instead of copying
it before each VCPU run
* Drop commit that moved SPE and trace registers from host_debug_state
into the kvm sysregs array because the guest values were never used
* Document kvm_etm_set_guest_trfcr()
* Guard kvm_etm_set_guest_trfcr() with a feature check
* Drop Mark B and Suzuki's review tags on the sysreg patch because it
turned out that broke the Perf build and needed some unconventional
changes to fix it (as in: to update the tools copy of the headers in
the same commit as the kernel changes)
Changes since V2:
* Add a new iflag to signify presence of FEAT_TRF and keep the
existing TRBE iflag. This fixes the issue where TRBLIMITR_EL1 was
being accessed even if TRBE didn't exist
* Reword a commit message
Changes since V1:
* Squashed all the arm64/tools/sysreg changes into the first commit
* Add a new commit to move SPE and TRBE regs into the kvm sysreg array
* Add a comment above the TRFCR global that it's per host CPU rather
than vcpu
Changes since nVHE RFC [1]:
* Re-write just in terms of the register value to be written for the
host and the guest. This removes some logic from the hyp code and
a value of kvm_vcpu_arch:trfcr_el1 = 0 no longer means "don't
restore".
* Remove all the conditional compilation and new files.
* Change the kvm_etm_update_vcpu_events macro to a function.
* Re-use DEBUG_STATE_SAVE_TRFCR so iflags don't need to be expanded
anymore.
* Expand the cover letter.
Changes since VHE v3 [2]:
* Use the same interface as nVHE mode so TRFCR_EL12 is now written by
kvm.
[1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/
[2]: https://lore.kernel.org/kvmarm/20230905102117.2011094-1-james.clark@arm.com/
[3]: https://lore.kernel.org/linux-arm-kernel/20240104162714.1062610-1-james.cla…
[4]: https://lore.kernel.org/all/20240220100924.2761706-1-james.clark@arm.com/
[5]: https://lore.kernel.org/linux-arm-kernel/20240226113044.228403-1-james.clar…
James Clark (12):
arm64/sysreg: Add a comment that the sysreg file should be sorted
tools: arm64: Update sysreg.h header files
arm64/sysreg/tools: Move TRFCR definitions to sysreg
KVM: arm64: Make vcpu flag macros more generic
KVM: arm64: Move SPE and TRBE flags to host data
KVM: arm64: Add flag for FEAT_TRF
KVM: arm64: arm_spe: Give SPE enabled state to KVM
KVM: arm64: Don't hit sysregs to see if SPE is enabled or not
KVM: arm64: coresight: Give TRBE enabled state to KVM
KVM: arm64: Don't hit sysregs to see if TRBE is enabled or not
KVM: arm64: Swap TRFCR on guest switch
coresight: Pass guest TRFCR value to KVM
arch/arm64/include/asm/kvm_host.h | 123 +++---
arch/arm64/include/asm/kvm_hyp.h | 2 +-
arch/arm64/include/asm/sysreg.h | 12 -
arch/arm64/kvm/arm.c | 3 -
arch/arm64/kvm/debug.c | 97 ++++-
arch/arm64/kvm/hyp/exception.c | 12 +-
arch/arm64/kvm/hyp/nvhe/debug-sr.c | 118 +++--
arch/arm64/kvm/hyp/nvhe/switch.c | 2 +-
arch/arm64/kvm/inject_fault.c | 4 +-
arch/arm64/kvm/mmio.c | 10 +-
arch/arm64/tools/sysreg | 38 ++
.../coresight/coresight-etm4x-core.c | 43 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
drivers/hwtracing/coresight/coresight-priv.h | 3 +
drivers/hwtracing/coresight/coresight-trbe.c | 15 +-
drivers/perf/arm_spe_pmu.c | 13 +-
tools/arch/arm64/include/asm/sysreg.h | 410 +++++++++++++++++-
tools/include/linux/kasan-tags.h | 15 +
18 files changed, 755 insertions(+), 167 deletions(-)
create mode 100644 tools/include/linux/kasan-tags.h
--
2.34.1
Hi
On 11/11/2024 14:12, Alexander Shishkin wrote:
> Uwe Kleine-König <u.kleine-koenig(a)baylibre.com> writes:
>
>> After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
>> return void") .remove() is (again) the right callback to implement for
>> platform drivers.
>>
>> Convert all platform drivers below drivers/hwtracing to use .remove(),
>> with the eventual goal to drop struct platform_driver::remove_new(). As
>> .remove() and .remove_new() have the same prototypes, conversion is done
>> by just changing the structure member name in the driver initializer.
>>
>> Also adapt some whitespace to make indention consistent.
>>
>> Signed-off-by: Uwe Kleine-König <u.kleine-koenig(a)baylibre.com>
>
> Acked-by: Alexander Shishkin <alexander.shishkin(a)linux.intel.com>
>
>> ---
>> Hello,
>>
>> I did a single patch for all of drivers/hwtracing. While I usually
>> prefer to do one logical change per patch, this seems to be
>> overengineering here as the individual changes are really trivial and
>> shouldn't be much in the way for stable backports. But I'll happily
>> split the patch if you prefer it split. Maybe split for coresight vs.
>> intel_th? Also if you object the indentation stuff, I can rework that.
>
> I'm fine with it as is.
>
>> This is based on today's next, if conflicts arise when you apply it at
>> some later time and don't want to resolve them, feel free to just drop
>> the changes to the conflicting files. I'll notice and followup at a
>> later time then. Or ask me for a fixed resend. (Having said that, I
>> recommend b4 am -3 + git am -3 which should resolve most conflicts just
>> fine.)
>
> Does anybody want to pick this up or should I? I'm fine either way, but
> if there are any conflicts they won't be from my end of things, so it
> might make sense to take it via the coresight path.
I am happy to take them via coresight tree and queue them for v6.14
Suzuki
>
> Thanks,
> --
> Alex
This patch series is rebased on coresight-next-v6.12.rc4
* Patches 1 & 2 adds support for allocation of trace buffer pages from reserved RAM
* Patches 3 & 4 adds support for saving metadata at the time of kernel panic
* Patch 5 adds support for reading trace data captured at the time of panic
* Patches 6 & 7 adds support for disabling coresight blocks at the time of panic
* Patch 8: Gives the full description about this feature as part of documentation
V10 is posted here,
https://lore.kernel.org/linux-arm-kernel/20240916103437.226816-1-lcherian@m…
Changelog from v10:
* Converted all csdev_access_* to readl functions in tmc_panic_sync_*
* Added "tmc" prefix for register snapshots in struct tmc_crash_metadata
* Converted dev_info to dev_dbg in panic handlers
* Converted dsb to dmb in panic handlers
* Fixed marking metadata as invalid when a user is trying to use the
reserved buffer. Earlier this was wrongly set at the time of reading
reserved trace buffer.
* Moved common validation checks to is_tmc_crashdata_valid and minor
code rearrangements for efficiency
* Got rid of sink specific prepare/unprepare invocations
* Got rid of full from struct tmc_resrv_buf
* While reading crashdata, size is now calculated from metdata instead
of relying on reserved buffer size populated by dtb
* Minor documenation fixes
Changelog from v9:
* Add common helper function of_tmc_get_reserved_resource_by_name
for better code reuse
* Reserved buffer validity and crashdata validity has been separated to
avoid interdependence
* New fields added to crash metadata: version, ffcr, ffsr, mode
* Version checks added for metadata validation
* Special file /dev/crash_tmc_xxx would be available only when
crash metadata is valid
* Removed READ_CRASHDATA mode meant for special casing crashdata reads.
Instead, dedicated read function added for crashdata reads from reserved
buffer which is common for both ETR and ETF sinks as well.
* Documentation added to Documentation/tracing/coresight/panic.rst
Changelog from v8:
* Added missing exit path on error in __tmc_probe.
* Few whitespace fixes, checkpatch fixes.
* With perf sessions honouring stop_on_flush sysfs attribute,
removed redundant variable stop_on_flush_en.
Changelog from v7:
* Fixed breakage on perf test -vvvv "arm coresight".
No issues seen with and without "resrv" buffer mode
* Moved the crashdev registration into a separate function.
* Removed redundant variable in tmc_etr_setup_crashdata_buf
* Avoided a redundant memcpy in tmc_panic_sync_etf.
* Tested kernel panic with trace session started uisng perf.
Please see the title "Perf based testing" below for details.
For this, stop_on_flush sysfs attribute is taken into
consideration while starting perf sessions as well.
Changelog from v6:
* Added special device files for reading crashdata, so that
read_prevboot mode flag is removed.
* Added new sysfs TMC device attribute, stop_on_flush.
Stop on flush trigger event is disabled by default.
User need to explicitly enable this from sysfs for panic stop
to work.
* Address parameter for panicstop ETM configuration is
chosen as kernel "panic" address by default.
* Added missing tmc_wait_for_tmcready during panic handling
* Few other misc code rearrangements.
Changelog from v5:
* Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP
* Fixed a memory leak while reading data from /dev/tmc_etrx in
READ_PREVBOOT mode
* Tested reading trace data from crashdump kernel
Changelog from v4:
* Device tree binding
- Description is made more explicit on the usage of reserved memory
region
- Mismatch in memory region names in dts binding and driver fixed
- Removed "mem" suffix from the memory region names
* Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata",
since it contains more than register snapshot.
Related variables are named accordingly.
* Rename struct tmc_drvdata members
resrv_buf -> crash_tbuf
metadata -> crash_mdata
* Size field in metadata refers to RSZ register and hence indicates the
size in 32 bit words. ETR metadata follows this convention, the same
has been extended to ETF metadata as well.
* Added crc32 for more robust metadata and tracedata validation.
* Added/modified dev_dbg messages during metadata validation
* Fixed a typo in patch 5 commit description
Changelog from v3:
* Converted the Coresight ETM driver change to a named configuration.
RFC tag has been removed with this change.
* Fixed yaml issues reported by "make dt_binding_check"
* Added names for reserved memory regions 0 and 1
* Added prevalidation checks for metadata processing
* Fixed a regression introduced in RFC v3
- TMC Status register was getting saved wrongly
* Reverted memremap attribute changes from _WB to _WC to match
with the dma map attributes
* Introduced reserved buffer mode specific .sync op.
This fixes a possible crash when reserved buffer mode was used in
normal trace capture, due to unwanted dma maintenance operations.
Linu Cherian (8):
dt-bindings: arm: coresight-tmc: Add "memory-region" property
coresight: tmc-etr: Add support to use reserved trace memory
coresight: core: Add provision for panic callbacks
coresight: tmc: Enable panic sync handling
coresight: tmc: Add support for reading crash data
coresight: tmc: Stop trace capture on FlIn
coresight: config: Add preloaded configuration
Documentation: coresight: Panic support
.../bindings/arm/arm,coresight-tmc.yaml | 26 ++
Documentation/trace/coresight/panic.rst | 356 ++++++++++++++++++
drivers/hwtracing/coresight/Makefile | 2 +-
.../coresight/coresight-cfg-preload.c | 2 +
.../coresight/coresight-cfg-preload.h | 2 +
.../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++
drivers/hwtracing/coresight/coresight-core.c | 42 +++
.../hwtracing/coresight/coresight-tmc-core.c | 326 +++++++++++++++-
.../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++-
.../hwtracing/coresight/coresight-tmc-etr.c | 181 ++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 104 +++++
include/linux/coresight.h | 12 +
12 files changed, 1216 insertions(+), 12 deletions(-)
create mode 100644 Documentation/trace/coresight/panic.rst
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
--
2.34.1
Changes in V11:
- Corrected prefix.
- Fixed compile-time error for perf debug build by substituting in
the map__pgoff macro (trace_event_python.c).
Changes in V10:
- Removed errant space in patch file 0002. Passed 'git apply --check'
at perf-tools-next, 6.11.0-rc6.
- Added back missing prefixes.
Changes in V9:
- Removed V8 patch files 1/4 and 2/4.
- Modified set_sym_in_dict (trace-event-python.c) to add map_pgoff
in dictionary as-is without regard to MAPPING_IDENTITY. This patch
file is now patch 2/2.
Changes in V8:
- in arm-cs-trace-disasm.py, ensure map_pgoff is not converted to
string.
- Remove map_pgoff integer conversion in dso not found print
message.
Changes in V7:
- In arm-cs-trace-disasm.py, fix print message core dump resulting
from mixed type arithmetic.
- Modify CS_ETM_TRACE_ON filter to filter zero start_addr. The
CS_ETM_TRACE_ON message is changed to print only in verbose mode.
- Removed verbose mode only notification for start_addr/stop_addr
outside of dso address range.
Changes in V6:
- In arm-cs-trace-disasm.py, zero map_pgoff for kernel files. Add
map_pgoff to start/end address for dso not found message.
- Added "Reviewed-by" trailer for patches 1-3 previously reviewed
by Leo Yan in V4 and V5.
Changes in V5:
- In symbol-elf.c, branch to exit_close label if open file.
- In trace_event_python.c, correct indentation. set_sym_in_dict
call parameter "map_pgoff" renamed as "addr_map_pgoff" to
match local naming.
Changes in V4:
- In trace-event-python.c, fixed perf-tools-next merge problem.
Changes in V3:
- Rebased to linux-perf-tools branch.
- Squash symbol-elf.c and symbol.h into same commit.
- In map.c, merge dso__is_pie() call into existing if statement.
- In arm-cs-trace-disasm.py, remove debug artifacts.
Changes in V2:
- In dso__is_pie() (symbol-elf.c), Decrease indentation, add null pointer
checks per Leo Yan review.
Steve Clevenger (2):
perf script cs_etm: Add map_pgoff to python dictionary
perf script python: Adjust objdump start/end per map pgoff parameter
tools/perf/scripts/python/arm-cs-trace-disasm.py | 16 +++++++++++-----
.../util/scripting-engines/trace-event-python.c | 9 ++++++---
2 files changed, 17 insertions(+), 8 deletions(-)
--
2.44.0
Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit
MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB
subunit has the same number and usage of registers as CMB subunit.
Just like the CMB subunit, the MCMB subunit must be configured prior
to enablement. This series adds support for TPDM to configure the
MCMB subunit.
Once this series patches are applied properly, the new tpdm nodes for
should be observed at the tpdm path /sys/bus/coresight/devices/tpdm*
which supports MCMB subunit. All sysfs files of CMB subunit TPDM are
included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will
have new sysfs files to select and enable the lane.
Changes in V2:
1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) ||
tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support.
2. Embed mcmb_dataset struct into cmb struct.
3. Update the date and version in sysfs-bus-coresight-devices-tpdm
Mao Jinlong (1):
coresight-tpdm: Add MCMB dataset support
Tao Zhang (2):
coresight-tpdm: Add support to select lane
coresight-tpdm: Add support to enable the lane for MCMB TPDM
.../testing/sysfs-bus-coresight-devices-tpdm | 15 +++
drivers/hwtracing/coresight/coresight-tpda.c | 7 +-
drivers/hwtracing/coresight/coresight-tpdm.c | 124 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++--
4 files changed, 158 insertions(+), 21 deletions(-)
--
2.17.1
Some HW has static trace id which cannot be changed via
software programming. For this case, configure the trace id
in device tree with "arm,static-trace-id = <xxx>", and
call coresight_trace_id_get_static_system_id with the trace id value
in device probe function. The id will be reserved for the HW
all the time if the device is probed.
Changes since V5:
1. Remove the warn for staic id not available.
2. Drop the system_id if registering the coresight device fails.
3. Return busy when static id is not available in dummy driver.
Changes since V4:
1. Use fwnode_property_read_u32 in fwnode_property_read_u32.
2. Update date and version in sysfs-bus-coresight-devices-dummy-source
Changes since V3:
1. Adda new API function
int coresight_trace_id_get_system_static_id(int trace_id).
2. Use the term "static trace id" for these devices where
the hardware sets a non-programmable trace ID.
Changes since V2:
1. Change "trace-id" to "arm,trace-id".
2. Add trace id flag for getting preferred id or ODD id.
Changes since V1:
1. Add argument to coresight_trace_id_get_system_id for preferred id
instead of adding new function coresight_trace_id_reserve_system_id.
2. Add constraint to trace-id in dt-binding file.
Mao Jinlong (3):
dt-bindings: arm: Add arm,static-trace-id for coresight dummy source
coresight: Add support to get static id for system trace sources
coresight: dummy: Add static trace id support for dummy source
.../sysfs-bus-coresight-devices-dummy-source | 15 ++++
.../arm/arm,coresight-dummy-source.yaml | 6 ++
drivers/hwtracing/coresight/coresight-dummy.c | 81 ++++++++++++++++---
.../hwtracing/coresight/coresight-platform.c | 6 ++
.../hwtracing/coresight/coresight-trace-id.c | 39 ++++++---
.../hwtracing/coresight/coresight-trace-id.h | 9 +++
include/linux/coresight.h | 1 +
7 files changed, 137 insertions(+), 20 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
--
2.17.1