CoreSight August 2022

coresight@lists.linaro.org

11 participants
28 discussions

[PATCH v2 00/13] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on hardware enable, and freed on hardware disable. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks backward compatibility for perf record and perf report. Because the method for generating the AUXTRACE_INFO meta data has changed, using an older perf record will result in metadata that does not match the trace IDs used in the recorded trace data. This mismatch will cause subsequent decode to fail. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are no longer present in the metadata. This will mean older versions of perf report cannot decode the file. Applies to coresight/next [c06475910b52] Tested on DB410c Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: trace-id: update CoreSight core to use Trace ID API coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove unused legacy source Trace ID ops coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +--- .../hwtracing/coresight/coresight-etm-perf.c | 17 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 85 +++--- .../coresight/coresight-etm3x-sysfs.c | 28 +- .../coresight/coresight-etm4x-core.c | 65 ++++- .../coresight/coresight-etm4x-sysfs.c | 32 ++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +--- .../hwtracing/coresight/coresight-trace-id.c | 263 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 65 +++++ include/linux/coresight-pmu.h | 31 ++- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 31 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 + tools/perf/util/cs-etm.c | 220 +++++++++++++-- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 784 insertions(+), 207 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 2 months

Make Coresight Secure World Only

by finn.burmester＠student.uni-luebeck.de

Hey, I want to restrict access to the Coresight registers to the secure world, so the normal world OS can not tamper with the tracing. Is this generally possible, and if yes, how? I already tried to use the address space controller (TZC-400) with the memory-addresses of the registers, but that didn’t work, because it is only for protecting DDR-memory regions, as I later found out. Best regards Finn

2 years, 2 months

Re: [PATCH v8 1/2] drivers/coresight: Add UltraSoc System Memory Buffer driver

by hejunhao

On 2022/8/17 2:00, Randy Dunlap wrote: Hi Randy, Thanks for your comments. > Hi-- > > On 8/16/22 06:16, Junhao He wrote: >> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >> index 514a9b8086e3..4380eb1a0a73 100644 >> --- a/drivers/hwtracing/coresight/Kconfig >> +++ b/drivers/hwtracing/coresight/Kconfig >> @@ -201,4 +201,14 @@ config CORESIGHT_TRBE >> >> To compile this driver as a module, choose M here: the module will be >> called coresight-trbe. > Please insert a blank line here like it is done elsewhere. I will fix it in the next version. Thanks. >> +config ULTRASOC_SMB >> + tristate "Ultrasoc system memory buffer drivers" >> + depends on ACPI && ARM64 && CORESIGHT_LINKS_AND_SINKS >> + help >> + This driver provides support for the Ultrasoc system memory buffer (SMB). >> + SMB is responsible for receiving the trace data from Coresight ETM devices >> + and storing them to a system buffer. >> + >> + To compile this driver as a module, choose M here: the module will be >> + called ultrasoc-smb. >> endif > thanks. Regards, Junhao.

2 years, 3 months

[PATCH v8 0/2] Add support for UltraSoc System Memory Buffer

by Junhao He

Add support for UltraSoc System Memory Buffer. Change since v7: - Use the macros for register bit flags and numbers of resource. - Fix punctuation. - Update the Date tag and the KernelVersion tag in the document. - Link: https://lore.kernel.org/lkml/20220712091353.34540-1-hejunhao3@huawei.com/ Change since v6: - Modify the code style and driver description according to Suzuki's comment. - Modify configuration of "drvdata->reading", to void problems in open/read concurrency scenario. - Rename the macro of "SMB_FLOW_MASK". - Use the "handle->head" to determine the page number and offset. - Link: https://lore.kernel.org/linux-arm-kernel/20220606130223.57354-1-liuqi115@hu… Change since v5: - Address the comments from Suzuki, add some comments in SMB document, and modify configuration of "drvdata->reading", to void problems in multi-core concurrency scenario - Link: https://lore.kernel.org/linux-arm-kernel/20220416083953.52610-1-liuqi115@hu… Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - Link: https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link: https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi115@hu… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link: https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB drivers .../sysfs-bus-coresight-devices-ultra_smb | 31 + .../trace/coresight/ultrasoc-smb.rst | 80 +++ drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 636 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 115 ++++ 6 files changed, 873 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.33.0

2 years, 3 months

Regression with CTI driver on Arm Juno-r2 board

by Leo Yan

Hi Mike & all, [ + CoreSight Mailing List ] At my side, I found the perf cs-etm regression. When I execute cs-etm test with below commands: # perf test list ... 87: Check Arm CoreSight trace data recording and synthesized samples ... $ perf test -v 87 Then it's stuck and has no response. In the console, sometimes I can see the log: [ 94.248480] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: Apparently, there have lockup and introduces CPU stuck. But I didn't narrow down furthermore if is a hardware lockup or software lockup. After git bisect, it's narrowed down the regression is related to the commit: e7676a00bc52b994960f89b118b0d548e4542372 is the first bad commit commit e7676a00bc52b994960f89b118b0d548e4542372 Author: Mike Leach <mike.leach(a)linaro.org> Date: Wed Apr 13 22:49:25 2022 +0100 arm64: dts: juno: add CTI entries to device tree Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> I built Linux kernel with below commands: $KERNEL=/kernel/path $OUT=/build/out/path pushd $KERNEL make defconfig O=$OUT ./scripts/config --file $OUT/.config -e CONFIG_BPF_SYSCALL ./scripts/config --file $OUT/.config -e CONFIG_BPF_JIT_ALWAYS_ON ./scripts/config --file $OUT/.config -e CONFIG_TRACEPOINTS ./scripts/config --file $OUT/.config -e CONFIG_KPROBES ./scripts/config --file $OUT/.config -e CONFIG_UPROBES ./scripts/config --file $OUT/.config -e CONFIG_KRETPROBES ./scripts/config --file $OUT/.config -e CONFIG_PROC_KCORE ./scripts/config --file $OUT/.config -e CONFIG_NOP_TRACER ./scripts/config --file $OUT/.config -e CONFIG_TRACER_MAX_TRACE ./scripts/config --file $OUT/.config -e CONFIG_RING_BUFFER ./scripts/config --file $OUT/.config -e CONFIG_EVENT_TRACING ./scripts/config --file $OUT/.config -e CONFIG_CONTEXT_SWITCH_TRACER ./scripts/config --file $OUT/.config -e CONFIG_TRACING ./scripts/config --file $OUT/.config -e CONFIG_GENERIC_TRACER ./scripts/config --file $OUT/.config -e CONFIG_FTRACE ./scripts/config --file $OUT/.config -e CONFIG_FUNCTION_TRACER ./scripts/config --file $OUT/.config -e CONFIG_FUNCTION_GRAPH_TRACER ./scripts/config --file $OUT/.config -e CONFIG_SCHED_TRACER ./scripts/config --file $OUT/.config -e CONFIG_FTRACE_SYSCALLS ./scripts/config --file $OUT/.config -e CONFIG_TRACER_SNAPSHOT ./scripts/config --file $OUT/.config -e CONFIG_KPROBE_EVENTS ./scripts/config --file $OUT/.config -e CONFIG_UPROBE_EVENTS ./scripts/config --file $OUT/.config -e CONFIG_BPF_EVENTS ./scripts/config --file $OUT/.config -e CONFIG_DYNAMIC_EVENTS ./scripts/config --file $OUT/.config -e CONFIG_PROBE_EVENTS ./scripts/config --file $OUT/.config -e CONFIG_DYNAMIC_FTRACE ./scripts/config --file $OUT/.config -e CONFIG_PID_IN_CONTEXTIDR ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_LINKS_AND_SINKS ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_LINK_AND_SINK_TMC ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_CATU ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_SINK_TPIU ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_SINK_ETBV10 ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_SOURCE_ETM4X ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_STM ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_CPU_DEBUG ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_CTI ./scripts/config --file $OUT/.config -e CONFIG_CORESIGHT_CTI_INTEGRATION_REGS ./scripts/config --file $OUT/.config -e CONFIG_DEBUG_INFO ./scripts/config --file $OUT/.config -e CONFIG_DEBUG_INFO_DWARF5 ./scripts/config --file $OUT/.config -e CONFIG_DEBUG_INFO_BTF ./scripts/config --file $OUT/.config -d CONFIG_DEBUG_INFO_REDUCED yes "" | make oldconfig O=$OUT make -j `nproc` Image dtbs O=$OUT popd When I have some free time, will come back to dig more for it. If have any suggestion, please let me know, I am glad to try and test at my side. Thanks, Leo

2 years, 3 months

Re: [PATCH] coresight: Fix possible deadlock with lock dependency

by Mike Leach

Hi Sudeep, On Thu, 21 Jul 2022 at 14:03, Sudeep Holla <sudeep.holla(a)arm.com> wrote: > > With lockdeps enabled, we get the following warning: > > ====================================================== > WARNING: possible circular locking dependency detected > ------------------------------------------------------ > kworker/u12:1/53 is trying to acquire lock: > ffff80000adce220 (coresight_mutex){+.+.}-{4:4}, at: coresight_set_assoc_ectdev_mutex+0x3c/0x5c > but task is already holding lock: > ffff80000add1f60 (ect_mutex){+.+.}-{4:4}, at: cti_probe+0x318/0x394 > > which lock already depends on the new lock. > the existing dependency chain (in reverse order) is: > > -> #1 (ect_mutex){+.+.}-{4:4}: > __mutex_lock_common+0xd8/0xe60 > mutex_lock_nested+0x44/0x50 > cti_add_assoc_to_csdev+0x4c/0x184 > coresight_register+0x2f0/0x314 > tmc_probe+0x33c/0x414 > > -> #0 (coresight_mutex){+.+.}-{4:4}: > __lock_acquire+0x1a20/0x32d0 > lock_acquire+0x160/0x308 > __mutex_lock_common+0xd8/0xe60 > mutex_lock_nested+0x44/0x50 > coresight_set_assoc_ectdev_mutex+0x3c/0x5c > cti_update_conn_xrefs+0x6c/0xf8 > cti_probe+0x33c/0x394 > > other info that might help us debug this: > Possible unsafe locking scenario: > CPU0 CPU1 > ---- ---- > lock(ect_mutex); > lock(coresight_mutex); > lock(ect_mutex); > lock(coresight_mutex); > *** DEADLOCK *** > > 4 locks held by kworker/u12:1/53: > #0: ((wq_completion)events_unbound){+.+.}-{0:0}, at: process_one_work+0x1fc/0x63c > #1: (deferred_probe_work){+.+.}-{0:0}, at: process_one_work+0x228/0x63c > #2: (&dev->mutex){....}-{4:4}, at: __device_attach+0x48/0x1a8 > #3: (ect_mutex){+.+.}-{4:4}, at: cti_probe+0x318/0x394 > > To fix the same, call cti_add_assoc_to_csdev without the holding > coresight_mutex and confine the locking while setting the associated > ect / cti device using coresight_set_assoc_ectdev_mutex(). > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 7 ++++--- > drivers/hwtracing/coresight/coresight-cti-core.c | 5 +++-- > 2 files changed, 7 insertions(+), 5 deletions(-) > > Hi, > > I am not sure if I missed to consider something, but this is something > I think could be the fix. > > Regards, > Sudeep > I have been running with lockdep testing coresight for a number of weeks now, without encountering the same issue with CTIs. That said, I am on a DB410, and the code in question is designed to take different paths depending on whether the CTI or other device is discovered first, so this could well be something different in the discovery order between juno and DB410. The change looks perfectly fine to me. As such: Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 1edfec1e9d18..275b4dce8401 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -1659,14 +1659,15 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > ret = coresight_fixup_device_conns(csdev); > if (!ret) > ret = coresight_fixup_orphan_conns(csdev); > - if (!ret && cti_assoc_ops && cti_assoc_ops->add) > - cti_assoc_ops->add(csdev); > > out_unlock: > mutex_unlock(&coresight_mutex); > /* Success */ > - if (!ret) > + if (!ret) { > + if (cti_assoc_ops && cti_assoc_ops->add) > + cti_assoc_ops->add(csdev); > return csdev; > + } > > /* Unregister the device if needed */ > if (registered) { > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8988b2ed2ea6..1be92342b5b9 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -541,7 +541,7 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name, > /* > * Search the cti list to add an associated CTI into the supplied CS device > * This will set the association if CTI declared before the CS device. > - * (called from coresight_register() with coresight_mutex locked). > + * (called from coresight_register() without coresight_mutex locked). > */ > static void cti_add_assoc_to_csdev(struct coresight_device *csdev) > { > @@ -569,7 +569,8 @@ static void cti_add_assoc_to_csdev(struct coresight_device *csdev) > * if we found a matching csdev then update the ECT > * association pointer for the device with this CTI. > */ > - csdev->ect_dev = ect_item->csdev; > + coresight_set_assoc_ectdev_mutex(csdev->ect_dev, > + ect_item->csdev); > break; > } > } > -- > 2.37.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 3 months

[PATCH v7 00/14] perf: test: Add trace data quality tests for CoreSight

by carsten.haitzler＠foss.arm.com

From: Carsten Haitzler <carsten.haitzler(a)arm.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 158 +++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- .../perf/Documentation/perf-arm-coresight.txt | 5 + tools/perf/Makefile.config | 2 + tools/perf/Makefile.perf | 17 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 14 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 30 files changed, 1094 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/perf-arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 3 months

[PATCH v6 00/14] perf: test: Add trace data quality tests for CoreSight

by carsten.haitzler＠foss.arm.com

From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (Rasterman) (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 158 +++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- .../perf/Documentation/perf-arm-coresight.txt | 5 + tools/perf/Makefile.config | 2 + tools/perf/Makefile.perf | 17 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 14 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 30 files changed, 1094 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/perf-arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 3 months

[PATCH v5 00/14] A patch series improving data quality of perf test for CoreSight

by carsten.haitzler＠foss.arm.com

From: "Carsten Haitzler (Rasterman)" <raster(a)rasterman.com> This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (Rasterman) (14): perf test: Refactor shell tests allowing subdirs perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 160 ++++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- tools/perf/Documentation/arm-coresight.txt | 5 + tools/perf/Makefile.perf | 18 +- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 ++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 + tools/perf/tests/builtin-test.c | 152 ++----------- tools/perf/tests/shell/coresight/Makefile | 30 +++ .../tests/shell/coresight/Makefile.miniconfig | 24 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 +++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 +++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 +++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 +++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 ++ .../coresight/thread_loop_check_tid_2.sh | 19 ++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 +++ .../unroll_loop_thread/unroll_loop_thread.c | 74 +++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++ 29 files changed, 1105 insertions(+), 139 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/arm-coresight.txt create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 3 months

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support

by Anshuman Khandual

On 9/24/21 15:36, Tao Zhang wrote: > Add the basic coresight components found on Qualcomm SM8250 Soc. The > basic coresight components include ETF, ETMs,STM and the related > funnels. Hello, Seems like this patch never merged mainline, what happened ? This change is required to enable coresight devices on RB5 platform. - Anshuman > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > --- > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 439 +++++++++++++++++++++++++++++++ > 1 file changed, 439 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > index 5f41de2..1e1579a 100644 > --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > @@ -223,6 +223,445 @@ > regulator-max-microvolt = <1800000>; > regulator-always-on; > }; > + > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x06002000 0 0x1000>, > + <0 0x16280000 0 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06041000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6042000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06042000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@4 { > + reg = <4>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6b04000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + arm,primecell-periphid = <0x000bb908>; > + > + reg = <0 0x6b04000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + swao_funnel_in7: endpoint { > + slave-mode; > + remote-endpoint= > + <&merg_funnel_out>; > + }; > + }; > + }; > + > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06045000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merg_funnel_out: endpoint { > + remote-endpoint = <&swao_funnel_in7>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + etf@6b05000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x06b05000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07040000 0 0x1000>; > + > + cpu = <&CPU0>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07140000 0 0x1000>; > + > + cpu = <&CPU1>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07240000 0 0x1000>; > + > + cpu = <&CPU2>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07340000 0 0x1000>; > + > + cpu = <&CPU3>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07440000 0 0x1000>; > + > + cpu = <&CPU4>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07540000 0 0x1000>; > + > + cpu = <&CPU5>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07640000 0 0x1000>; > + > + cpu = <&CPU6>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07740000 0 0x1000>; > + > + cpu = <&CPU7>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07800000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07810000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port { > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > }; > > &adsp {

2 years, 3 months

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