CoreSight May 2022

coresight@lists.linaro.org

11 participants
26 discussions

[PATCH 1/3] perf test: Shell - Limit to only run executable scripts in tests

by carsten.haitzler＠foss.arm.com

From: Carsten Haitzler <carsten.haitzler(a)arm.com> Perf test's shell runner will just run everything in the tests directory (as long as it's not another directory or does not begin with a dot), but sometimes you find files in there that are not shell scripts - perf.data output for example if you do some testing and then the next time you run perf test it tries to run these. Check the files are executable so they are actually intended to be test scripts and not just some "random junk" files there. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> --- tools/perf/tests/builtin-test.c | 4 +++- tools/perf/util/path.c | 14 +++++++++++++- tools/perf/util/path.h | 1 + 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index fac3717d9ba1..3c34cb766724 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -296,7 +296,9 @@ static const char *shell_test__description(char *description, size_t size, #define for_each_shell_test(entlist, nr, base, ent) \ for (int __i = 0; __i < nr && (ent = entlist[__i]); __i++) \ - if (!is_directory(base, ent) && ent->d_name[0] != '.') + if (!is_directory(base, ent) && \ + is_executable_file(base, ent) && \ + ent->d_name[0] != '.') static const char *shell_tests__dir(char *path, size_t size) { diff --git a/tools/perf/util/path.c b/tools/perf/util/path.c index caed0336429f..ce80b79be103 100644 --- a/tools/perf/util/path.c +++ b/tools/perf/util/path.c @@ -86,9 +86,21 @@ bool is_directory(const char *base_path, const struct dirent *dent) char path[PATH_MAX]; struct stat st; - sprintf(path, "%s/%s", base_path, dent->d_name); + snprintf(path, sizeof(path), "%s/%s", base_path, dent->d_name); if (stat(path, &st)) return false; return S_ISDIR(st.st_mode); } + +bool is_executable_file(const char *base_path, const struct dirent *dent) +{ + char path[PATH_MAX]; + struct stat st; + + snprintf(path, sizeof(path), "%s/%s", base_path, dent->d_name); + if (stat(path, &st)) + return false; + + return !S_ISDIR(st.st_mode) && (st.st_mode & S_IXUSR); +} diff --git a/tools/perf/util/path.h b/tools/perf/util/path.h index 083429b7efa3..d94902c22222 100644 --- a/tools/perf/util/path.h +++ b/tools/perf/util/path.h @@ -12,5 +12,6 @@ int path__join3(char *bf, size_t size, const char *path1, const char *path2, con bool is_regular_file(const char *file); bool is_directory(const char *base_path, const struct dirent *dent); +bool is_executable_file(const char *base_path, const struct dirent *dent); #endif /* _PERF_PATH_H */ -- 2.32.0

2 years, 5 months

[PATCH v2 1/2] coresight: etm4x: Expose default timestamp source in sysfs

by German Gomez

Add a new sysfs interface in /sys/bus/coresight/devices/etm<N>/ts_source indicating the configured timestamp source when the ETM device driver was probed. The perf tool will use this information to detect if the trace data timestamp matches the kernel time, enabling correlation of CoreSight trace with perf events. Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: German Gomez <german.gomez(a)arm.com> Reviewed-by: Leo Yan <leo.yan(a)linaro.org> --- v1: - https://lore.kernel.org/all/20220429123100.268059-2-german.gomez@arm.com/ v2: - Inline etmv4_to_ts_source() function. - Collect review tag from Leo. --- arch/arm64/include/asm/sysreg.h | 1 + .../coresight/coresight-etm4x-sysfs.c | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 38508e507d73a..263a7bee06f9a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1146,6 +1146,7 @@ #define SYS_MPIDR_SAFE_VAL (BIT(31)) #define TRFCR_ELx_TS_SHIFT 5 +#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index a0640fa5c55bd..2a48827a4e135 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2264,6 +2264,34 @@ static ssize_t cpu_show(struct device *dev, } static DEVICE_ATTR_RO(cpu); +static ssize_t ts_source_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (!drvdata->trfcr) { + val = -1; + goto out; + } + + switch (drvdata->trfcr & TRFCR_ELx_TS_MASK) { + case TRFCR_ELx_TS_VIRTUAL: + case TRFCR_ELx_TS_GUEST_PHYSICAL: + case TRFCR_ELx_TS_PHYSICAL: + val = FIELD_GET(TRFCR_ELx_TS_MASK, drvdata->trfcr); + break; + default: + val = -1; + break; + } + +out: + return sysfs_emit(buf, "%d\n", val); +} +static DEVICE_ATTR_RO(ts_source); + static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_nr_pe_cmp.attr, &dev_attr_nr_addr_cmp.attr, @@ -2318,6 +2346,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_vmid_val.attr, &dev_attr_vmid_masks.attr, &dev_attr_cpu.attr, + &dev_attr_ts_source.attr, NULL, }; -- 2.25.1

2 years, 5 months

[PATCH v7 00/10] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series "coresight: Add new API to allocate trace source ID values". https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220308205000.… Changes from V6: 1. Update the commit title and move the changes to right place which is sorted by address for dtsi changes. -- Konrad Dybcio <konrad.dybcio(a)somainline.org> Mao Jinlong (10): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add coresight components arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/coresight-tpda.yaml | 119 ++++ .../bindings/arm/coresight-tpdm.yaml | 99 +++ .../devicetree/bindings/arm/coresight.txt | 7 + MAINTAINERS | 2 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 658 ++++++++++++++++++ drivers/hwtracing/coresight/Kconfig | 24 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 201 ++++++ drivers/hwtracing/coresight/coresight-tpda.h | 33 + drivers/hwtracing/coresight/coresight-tpdm.c | 258 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 63 ++ include/linux/coresight.h | 1 + 14 files changed, 1510 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

2 years, 5 months

[PATCH v3 0/5] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load and unload are provided to in the configurations group to implement the load functionality. Routines to generate binary configuration files are supplied in ./tools/coresight. Example generator and reader applications are provided. Tools may be cross compiled or built for use on host system. Documentation is updated to describe feature usage. Changes since v2: 1) Rebased & tested oo coresight/next - 5.18-rc2 2) Moved coresight config generator and reader programs from samples to tools/coresight. Docs updated to match. (suggested by Mathieu) 3) userspace builds now use userspace headers from tools/... 4) Other minor fixes from Mathieu's review. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (5): coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: tools: Add config file write and reader tools Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 166 +++++- MAINTAINERS | 2 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 475 ++++++++++++++++++ .../coresight/coresight-config-file.h | 126 +++++ .../hwtracing/coresight/coresight-config.h | 27 + .../coresight/coresight-syscfg-configfs.c | 91 ++++ .../hwtracing/coresight/coresight-syscfg.c | 37 ++ .../hwtracing/coresight/coresight-syscfg.h | 2 + tools/coresight/Makefile | 51 ++ tools/coresight/coresight-cfg-bufw.c | 303 +++++++++++ tools/coresight/coresight-cfg-bufw.h | 26 + tools/coresight/coresight-cfg-example1.c | 65 +++ tools/coresight/coresight-cfg-examples.h | 27 + tools/coresight/coresight-cfg-file-read.c | 197 ++++++++ tools/coresight/coresight-cfg-filegen.c | 58 +++ tools/include/uapi/coresight-config-uapi.h | 76 +++ 17 files changed, 1724 insertions(+), 7 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 tools/coresight/Makefile create mode 100644 tools/coresight/coresight-cfg-bufw.c create mode 100644 tools/coresight/coresight-cfg-bufw.h create mode 100644 tools/coresight/coresight-cfg-example1.c create mode 100644 tools/coresight/coresight-cfg-examples.h create mode 100644 tools/coresight/coresight-cfg-file-read.c create mode 100644 tools/coresight/coresight-cfg-filegen.c create mode 100644 tools/include/uapi/coresight-config-uapi.h -- 2.17.1

2 years, 5 months

[PATCH] coresight: configfs: Fix unload of configurations on module exit

by Mike Leach

Any loaded configurations must be correctly unloaded on coresight module exit, or issues can arise with nested locking in the configfs directory code if built with CONFIG_LOCKDEP. Prior to this patch, the preloaded configuration configfs directory entries were being unloaded by the recursive code in configfs_unregister_subsystem(). However, when built with CONFIG_LOCKDEP, this caused a nested lock warning, which was not mitigated by the LOCKDEP dependent code in fs/configfs/dir.c designed to prevent this, due to the different directory levels for the root of the directory being removed. As the preloaded (and all other) configurations are registered after configfs_register_subsystem(), we now explicitly unload them before the call to configfs_unregister_subsystem(). The new routine cscfg_unload_cfgs_on_exit() iterates through the load owner list to unload any remaining configurations that were not unloaded by the user before the module exits. This covers both the CSCFG_OWNER_PRELOAD and CSCFG_OWNER_MODULE owner types, and will be extended to cover future load owner types for CoreSight configurations. Applies to coresight/next Fixes: eb2ec49606c2 ("coresight: syscfg: Update load API for config loadable modules") Reported-by: Suzuki Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- .../hwtracing/coresight/coresight-syscfg.c | 57 +++++++++++++++++-- 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 11850fd8c3b5..75df0f865355 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -1056,14 +1056,61 @@ static int cscfg_create_device(void) return err; } -static void cscfg_clear_device(void) +/* + * Loading and unloading is generally on user discretion. + * If exiting due to coresight module unload, we need to unload any configurations that remain, + * before we unregister the configfs intrastructure. + * + * Do this by walking the load_owner list and taking appropriate action, depending on the load + * owner type. + * + * called with the cscfg_mutex held + */ + +#define LOADABLE_MOD_ERR "cscfg: ERROR - a loadable module failed to unload configs on exit\n" + +static void cscfg_unload_cfgs_on_exit(void) { - struct cscfg_config_desc *cfg_desc; + struct cscfg_load_owner_info *owner_info = NULL; - mutex_lock(&cscfg_mutex); - list_for_each_entry(cfg_desc, &cscfg_mgr->config_desc_list, item) { - etm_perf_del_symlink_cscfg(cfg_desc); + while (!list_empty(&cscfg_mgr->load_order_list)) { + + /* remove in reverse order of loading */ + owner_info = list_last_entry(&cscfg_mgr->load_order_list, + struct cscfg_load_owner_info, item); + + /* action according to type */ + switch (owner_info->type) { + case CSCFG_OWNER_PRELOAD: + /* + * preloaded descriptors are statically allocated in + * this module - just need to unload dynamic items from + * csdev lists, and remove from configfs directories. + */ + pr_info("cscfg: unloading preloaded configurations\n"); + cscfg_unload_owned_cfgs_feats(owner_info); + break; + + case CSCFG_OWNER_MODULE: + /* + * this is an error - the loadable module must have been unloaded prior + * to the coresight module unload. Therefore that module has not + * correctly unloaded configs in its own exit code. + * Nothing to do other than emit an error string. + */ + pr_err(LOADABLE_MOD_ERR); + break; + } + + /* remove from load order list */ + list_del(&owner_info->item); } +} + +static void cscfg_clear_device(void) +{ + mutex_lock(&cscfg_mutex); + cscfg_unload_cfgs_on_exit(); cscfg_configfs_release(cscfg_mgr); device_unregister(cscfg_device()); mutex_unlock(&cscfg_mutex); -- 2.17.1

2 years, 5 months

[PATCH v6 0/2] perf script python: Add script for CoreSight disassembly

by Leo Yan

This patch set is to add CoreSight disassembly script, the python script can dump assembly, source line and symbols for humans inspecting. The first patch changes python script engine to expose more information for DSO and maps, so it's helpful for disassembly with objdump program. The second patch is to introduce the python script for CoreSight trace data disassembly for branch samples. It also can dump source line and symbol info for instruction samples. This patch set has been tested on Arm64 Juno board: # perf script -s scripts/python/arm-cs-trace-disasm.py ... main 6728/6728 [0004] 0.000000000 main+0x40 /root/coresight_test/main.c 15 for (i = 0; i < 10000; i++) { main 6728/6728 [0004] 0.000000000 main+0x20 /root/coresight_test/main.c 16 val = lib_loop_test(100); main 6728/6728 [0004] 0.000000000 lib_loop_test@plt+0xc /root/coresight_test/main main 6728/6728 [0004] 0.000000000 lib_loop_test+0xc /root/coresight_test/libcstest.c 8 for (i = 0; i < 5; i++) main 6728/6728 [0004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [0004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [0004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [0004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [0004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [0004] 0.000000000 lib_loop_test+0x3c /root/coresight_test/libcstest.c 12 } ... # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d llvm-objdump-11 -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3198 <etm4_enable_hw>: ffff800008eb3310: c0 38 00 35 cbnz w0, 0xffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: 9f 3f 03 d5 dsb sy ffff800008eb3318: df 3f 03 d5 isb ffff800008eb331c: f5 5b 42 a9 ldp x21, x22, [sp, #32] ffff800008eb3320: fb 73 45 a9 ldp x27, x28, [sp, #80] ffff800008eb3324: e0 82 40 39 ldrb w0, [x23, #32] ffff800008eb3328: 60 00 00 34 cbz w0, 0xffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: e0 03 19 aa mov x0, x25 ffff800008eb3330: 8c fe ff 97 bl 0xffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: 1f 20 03 d5 nop ffff800008eb2d64: 1f 20 03 d5 nop ffff800008eb2d68: 3f 23 03 d5 hint #25 ffff800008eb2d6c: 00 00 40 f9 ldr x0, [x0] ffff800008eb2d70: 9f 3f 03 d5 dsb sy ffff800008eb2d74: 00 c0 3e 91 add x0, x0, #4016 ffff800008eb2d78: 1f 00 00 b9 str wzr, [x0] ffff800008eb2d7c: bf 23 03 d5 hint #29 ffff800008eb2d80: c0 03 5f d6 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d objdump -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3310 <etm4_enable_hw+0x178>: ffff800008eb3310: 350038c0 cbnz w0, ffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: d5033f9f dsb sy ffff800008eb3318: d5033fdf isb ffff800008eb331c: a9425bf5 ldp x21, x22, [sp, #32] ffff800008eb3320: a94573fb ldp x27, x28, [sp, #80] ffff800008eb3324: 394082e0 ldrb w0, [x23, #32] ffff800008eb3328: 34000060 cbz w0, ffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: aa1903e0 mov x0, x25 ffff800008eb3330: 97fffe8c bl ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: d503201f nop ffff800008eb2d64: d503201f nop ffff800008eb2d68: d503233f paciasp ffff800008eb2d6c: f9400000 ldr x0, [x0] ffff800008eb2d70: d5033f9f dsb sy ffff800008eb2d74: 913ec000 add x0, x0, #0xfb0 ffff800008eb2d78: b900001f str wzr, [x0] ffff800008eb2d7c: d50323bf autiasp ffff800008eb2d80: d65f03c0 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 Changes from v5: * Updated script for using f-string format (Ian); * Added Adrian's review tag for patch 01; * Fixed the issue for printing souce code line; * Fixed several issues for using python3 (dictionary index, decode output for 'utf-8'). Changes from v4: * Enhanced python script engine for DSO and map infos; * Rewrote the python script, added support for symbol and source line dumping. Leo Yan (2): perf scripting python: Expose dso and map information perf scripts python: Support Arm CoreSight trace data disassembly .../scripts/python/arm-cs-trace-disasm.py | 272 ++++++++++++++++++ .../scripting-engines/trace-event-python.c | 21 +- 2 files changed, 289 insertions(+), 4 deletions(-) create mode 100755 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.25.1

2 years, 5 months

[PATCH v3 0/4] coresight: Add config flag to enable branch broadcast

by James Clark

Apologies for the delay. Changes since v2: * Pick up some of Mike's review tags * Add a comment explaining rationale for not opening the event when BB isn't supported * Extend docs to say that Perf doesn't support decode when binaries are modified * Drop Perf side patches that were already merged Thanks James James Clark (4): coresight: Add config flag to enable branch broadcast Documentation: coresight: Turn numbered subsections into real subsections Documentation: coresight: Link config options to existing documentation Documentation: coresight: Expand branch broadcast documentation .../coresight/coresight-etm4x-reference.rst | 17 +++++- Documentation/trace/coresight/coresight.rst | 56 +++++++++++++++++-- .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 14 +++++ include/linux/coresight-pmu.h | 2 + 5 files changed, 85 insertions(+), 6 deletions(-) -- 2.28.0

2 years, 5 months

Re: arm coresight driver

by Mathieu Poirier

Hi Chenkai, I am taking the liberty of CC'ing the coresight mailing list so that people with more experience with the HW implementation can chime in. On Tue, 24 May 2022 at 05:07, 陈凯 <chenkai.system(a)bytedance.com> wrote: > > Dear Poirier, > I‘m recently read the Linux driver of coresight, I have a question for you about the coresight driver ; That is a lot of reading. > I have a SOC(without arm core) ，in which we integrate the ARM CoreSight; Interesting. > Is the CoreSight driver still compatible for the soc without ETM，beacuse SOC donot include arm core； > and look forwarding to your replay. > The coresight framework does not specifically need an ETM device to work and will transport traces generated by any kind of source that comply with the specification. But you will need to supply your own decoder in the perf tools if you want to take advantage of the perf infrastructure. > > Best regards， > ChenKai

2 years, 5 months

Re: [PATCH v7 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions

by Jinlong Mao

Thanks Rob and Suzuki for the review. I will fix the warning and update in next version. On 5/23/2022 10:24 PM, Rob Herring wrote: > On Mon, May 23, 2022 at 4:44 AM Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: >> Cc: Rob Herring >> > Will or will not have any effect... > > Please use get_maintainers.pl and send your patches to the right > lists/maintainers. DT patches only get reviewed if sent to DT list. So > please resend to the DT list. But before you do, I can tell this > binding hasn't been tested so fix all the warnings first. > > Rob > >> >> On 09/05/2022 14:39, Mao Jinlong wrote: >>> Adds new coresight-tpda.yaml file describing the bindings required >>> to define tpda in the device trees. >>> >>> Reviewed-by: Mike Leach <mike.leach(a)linaro.org> >>> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >>> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >>> --- >>> .../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++ >>> MAINTAINERS | 1 + >>> 2 files changed, 120 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> new file mode 100644 >>> index 000000000000..4948ac13e7f8 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> @@ -0,0 +1,119 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >>> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Trace, Profiling and Diagnostics Aggregator - TPDA >>> + >>> +description: | >>> + TPDAs are responsible for packetization and timestamping of data sets >>> + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or >>> + more attached TPDM and pushing the resultant (packetized) data out a >>> + master ATB interface. Performing an arbitrated ATB interleaving (funneling) >>> + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). >>> + >>> +maintainers: >>> + - Mao Jinlong <quic_jinlmao(a)quicinc.com> >>> + - Tao Zhang <quic_taozha(a)quicinc.com> >>> + >>> +properties: >>> + $nodename: >>> + pattern: "^tpda(@[0-9a-f]+)$" >>> + compatible: >>> + items: >>> + - const: qcom,coresight-tpda >>> + - const: arm,primecell >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + clocks: >>> + maxItems: 1 >>> + >>> + clock-names: >>> + items: >>> + - const: apb_pclk >>> + >>> + in-ports: >>> + type: object >>> + description: | >>> + Input connections from TPDM to TPDA >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >> --->8--- >>> + properties: >>> + '#address-cells': >>> + const: 1 >>> + >>> + '#size-cells': >>> + const: 0 >>> + >>> + patternProperties: >>> + "^port@[0-9a-f]+$": >>> + type: object >>> + required: >>> + - reg >>> + >>> + required: >>> + - '#size-cells' >>> + - '#address-cells' >> ---8<--- >> >> I believe the above snippet is not needed and is covered by the generic >> ports. >> >> >>> + >>> + out-ports: >>> + type: object >>> + description: | >>> + Output connections from the TPDA to legacy CoreSight trace bus. >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >>> + properties: >>> + port: >>> + description: >>> + Output connection from the TPDA to legacy CoreSight Trace bus. >>> + $ref: /schemas/graph.yaml#/properties/port >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - clocks >>> + - clock-names >>> + - in-ports >>> + - out-ports >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + # minimum tpda definition. >>> + - | >>> + tpda@6004000 { >>> + compatible = "qcom,coresight-tpda", "arm,primecell"; >>> + reg = <0x6004000 0x1000>; >>> + >>> + qcom,tpda-atid = <65>; >>> + >>> + clocks = <&aoss_qmp>; >>> + clock-names = "apb_pclk"; >>> + >>> + in-ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + tpda_qdss_0_in_tpdm_dcc: endpoint { >>> + remote-endpoint = >>> + <&tpdm_dcc_out_tpda_qdss_0>; >>> + }; >>> + }; >>> + }; >>> + >>> + out-ports { >>> + port { >>> + tpda_qdss_out_funnel_in0: endpoint { >>> + remote-endpoint = >>> + <&funnel_in0_in_tpda_qdss>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> +... >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index 28d32b3f3f5c..5d2d8c0ee340 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -1978,6 +1978,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git >>> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* >>> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt >>> F: Documentation/devicetree/bindings/arm/coresight-cti.yaml >>> +F: Documentation/devicetree/bindings/arm/coresight-tpda.yaml >>> F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml >>> F: Documentation/devicetree/bindings/arm/coresight.txt >>> F: Documentation/devicetree/bindings/arm/ete.yaml >> Otherwise looks good to me. >> >> Suzuki

2 years, 5 months

Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT schema

by Suzuki K Poulose

Hi Rob, Thanks a lot for converting these to yaml. Some minor comments below. In general, the "clocks" and "clock-names" are optional (e.g, for etm4 with system register access). On 20/05/2022 22:44, Rob Herring wrote: > Each CoreSight component has slightly different requirements and > nothing applies to every component, so each CoreSight component has its > own schema document. > > Signed-off-by: Rob Herring <robh(a)kernel.org> > --- > .../bindings/arm/arm,coresight-catu.yaml | 101 +++++ > .../arm/arm,coresight-dynamic-funnel.yaml | 126 ++++++ > .../bindings/arm/arm,coresight-etb10.yaml | 92 ++++ > .../bindings/arm/arm,coresight-etm.yaml | 156 +++++++ > .../arm/arm,coresight-static-replicator.yaml | 90 ++++ > .../bindings/arm/arm,coresight-stm.yaml | 101 +++++ > .../bindings/arm/arm,coresight-tmc.yaml | 132 ++++++ > .../bindings/arm/arm,coresight-tpiu.yaml | 91 ++++ > .../devicetree/bindings/arm/coresight.txt | 402 ------------------ > 9 files changed, 889 insertions(+), 402 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt ... > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > new file mode 100644 > index 000000000000..ee1ce47225be > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Arm CoreSight Trace Memory Controller > + ... > + out-ports: > + $ref: /schemas/graph.yaml#/properties/ports > + additionalProperties: false > + > + properties: > + port: > + description: AXI Master output connection. Used for ETR and ETF > + configurations. nit: This is only for ETRs. Never for ETFs. Suzuki

2 years, 5 months

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