CoreSight November 2021

coresight@lists.linaro.org

8 participants
31 discussions

[PATCH v2 0/6] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load, unload and last_load_status are provided to implement the load functionality. Routines to generate binary configuration files are supplied in ./samples/coresight. Example generator and reader applications are provided. Additional Makefile.host supplied to build the generator and reader applications on the host system separate from a cross compiled kernel. Documentation is updated to describe feature usage. Applies and tested on latest coresight/next that includes the previous coresight configuration dynamic load patchset. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (6): coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: samples: Add an example config writer for configfs load coresight: samples: Add coresight file reader sample program Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 151 +++++- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 472 ++++++++++++++++++ .../coresight/coresight-config-file.h | 158 ++++++ .../hwtracing/coresight/coresight-config.h | 38 ++ .../coresight/coresight-syscfg-configfs.c | 148 +++++- .../coresight/coresight-syscfg-configfs.h | 8 + .../hwtracing/coresight/coresight-syscfg.c | 36 ++ .../hwtracing/coresight/coresight-syscfg.h | 2 + samples/coresight/Makefile | 23 + samples/coresight/Makefile.host | 47 ++ samples/coresight/coresight-cfg-bufw.c | 302 +++++++++++ samples/coresight/coresight-cfg-bufw.h | 24 + samples/coresight/coresight-cfg-file-read.c | 191 +++++++ samples/coresight/coresight-cfg-filegen.c | 89 ++++ 15 files changed, 1677 insertions(+), 14 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 samples/coresight/Makefile.host create mode 100644 samples/coresight/coresight-cfg-bufw.c create mode 100644 samples/coresight/coresight-cfg-bufw.h create mode 100644 samples/coresight/coresight-cfg-file-read.c create mode 100644 samples/coresight/coresight-cfg-filegen.c -- 2.17.1

2 years, 9 months

[PATCH v3] drivers/coresight: Add Ultrasoc System Memory Buffer driver

by Qi Liu

This patch adds driver for Ultrasoc SMB(System Memory Buffer) device. SMB provides a way to buffer messages from ETM, and store these CPU instructions in system memory. SMB is developed by Ultrasoc technology, which is acquired by Siemens, and we still use "Ultrasoc" to name driver. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> Tested-by: JunHao He <hejunhao2(a)hisilicon.com> --- Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link:https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of Ultrasoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move ultrasoc driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/ultrasoc-smb.c | 607 +++++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 116 ++++ 4 files changed, 737 insertions(+) create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 514a9b8086e3..d24a5d95153a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,16 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +config ULTRASOC_SMB + tristate "Ultrasoc system memory buffer drivers" + depends on ARM64 && CORESIGHT + help + This driver provides support for the Ultrasoc system memory buffer (SMB). + SMB is responsible for receiving the trace data from Coresight ETM devices + and storing them to a system buffer. + + To compile this driver as a module, choose M here: the module will be + called ultrasoc-smb. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..2899e5a5d5cd 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -27,3 +27,5 @@ obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o + +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c new file mode 100644 index 000000000000..b477fc51fbbb --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#include <linux/acpi.h> +#include <linux/circ_buf.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include "ultrasoc-smb.h" + +DEFINE_CORESIGHT_DEVLIST(sink_devs, "sink_smb"); + +static bool smb_buffer_is_empty(struct smb_drv_data *drvdata) +{ + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS); + + return buf_status & BIT(0) ? false : true; +} + +static bool smb_buffer_cmp_pointer(struct smb_drv_data *drvdata) +{ + u32 wr_offset, rd_offset; + + wr_offset = readl(drvdata->base + SMB_LB_WR_ADDR); + rd_offset = readl(drvdata->base + SMB_LB_RD_ADDR); + return wr_offset == rd_offset; +} + +static void smb_reset_buffer_status(struct smb_drv_data *drvdata) +{ + writel(0xf, drvdata->base + SMB_LB_INT_STS); +} + +/* Purge data remaining in hardware path to SMB. */ +static void smb_purge_data(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_LB_PURGE); +} + +static void smb_update_data_size(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 write_offset; + + smb_purge_data(drvdata); + if (smb_buffer_cmp_pointer(drvdata)) { + if (smb_buffer_is_empty(drvdata)) + sdb->data_size = 0; + else + sdb->data_size = sdb->buf_size; + return; + } + + write_offset = readl(drvdata->base + SMB_LB_WR_ADDR) - sdb->start_addr; + sdb->data_size = CIRC_CNT(write_offset, sdb->rd_offset, sdb->buf_size); +} + +static int smb_open(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + + if (local_cmpxchg(&drvdata->reading, 0, 1)) + return -EBUSY; + + return 0; +} + +static ssize_t smb_read(struct file *file, char __user *data, size_t len, loff_t *ppos) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct device *dev = &drvdata->csdev->dev; + unsigned long flags; + int to_copy = 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (!sdb->data_size) { + smb_update_data_size(drvdata); + if (!sdb->data_size) + goto out; + } + + if (atomic_read(drvdata->csdev->refcnt)) { + to_copy = -EBUSY; + goto out; + } + + to_copy = min(sdb->data_size, len); + + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + + if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, to_copy)) { + dev_dbg(dev, "Failed to copy data to user.\n"); + to_copy = -EFAULT; + goto out; + } + + *ppos += to_copy; + sdb->data_size -= to_copy; + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + dev_dbg(dev, "%d bytes copied.\n", to_copy); +out: + if (!sdb->data_size) + smb_reset_buffer_status(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return to_copy; +} + +static int smb_release(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + local_set(&drvdata->reading, 0); + return 0; +} + +static const struct file_operations smb_fops = { + .owner = THIS_MODULE, + .open = smb_open, + .read = smb_read, + .release = smb_release, + .llseek = no_llseek, +}; + +smb_simple_func(struct smb_drv_data, read_pos, SMB_LB_RD_ADDR); +smb_simple_func(struct smb_drv_data, write_pos, SMB_LB_WR_ADDR); +smb_simple_func(struct smb_drv_data, buf_status, SMB_LB_INT_STS); + +static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); +} +static DEVICE_ATTR_RO(buf_size); + +static struct attribute *smb_sink_attrs[] = { + &dev_attr_read_pos.attr, + &dev_attr_write_pos.attr, + &dev_attr_buf_status.attr, + &dev_attr_buf_size.attr, + NULL, +}; + +static const struct attribute_group smb_sink_group = { + .attrs = smb_sink_attrs, + .name = "status", +}; + +static const struct attribute_group *smb_sink_groups[] = { + &smb_sink_group, + NULL, +}; + +static int smb_set_perf_buffer(struct perf_output_handle *handle) +{ + struct cs_buffers *buf = etm_perf_sink_config(handle); + u32 head; + + if (!buf) + return -EINVAL; + + /* Wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* Find the page to write to and offset within that page */ + buf->cur = head / PAGE_SIZE; + buf->offset = head % PAGE_SIZE; + + local_set(&buf->data_size, 0); + + return 0; +} + +static void smb_enable_hw(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_GLOBAL_EN); +} + +static void smb_disable_hw(struct smb_drv_data *drvdata) +{ + writel(0x0, drvdata->base + SMB_GLOBAL_EN); +} + +static int smb_enable_sysfs(struct smb_drv_data *drvdata) +{ + if (drvdata->mode == CS_MODE_PERF) + return -EBUSY; + + if (drvdata->mode == CS_MODE_SYSFS) + return 0; + + smb_enable_hw(drvdata); + drvdata->mode = CS_MODE_SYSFS; + return 0; +} + +static int smb_enable_perf(struct smb_drv_data *drvdata, void *data) +{ + struct device *dev = &drvdata->csdev->dev; + struct perf_output_handle *handle = data; + pid_t pid; + + if (drvdata->mode == CS_MODE_SYSFS) { + dev_err(dev, "Device is already in used by sysfs.\n"); + return -EBUSY; + } + + /* Get a handle on the pid of the target process*/ + pid = task_pid_nr(handle->event->owner); + if (drvdata->pid != -1 && drvdata->pid != pid) { + dev_err(dev, "Device is already in used by other session.\n"); + return -EBUSY; + } + /* The sink is already enabled by this session. */ + if (drvdata->pid == pid) + return 0; + + if (smb_set_perf_buffer(handle)) + return -EINVAL; + + smb_enable_hw(drvdata); + drvdata->pid = pid; + drvdata->mode = CS_MODE_PERF; + + return 0; +} + +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int ret = -EINVAL; + + /* Do nothing if trace data is reading by other interface now. */ + if (local_read(&drvdata->reading)) + return -EBUSY; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (mode == CS_MODE_SYSFS) + ret = smb_enable_sysfs(drvdata); + + if (mode == CS_MODE_PERF) + ret = smb_enable_perf(drvdata, data); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (ret) + return ret; + + atomic_inc(csdev->refcnt); + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled.\n"); + + return 0; +} + +static int smb_disable(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + smb_disable_hw(drvdata); + + /* + * Data remaining in hardware path will be sent to SMB after purge, so needs to + * synchronize the read pointer to write pointer in perf mode. + */ + smb_purge_data(drvdata); + if (drvdata->mode == CS_MODE_PERF) + writel(readl(drvdata->base + SMB_LB_WR_ADDR), drvdata->base + SMB_LB_RD_ADDR); + + /* Dissociate from the target process. */ + drvdata->pid = -1; + drvdata->mode = CS_MODE_DISABLED; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled.\n"); + return 0; +} + +static void *smb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) +{ + struct cs_buffers *buf; + int node; + + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + buf->data_pages = pages; + + return buf; +} + +static void smb_free_buffer(void *config) +{ + struct cs_buffers *buf = config; + + kfree(buf); +} + +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, + struct cs_buffers *buf, unsigned long data_size) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + char **dst_pages = (char **)buf->data_pages; + unsigned long buf_offset = buf->offset; + unsigned int cur = buf->cur; + unsigned long to_copy; + + while (data_size) { + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + PAGE_SIZE - buf_offset > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + else + to_copy = min(data_size, PAGE_SIZE - buf_offset); + + memcpy_fromio(dst_pages[cur] + buf_offset, sdb->buf_base + sdb->rd_offset, to_copy); + + buf_offset += to_copy; + if (buf_offset >= PAGE_SIZE) { + buf_offset = 0; + cur++; + cur %= buf->nr_pages; + } + data_size -= to_copy; + /* ensure memcpy finished before update the read pointer */ + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + } + + sdb->data_size = 0; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + smb_reset_buffer_status(drvdata); +} + +static unsigned long smb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct cs_buffers *buf = sink_config; + unsigned long data_size = 0; + unsigned long flags; + bool lost = false; + + if (!buf) + return 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink. */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + + smb_update_data_size(drvdata); + data_size = sdb->data_size; + if (data_size > handle->size) { + sdb->rd_offset += data_size - handle->size; + sdb->rd_offset %= sdb->buf_size; + data_size = handle->size; + lost = true; + } + + smb_sync_perf_buffer(drvdata, buf, data_size); + if (!buf->snapshot && lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return data_size; +} + +static const struct coresight_ops_sink smb_cs_ops = { + .enable = smb_enable, + .disable = smb_disable, + .alloc_buffer = smb_alloc_buffer, + .free_buffer = smb_free_buffer, + .update_buffer = smb_update_buffer, +}; + +static const struct coresight_ops cs_ops = { + .sink_ops = &smb_cs_ops, +}; + +static int smb_init_data_buffer(struct platform_device *pdev, struct smb_data_buffer *sdb) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "SMB device failed to get resource.\n"); + return -EINVAL; + } + + sdb->start_addr = res->start & SMB_BASE_LOW_MASK; + sdb->buf_size = resource_size(res); + if (sdb->buf_size == 0) + return -EINVAL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + sdb->buf_base = base; + + return 0; +} + +static void smb_init_hw(struct smb_drv_data *drvdata) +{ + u32 value; + + /* First disable smb and clear the status of SMB buffer */ + smb_reset_buffer_status(drvdata); + smb_disable_hw(drvdata); + smb_purge_data(drvdata); + + /* Using smb in single-end mode, and set other configures default */ + value = SMB_BUF_CFG_STREAMING | SMB_BUF_SINGLE_END | SMB_BUF_EN; + writel(value, drvdata->base + SMB_LB_CFG_LO); + value = SMB_MSG_FILTER(0x0, 0xff); + writel(value, drvdata->base + SMB_LB_CFG_HI); + + writel(SMB_GLOBAL_CFG, drvdata->base + SMB_CFG_REG); + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLOBAL_INT); + writel(SMB_BUF_INT_CFG, drvdata->base + SMB_LB_INT_CTRL); +} + +static int smb_register_sink(struct platform_device *pdev, struct smb_drv_data *drvdata) +{ + struct coresight_platform_data *pdata = NULL; + struct coresight_desc desc = { 0 }; + int ret; + + pdata = coresight_get_platform_data(&pdev->dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc.ops = &cs_ops; + desc.pdata = pdata; + desc.dev = &pdev->dev; + desc.groups = smb_sink_groups; + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); + if (!desc.name) { + dev_err(&pdev->dev, "Failed to alloc coresight device name."); + return -ENOMEM; + } + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &smb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) { + coresight_unregister(drvdata->csdev); + dev_err(&pdev->dev, "Failed to register misc, ret=%d.\n", ret); + } + + return ret; +} + +static void smb_unregister_sink(struct smb_drv_data *drvdata) +{ + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); +} + +/* + * Send ultrasoc messge to control hardwares on the tracing path, + * using DSM calls to avoid exposing ultrasoc message format. + */ +static int smb_config_inport(struct device *dev, bool enable) +{ + u32 flag = enable ? 1 : 0; + union acpi_object *obj; + guid_t guid; + + if (guid_parse("82ae1283-7f6a-4cbe-aa06-53e8fb24db18", &guid)) { + dev_err(dev, "Get GUID failed.\n"); + return -EINVAL; + } + + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, flag, NULL); + if (!obj) + dev_err(dev, "ACPI handle failed!\n"); + else + ACPI_FREE(obj); + + return 0; +} + +static int smb_probe(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata; + int ret; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) { + dev_err(&pdev->dev, "Failed to ioremap resource.\n"); + return PTR_ERR(drvdata->base); + } + + ret = smb_init_data_buffer(pdev, &drvdata->sdb); + if (ret) { + dev_err(&pdev->dev, "Failed to init buffer, ret = %d.\n", ret); + return ret; + } + + smb_init_hw(drvdata); + spin_lock_init(&drvdata->spinlock); + drvdata->pid = -1; + + ret = smb_register_sink(pdev, drvdata); + if (ret) { + dev_err(&pdev->dev, "Failed to register smb sink.\n"); + return ret; + } + + ret = smb_config_inport(&pdev->dev, true); + if (ret) { + smb_unregister_sink(drvdata); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + return 0; +} + +static int smb_remove(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); + int ret; + + ret = smb_config_inport(&pdev->dev, false); + if (ret) + return ret; + + smb_unregister_sink(drvdata); + return 0; +} + +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { + {"HISI03A1", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); + +static struct platform_driver smb_driver = { + .driver = { + .name = "ultrasoc,smb", + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), + .suppress_bind_attrs = true, + }, + .probe = smb_probe, + .remove = smb_remove, +}; +module_platform_driver(smb_driver); + +MODULE_DESCRIPTION("Ultrasoc smb driver"); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen(a)huawei.com>"); +MODULE_AUTHOR("Qi Liu <liuqi115(a)huawei.com>"); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h new file mode 100644 index 000000000000..0b725db88f84 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#ifndef _ULTRASOC_SMB_H +#define _ULTRASOC_SMB_H + +#include <linux/coresight.h> +#include <linux/list.h> +#include <linux/miscdevice.h> + +#include "coresight-etm-perf.h" +#include "coresight-priv.h" + +/* Offset of SMB logical buffer registers */ +#define SMB_CFG_REG 0X0 +#define SMB_GLOBAL_EN 0X4 +#define SMB_GLOBAL_INT 0X8 +#define SMB_LB_CFG_LO 0X40 +#define SMB_LB_CFG_HI 0X44 +#define SMB_LB_INT_CTRL 0X48 +#define SMB_LB_INT_STS 0X4C +#define SMB_LB_LIMIT 0X58 +#define SMB_LB_RD_ADDR 0X5C +#define SMB_LB_WR_ADDR 0X60 +#define SMB_LB_PURGE 0X64 + +/* Set SMB_CFG_REG register */ +#define SMB_IDLE_PRD(period) (((period - 216) & 0xf) << 12) +#define SMB_MEM_WR(credit, rate) (((credit) << 16) | ((rate) << 18)) +#define SMB_MEM_RD(credit, rate) (((credit) << 22) | ((rate) << 24)) +#define SMB_BURST_LEN(len) ((len - 1) << 4) +#define SMB_GLOBAL_CFG (SMB_IDLE_PRD(231) | SMB_MEM_WR(0x3, 0x0) | \ + SMB_MEM_RD(0x3, 0x6) | SMB_BURST_LEN(16)) + +/* Set SMB_GLOBAL_INT register */ +#define SMB_INT_EN BIT(0) +#define SMB_INT_TYPE_PULSE BIT(1) +#define SMB_INT_POLARITY_HIGH BIT(2) +#define SMB_GLB_INT_CFG (SMB_INT_EN | SMB_INT_TYPE_PULSE | SMB_INT_POLARITY_HIGH) + +/* Set SMB_LB_CFG_LO register */ +#define SMB_BUF_EN BIT(0) +#define SMB_BUF_SINGLE_END BIT(1) +#define SMB_BUF_INIT BIT(8) +#define SMB_BUF_CONTINUOUS BIT(11) +#define SMB_FLOW_MASK GENMASK(19, 16) +#define SMB_BUF_CFG_STREAMING (SMB_BUF_INIT | SMB_BUF_CONTINUOUS | SMB_FLOW_MASK) +#define SMB_BASE_LOW_MASK GENMASK(31, 0) + +/* Set SMB_LB_CFG_HI register */ +#define SMB_MSG_FILTER(lower, upper) ((lower & 0xff) | ((upper & 0xff) << 8)) +#define SMB_BUF_INT_EN BIT(0) +#define SMB_BUF_NOTE_MASK GENMASK(11, 8) +#define SMB_BUF_INT_CFG (SMB_BUF_INT_EN | SMB_BUF_NOTE_MASK) + +/** + * struct smb_data_buffer - Details of the buffer used by SMB + * @buf_base : Memory mapped base address of SMB. + * @start_addr : SMB buffer start Physical address. + * @buf_size : Size of the buffer. + * @data_size : Size of Trace data copy to userspace. + * @rd_offset : Offset of the read pointer in the buffer. + */ +struct smb_data_buffer { + void __iomem *buf_base; + u32 start_addr; + unsigned long buf_size; + unsigned long data_size; + unsigned long rd_offset; +}; + +/** + * struct smb_drv_data - specifics associated to an SMB component + * @base: Memory mapped base address for SMB component. + * @csdev: Component vitals needed by the framework. + * @sdb: Data buffer for SMB. + * @miscdev: Specifics to handle "/dev/xyz.tmc" entry. + * @spinlock: Only one at a time pls. + * @reading: Synchronise user space access to SMB buffer. + * @pid: Process ID of the process being monitored by the session + * that is using this component. + * @mode: how this SMB is being used, perf mode or sysfs mode. + */ +struct smb_drv_data { + void __iomem *base; + struct coresight_device *csdev; + struct smb_data_buffer sdb; + struct miscdevice miscdev; + spinlock_t spinlock; + local_t reading; + pid_t pid; + u32 mode; +}; + +#define smb_simple_func(type, name, offset) \ +static ssize_t name##_show(struct device *_dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + type *drvdata = dev_get_drvdata(_dev->parent); \ + u32 val = readl(drvdata->base + offset); \ + \ + return sysfs_emit(buf, "0x%x\n", val); \ +} \ +static DEVICE_ATTR_RO(name) + +#endif -- 2.33.0

2 years, 10 months

[PATCH v3 0/6] coresight: syscfg: dynamic load

by Mike Leach

1) API updated to allow dynamic load and unload of configurations and features. Dependency management between loaded sets is added. 2) New configuration and feature sets can be added using a loadable module. An example in /samples/coresight is provided to demonstrate this. 3) configfs can be used to activate a configuration which will then be used when controlling tracing using sysfs. Applies and tested on coresight/next - which is 5.16-rc1 Changes since v2: (requested by Mathieu) a) Split first patch into two patches to introduce the concept of owner, then use it to implement dynamic load / unload. b) Renamed configfs configuration attributes used to enable and set preset on configurations when using CoreSight with sysfs c) Updated docs to reflect use of enable and preset attributes for sysfs CoreSight control. Changes since v1: a) Original set split to divide related changes into smaller sets. Removed RFC flag. b) Revised config activation for sysfs to simplify common function. (patch 4). c) Minor changes requested by Mathieu added. Mike Leach (6): coresight: configuration: Update API to introduce load owner concept coresight: configuration: Update API to permit dynamic load/unload coresight: syscfg: Update load API for config loadable modules coresight: syscfg: Example CoreSight configuration loadable module coresight: configfs: Allow configfs to activate configuration Documentation: coresight: Update coresight configuration docs .../trace/coresight/coresight-config.rst | 62 +++- MAINTAINERS | 1 + .../coresight/coresight-cfg-preload.c | 9 +- .../hwtracing/coresight/coresight-config.h | 9 +- .../coresight/coresight-etm4x-core.c | 11 +- .../coresight/coresight-syscfg-configfs.c | 87 +++++ .../coresight/coresight-syscfg-configfs.h | 4 + .../hwtracing/coresight/coresight-syscfg.c | 315 ++++++++++++++++-- .../hwtracing/coresight/coresight-syscfg.h | 39 ++- samples/Kconfig | 9 + samples/Makefile | 1 + samples/coresight/Makefile | 4 + samples/coresight/coresight-cfg-sample.c | 73 ++++ 13 files changed, 586 insertions(+), 38 deletions(-) create mode 100644 samples/coresight/Makefile create mode 100644 samples/coresight/coresight-cfg-sample.c -- 2.17.1

2 years, 11 months

Re: [PATCH v2 2/6] hwtracing: Add trace function support for HiSilicon PCIe Tune and Trace device

by Mathieu Poirier

On Thu, Nov 25, 2021 at 04:39:46PM +0800, Yicong Yang wrote: > Hi Mathieu, > > Thanks for the comments! Replies inline. > > On 2021/11/25 2:51, Mathieu Poirier wrote: > > Hi Yicong, > > > > On Tue, Nov 16, 2021 at 05:06:21PM +0800, Yicong Yang wrote: > >> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex > >> integrated Endpoint(RCiEP) device, providing the capability > >> to dynamically monitor and tune the PCIe traffic(tune), > >> and trace the TLP headers(trace). > >> > > > > Is there a reason to put "tune" and "trace" are whithin parentheses? > > > > yeah. I want to use these single word to denote the related function, and > place them in the parantheses near the function's description to make sure > readers can match them. > Probably a better idea to simply write "TLP headers" and "PCIe traffic" when referring to them. Otherwise it is very confusing because the reader doesn't know if you mean the acronym or the real definition of "tune" and "trace". > >> Add the driver for the device to enable the trace function. The driver > >> will create PMU device for each PTT device, and users can start trace > >> through perf command. > >> > >> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > >> --- > >> drivers/Makefile | 1 + > >> drivers/hwtracing/Kconfig | 2 + > >> drivers/hwtracing/hisilicon/Kconfig | 8 + > >> drivers/hwtracing/hisilicon/Makefile | 2 + > >> drivers/hwtracing/hisilicon/hisi_ptt.c | 1146 ++++++++++++++++++++++++ > > > > Not sure about the "hisilicon" directory. Right now we have "coresight", > > "intel_th" and "stm" - they concentrate on the technology rather than the > > vendor. I think "ptt" would be just fine: > > > > drivers/hwtracing/ptt/Kconfig > > drivers/hwtracing/ptt/Makefile > > drivers/hwtracing/ptt/hisi_ptt.c > > > > That way if other vendors want to introduce support for the same kind of > > technology we can simply put them under "drivers/hwtracing/ptt/" and things are > > still accurate. > > > > sure. sounds sensible. will rename the directory to "ptt" if no objection. > > > > >> 5 files changed, 1159 insertions(+) > >> create mode 100644 drivers/hwtracing/hisilicon/Kconfig > >> create mode 100644 drivers/hwtracing/hisilicon/Makefile > >> create mode 100644 drivers/hwtracing/hisilicon/hisi_ptt.c > >> > >> diff --git a/drivers/Makefile b/drivers/Makefile > >> index be5d40ae1488..bb0dc9b55ea2 100644 > >> --- a/drivers/Makefile > >> +++ b/drivers/Makefile > >> @@ -176,6 +176,7 @@ obj-$(CONFIG_USB4) += thunderbolt/ > >> obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ > >> obj-y += hwtracing/intel_th/ > >> obj-$(CONFIG_STM) += hwtracing/stm/ > >> +obj-$(CONFIG_HISI_PTT) += hwtracing/hisilicon/ > >> obj-$(CONFIG_ANDROID) += android/ > >> obj-$(CONFIG_NVMEM) += nvmem/ > >> obj-$(CONFIG_FPGA) += fpga/ > >> diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig > >> index 13085835a636..e3796b17541a 100644 > >> --- a/drivers/hwtracing/Kconfig > >> +++ b/drivers/hwtracing/Kconfig > >> @@ -5,4 +5,6 @@ source "drivers/hwtracing/stm/Kconfig" > >> > >> source "drivers/hwtracing/intel_th/Kconfig" > >> > >> +source "drivers/hwtracing/hisilicon/Kconfig" > >> + > >> endmenu > >> diff --git a/drivers/hwtracing/hisilicon/Kconfig b/drivers/hwtracing/hisilicon/Kconfig > >> new file mode 100644 > >> index 000000000000..9c3ab80d99fe > >> --- /dev/null > >> +++ b/drivers/hwtracing/hisilicon/Kconfig > >> @@ -0,0 +1,8 @@ > >> +# SPDX-License-Identifier: GPL-2.0-only > >> +config HISI_PTT > >> + tristate "HiSilicon PCIe Tune and Trace Device" > >> + depends on PCI && HAS_DMA && HAS_IOMEM > > > > What Arm architecture are you aiming this for? Can it be found on both armv7 > > and armv8? > > > > currently the device will appear on Kunpeng 930, which is armv8. Ok, then please make it dependent on armv8. > > >> + help > >> + HiSilicon PCIe Tune and Trace Device exist as a PCIe RCiEP > >> + device, provides support for PCIe traffic tuning and > >> + tracing TLP headers to the memory. > > > > Please indicate what the name of the driver will be when compiled as a module. > > > > sure. will add the module's name here. > > >> diff --git a/drivers/hwtracing/hisilicon/Makefile b/drivers/hwtracing/hisilicon/Makefile > >> new file mode 100644 > >> index 000000000000..908c09a98161 > >> --- /dev/null > >> +++ b/drivers/hwtracing/hisilicon/Makefile > >> @@ -0,0 +1,2 @@ > >> +# SPDX-License-Identifier: GPL-2.0 > >> +obj-$(CONFIG_HISI_PTT) += hisi_ptt.o > >> diff --git a/drivers/hwtracing/hisilicon/hisi_ptt.c b/drivers/hwtracing/hisilicon/hisi_ptt.c > >> new file mode 100644 > >> index 000000000000..e11e9b6cc2a8 > >> --- /dev/null > >> +++ b/drivers/hwtracing/hisilicon/hisi_ptt.c > >> @@ -0,0 +1,1146 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > >> +/* > >> + * Driver for HiSilicon PCIe tune and trace device > >> + * > >> + * Copyright (c) 2021 HiSilicon Limited. > >> + */ > >> + > >> +#include <linux/bitfield.h> > >> +#include <linux/bitops.h> > >> +#include <linux/delay.h> > >> +#include <linux/dma-iommu.h> > >> +#include <linux/dma-mapping.h> > >> +#include <linux/interrupt.h> > >> +#include <linux/io.h> > >> +#include <linux/iommu.h> > >> +#include <linux/iopoll.h> > >> +#include <linux/kfifo.h> > >> +#include <linux/module.h> > >> +#include <linux/notifier.h> > >> +#include <linux/pci.h> > >> +#include <linux/perf_event.h> > >> +#include <linux/sizes.h> > >> +#include <linux/sysfs.h> > >> +#include <linux/vmalloc.h> > >> +#include <linux/workqueue.h> > >> + > >> +#define HISI_PTT_TRACE_ADDR_SIZE 0x0800 > >> +#define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810 > >> +#define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814 > >> +#define HISI_PTT_TRACE_ADDR_STRIDE 0x8 > >> +#define HISI_PTT_TRACE_CTRL 0x0850 > >> +#define HISI_PTT_TRACE_CTRL_EN BIT(0) > >> +#define HISI_PTT_TRACE_CTRL_RST BIT(1) > >> +#define HISI_PTT_TRACE_CTRL_RXTX_SEL GENMASK(3, 2) > >> +#define HISI_PTT_TRACE_CTRL_TYPE_SEL GENMASK(7, 4) > >> +#define HISI_PTT_TRACE_CTRL_DATA_FORMAT BIT(14) > >> +#define HISI_PTT_TRACE_CTRL_FILTER_MODE BIT(15) > >> +#define HISI_PTT_TRACE_CTRL_TARGET_SEL GENMASK(31, 16) > >> +#define HISI_PTT_TRACE_INT_STAT 0x0890 > >> +#define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0) > >> +#define HISI_PTT_TRACE_INT_MASK 0x0894 > >> +#define HISI_PTT_TRACE_WR_STS 0x08a0 > >> +#define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0) > >> +#define HISI_PTT_TRACE_WR_STS_BUFFER GENMASK(29, 28) > >> +#define HISI_PTT_TRACE_STS 0x08b0 > >> +#define HISI_PTT_TRACE_IDLE BIT(0) > >> +#define HISI_PTT_DEVICE_RANGE 0x0fe0 > >> +#define HISI_PTT_LOCATION 0x0fe8 > >> +#define HISI_PTT_CORE_ID GENMASK(15, 0) > >> +#define HISI_PTT_SICL_ID GENMASK(31, 16) > > > > Extra spaces between #define and the literals. Please align the values with > > that of HISI_PTT_TRACE_DMA_IRQ below. > > > > Spaces are intended to distinguish the definition of the register offset and > related register fields. also used in include/uapi/linux/pci_regs.h. > Interesting and definitely not the norm... > HISI_PTT_TRACE_DMA_IRQ is well aligned with tab but seems with problem display > in the mail text, maybe because the tab is not 8 characters when display. > In my VI terminal the '0' of HISI_PTT_TRACE_DMA_IRQ is align with the '3' in GENMASK(31, 16) and I suspect it is the same for other people. > >> + > >> +#define HISI_PTT_TRACE_DMA_IRQ 0 > >> +#define HISI_PTT_TRACE_BUFLETS_CNT 4 > >> +#define HISI_PTT_TRACE_BUFLET_SIZE SZ_4M > >> +#define HISI_PTT_TRACE_BUFFER_SIZE (HISI_PTT_TRACE_BUFLET_SIZE * \ > >> + HISI_PTT_TRACE_BUFLETS_CNT) > >> +#define HISI_PTT_FILTER_UPDATE_FIFO_SIZE 16 > >> + > >> +/* Delay time for filter updating work */ > >> +#define HISI_PTT_WORK_DELAY_MS 100UL > >> +/* Wait time for DMA hardware to reset */ > >> +#define HISI_PTT_RESET_WAIT_MS 1000UL > >> +/* Poll timeout and interval for waiting hardware work to finish */ > >> +#define HISI_PTT_WAIT_TIMEOUT_US 1000000UL > >> +#define HISI_PTT_WAIT_POLL_INTERVAL_US 100UL > >> + > >> +#define HISI_PCIE_CORE_PORT_ID(devfn) (PCI_FUNC(devfn) << 1) > >> + > >> +enum hisi_ptt_trace_status { > >> + HISI_PTT_TRACE_STATUS_OFF = 0, > >> + HISI_PTT_TRACE_STATUS_ON, > >> +}; > >> + > >> +struct hisi_ptt_dma_buflet { > > > > I'm not sure what a "buflet" is... Probably best to just call this > > hisi_ptt_dma_buffer" if it pertains to a buffer. On that note it is hard to > > know due to the lack of proper structure documentation. Please have a look at > > how "coresight_device" is documented. The same applies to the rest of the > > structures declared below. > > > > It's mentioned in section 5 of hisi_ptt.rst as "Driver will allocate each DMA buffer > (we call it buflet) of 4MiB ...". I just noticed the documentation in patch 5 - I will read it before continuing with this set. > > The total DMA buffer of PTT device is divided into 4 parts, and each part is called > a 'buflet', which means a small buffer (there exists other words with similiar > format: droplet, wavelet, ...). > > The device is designed like this to make sure we won't lose any data when we have to change > the buffer address, the device can continue to write to the next buflet and don't > neet to pause. > > >> + struct list_head list; > >> + unsigned int size; > >> + dma_addr_t dma; > >> + > >> + /* > >> + * The address of the buflet holding the trace data. > >> + * See Documentation/trace/hisi-ptt.rst for the details > > > > As of this writing, hisi-ptt.rst doesn't exist. > > > > The comment intends to direct the user to the documentation if the user > want to know details about the data format. The data format is decribed > in the section 4 of the doc. > > >> + * of the data format. > >> + */ > >> + void *addr; > >> + int index; > >> +}; > >> + > >> +struct hisi_ptt_trace_ctrl { > >> + enum hisi_ptt_trace_status status; > >> + struct perf_output_handle handle; > >> + struct list_head trace_buf; > >> + /* > >> + * The index of the buffer which trace data > >> + * currently is writing to. > >> + */ > >> + u32 buf_index; > >> + > >> + int default_cpu; > >> + u32 buflet_size; > >> + bool is_port; > >> + u32 format:1; /* Format of the traced TLP headers */ > >> + u32 type:4; /* Type of the TLP headers to trace */ > >> + u32 direction:2; /* Direction of the TLP headers to trace */ > >> + u32 filter:16; /* Root port or Requester to filter the TLP headers */ > >> + > >> + phys_addr_t rmr_addr; > >> + size_t rmr_length; > >> + bool has_rmr; > >> +}; > >> + > >> +struct hisi_ptt_filter_desc { > >> + struct list_head list; > >> + struct pci_dev *pdev; > >> + u16 val; > >> +}; > >> + > >> +struct hisi_ptt_pmu_buf { > >> + size_t length; > >> + int nr_pages; > >> + void *base; > >> + long pos; > >> +}; > >> + > >> +/* Structure containing the information for filter updating */ > >> +struct hisi_ptt_filter_update_info { > >> + struct pci_dev *pdev; > >> + u32 port_devid; > >> + bool is_port; > >> + bool is_add; > >> + u16 val; > >> +}; > >> + > >> +struct hisi_ptt { > >> + struct hisi_ptt_trace_ctrl trace_ctrl; > >> + struct notifier_block hisi_ptt_nb; > >> + struct pmu hisi_ptt_pmu; > >> + void __iomem *iobase; > >> + struct pci_dev *pdev; > >> + /* > >> + * Use the mutex to protect the filter list and > >> + * serialize the perf process. > >> + */ > >> + struct mutex mutex; > >> + const char *name; > >> + u16 core_id; > >> + u16 sicl_id; > >> + /* PCI device range managed by the PTT device */ > >> + u32 upper; > >> + u32 lower; > >> + u8 busnr; > >> + > >> + /* > >> + * The trace TLP headers can either be filtered by certain > >> + * root port, or by the requester ID. Organize the filters > >> + * by @port_filters and @req_filters here. The mask of all > >> + * the valid ports is also cached for doing sanity check > >> + * of user input. > >> + */ > >> + struct list_head port_filters; > >> + struct list_head req_filters; > >> + u16 port_mask; > >> + > >> + /* > >> + * We use a delayed work here to avoid indefinitely waiting for > >> + * the hisi_ptt->mutex which protecting the filter list. The > >> + * work will be delayed only if the mutex can not be held, > >> + * otherwise no delay will be applied. > >> + */ > >> + struct delayed_work work; > >> + spinlock_t filter_update_lock; > >> + DECLARE_KFIFO(filter_update_kfifo, struct hisi_ptt_filter_update_info, > >> + HISI_PTT_FILTER_UPDATE_FIFO_SIZE); > >> +}; > > > > It might be a good idea to spinoff a hisi_ptt.h for the above declarations. > > > > I'm not sure whether it is common or permitted to provide a header which is only used by > this driver with a single file. I've seen it done many times. > > >> + > >> +static inline struct hisi_ptt *to_hisi_ptt(struct pmu *pmu) > >> +{ > >> + return container_of(pmu, struct hisi_ptt, hisi_ptt_pmu); > >> +} > > > > I'm not sure there is any value to this inline function. I suggest to simply > > call container_of() whenever it is needed. > > > > ok. > > >> + > >> +static u16 hisi_ptt_get_filter_val(struct pci_dev *pdev) > >> +{ > >> + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) > >> + return BIT(HISI_PCIE_CORE_PORT_ID(PCI_SLOT(pdev->devfn))); > >> + > >> + return PCI_DEVID(pdev->bus->number, pdev->devfn); > >> +} > >> + > >> +static int hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt) > >> +{ > >> + u32 val; > >> + > >> + return readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TRACE_STS, val, > >> + val & HISI_PTT_TRACE_IDLE, > >> + HISI_PTT_WAIT_POLL_INTERVAL_US, > >> + HISI_PTT_WAIT_TIMEOUT_US); > >> +} > >> + > >> +static void hisi_ptt_free_trace_buf(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > >> + struct device *dev = &hisi_ptt->pdev->dev; > >> + struct hisi_ptt_dma_buflet *buflet, *tbuflet; > >> + > >> + list_for_each_entry_safe(buflet, tbuflet, &ctrl->trace_buf, list) { > >> + list_del(&buflet->list); > >> + > >> + if (ctrl->has_rmr) > >> + memunmap(buflet->addr); > >> + else > >> + dma_free_coherent(dev, buflet->size, buflet->addr, > >> + buflet->dma); > >> + > >> + kfree(buflet); > >> + } > >> +} > >> + > >> +static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > >> + struct device *dev = &hisi_ptt->pdev->dev; > >> + struct hisi_ptt_dma_buflet *buflet; > >> + int i, ret; > >> + > >> + hisi_ptt->trace_ctrl.buf_index = 0; > >> + > >> + /* Make sure the trace buffer is empty before allocating */ > >> + if (!list_empty(&ctrl->trace_buf)) { > >> + list_for_each_entry(buflet, &ctrl->trace_buf, list) > >> + memset(buflet->addr, 0, buflet->size); > >> + return 0; > >> + } > >> + > >> + for (i = 0; i < HISI_PTT_TRACE_BUFLETS_CNT; ++i) { > >> + buflet = kzalloc(sizeof(*buflet), GFP_KERNEL); > >> + if (!buflet) { > >> + ret = -ENOMEM; > >> + goto err; > >> + } > >> + > >> + if (ctrl->has_rmr) { > >> + phys_addr_t base = ctrl->rmr_addr + i * ctrl->buflet_size; > >> + > >> + buflet->dma = base; > >> + buflet->addr = memremap(base, ctrl->buflet_size, MEMREMAP_WB); > >> + } else { > >> + buflet->addr = dma_alloc_coherent(dev, ctrl->buflet_size, > >> + &buflet->dma, GFP_KERNEL); > >> + } > >> + > >> + if (!buflet->addr) { > >> + kfree(buflet); > >> + ret = -ENOMEM; > >> + goto err; > >> + } > >> + > >> + memset(buflet->addr, 0, buflet->size); > >> + > >> + buflet->index = i; > >> + buflet->size = ctrl->buflet_size; > >> + list_add_tail(&buflet->list, &ctrl->trace_buf); > >> + } > >> + > >> + return 0; > >> +err: > >> + hisi_ptt_free_trace_buf(hisi_ptt); > >> + return ret; > >> +} > >> + > >> +static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt) > >> +{ > >> + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + hisi_ptt->trace_ctrl.status = HISI_PTT_TRACE_STATUS_OFF; > >> +} > >> + > >> +static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > >> + struct hisi_ptt_dma_buflet *cur; > >> + u32 val; > >> + > >> + /* Check device idle before start trace */ > >> + if (hisi_ptt_wait_trace_hw_idle(hisi_ptt)) { > >> + pci_err(hisi_ptt->pdev, "Failed to start trace, the device is still busy.\n"); > >> + return -EBUSY; > >> + } > >> + > >> + /* Reset the DMA before start tracing */ > >> + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + val |= HISI_PTT_TRACE_CTRL_RST; > >> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + > >> + /* > >> + * We'll be in the perf context where preemption is disabled, > >> + * so use busy loop here. > >> + */ > >> + mdelay(HISI_PTT_RESET_WAIT_MS); > >> + > >> + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + val &= ~HISI_PTT_TRACE_CTRL_RST; > >> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + > >> + /* clear the interrupt status */ > >> + writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > >> + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK); > >> + > >> + list_for_each_entry(cur, &ctrl->trace_buf, list) { > >> + writel(lower_32_bits(cur->dma), > >> + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_LO_0 + > >> + cur->index * HISI_PTT_TRACE_ADDR_STRIDE); > >> + writel(upper_32_bits(cur->dma), > >> + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_HI_0 + > >> + cur->index * HISI_PTT_TRACE_ADDR_STRIDE); > >> + } > >> + writel(ctrl->buflet_size, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE); > >> + > >> + /* set the trace control register */ > >> + val = FIELD_PREP(HISI_PTT_TRACE_CTRL_TYPE_SEL, ctrl->type); > >> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_RXTX_SEL, ctrl->direction); > >> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_DATA_FORMAT, ctrl->format); > >> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter); > >> + if (!hisi_ptt->trace_ctrl.is_port) > >> + val |= HISI_PTT_TRACE_CTRL_FILTER_MODE; > >> + > >> + val |= HISI_PTT_TRACE_CTRL_EN; > >> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > >> + > >> + ctrl->status = HISI_PTT_TRACE_STATUS_ON; > >> + > >> + return 0; > >> +} > >> + > >> +static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop) > >> +{ > >> + struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle; > >> + struct perf_event *event = handle->event; > >> + struct hisi_ptt_dma_buflet *cur; > >> + struct hisi_ptt_pmu_buf *buf; > >> + > >> + buf = perf_get_aux(handle); > >> + if (!buf || !handle->size) > >> + return -EINVAL; > >> + > >> + list_for_each_entry(cur, &hisi_ptt->trace_ctrl.trace_buf, list) > >> + if (cur->index == index) > >> + break; > >> + > >> + memcpy(buf->base + buf->pos, cur->addr, cur->size); > >> + memset(cur->addr, 0, cur->size); > >> + buf->pos += cur->size; > >> + > >> + if (stop) { > >> + perf_aux_output_end(handle, buf->pos); > >> + } else if (buf->length - buf->pos < cur->size) { > >> + perf_aux_output_skip(handle, buf->length - buf->pos); > >> + perf_aux_output_end(handle, buf->pos); > >> + > >> + buf = perf_aux_output_begin(handle, event); > >> + if (!buf) > >> + return -EINVAL; > >> + > >> + buf->pos = handle->head % buf->length; > >> + if (buf->length - buf->pos < cur->size) { > >> + perf_aux_output_end(handle, 0); > >> + return -EINVAL; > >> + } > >> + } > >> + > >> + return 0; > >> +} > >> + > >> +static irqreturn_t hisi_ptt_isr(int irq, void *context) > >> +{ > >> + struct hisi_ptt *hisi_ptt = context; > >> + u32 status, buf_idx; > >> + > >> + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > >> + buf_idx = ffs(status) - 1; > >> + > >> + /* Clear the interrupt status of buflet @buf_idx */ > >> + writel(status, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > >> + > >> + /* > >> + * Update the AUX buffer and cache the current buflet index, > >> + * as we need to know this and save the data when the trace > >> + * is ended out of the interrupt handler. End the trace > >> + * if the updating fails. > >> + */ > >> + if (hisi_ptt_update_aux(hisi_ptt, buf_idx, false)) > >> + hisi_ptt_trace_end(hisi_ptt); > >> + else > >> + hisi_ptt->trace_ctrl.buf_index = (buf_idx + 1) % HISI_PTT_TRACE_BUFLETS_CNT; > >> + > >> + return IRQ_HANDLED; > >> +} > >> + > >> +static irqreturn_t hisi_ptt_irq(int irq, void *context) > >> +{ > >> + struct hisi_ptt *hisi_ptt = context; > >> + u32 status; > >> + > >> + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > >> + if (!(status & HISI_PTT_TRACE_INT_STAT_MASK)) > >> + return IRQ_NONE; > >> + > >> + return IRQ_WAKE_THREAD; > >> +} > >> + > >> +static void hisi_ptt_irq_free_vectors(void *pdev) > >> +{ > >> + pci_free_irq_vectors(pdev); > >> +} > >> + > >> +static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct pci_dev *pdev = hisi_ptt->pdev; > >> + int ret; > >> + > >> + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); > >> + if (ret < 0) { > >> + pci_err(pdev, "failed to allocate irq vector, ret = %d.\n", ret); > >> + return ret; > >> + } > >> + > >> + ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_irq_free_vectors, pdev); > >> + if (ret < 0) > >> + return ret; > >> + > >> + ret = devm_request_threaded_irq(&pdev->dev, > >> + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), > >> + hisi_ptt_irq, hisi_ptt_isr, 0, > >> + "hisi-ptt", hisi_ptt); > >> + if (ret) { > >> + pci_err(pdev, "failed to request irq %d, ret = %d.\n", > >> + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret); > >> + return ret; > >> + } > >> + > >> + return 0; > >> +} > >> + > >> +static void hisi_ptt_update_filters(struct work_struct *work) > >> +{ > >> + struct delayed_work *delayed_work = to_delayed_work(work); > >> + struct hisi_ptt_filter_update_info info; > >> + struct hisi_ptt_filter_desc *filter; > >> + struct list_head *target_list; > >> + struct hisi_ptt *hisi_ptt; > >> + > >> + hisi_ptt = container_of(delayed_work, struct hisi_ptt, work); > >> + > >> + if (!mutex_trylock(&hisi_ptt->mutex)) { > >> + schedule_delayed_work(&hisi_ptt->work, HISI_PTT_WORK_DELAY_MS); > >> + return; > >> + } > >> + > >> + while (kfifo_get(&hisi_ptt->filter_update_kfifo, &info)) { > >> + target_list = info.is_port ? &hisi_ptt->port_filters : > >> + &hisi_ptt->req_filters; > >> + > >> + if (info.is_add) { > >> + filter = kzalloc(sizeof(*filter), GFP_KERNEL); > >> + if (!filter) > >> + continue; > >> + > >> + filter->pdev = info.pdev; > >> + filter->val = info.val; > >> + > >> + list_add_tail(&filter->list, target_list); > >> + } else { > >> + list_for_each_entry(filter, target_list, list) > >> + if (filter->val == info.val) { > >> + list_del(&filter->list); > >> + kfree(filter); > >> + break; > >> + } > >> + } > >> + > >> + /* Update the available port mask */ > >> + if (!info.is_port) > >> + continue; > >> + > >> + if (info.is_add) > >> + hisi_ptt->port_mask |= info.val; > >> + else > >> + hisi_ptt->port_mask &= ~info.val; > >> + } > >> + > >> + mutex_unlock(&hisi_ptt->mutex); > >> +} > >> + > >> +static void hisi_ptt_update_fifo_in(struct hisi_ptt *hisi_ptt, > >> + struct hisi_ptt_filter_update_info *info) > >> +{ > >> + struct pci_dev *root_port = pcie_find_root_port(info->pdev); > >> + > >> + if (!root_port) > >> + return; > >> + > >> + info->port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn); > >> + if (info->port_devid < hisi_ptt->lower || > >> + info->port_devid > hisi_ptt->upper) > >> + return; > >> + > >> + info->is_port = pci_pcie_type(info->pdev) == PCI_EXP_TYPE_ROOT_PORT; > >> + info->val = hisi_ptt_get_filter_val(info->pdev); > >> + > >> + if (kfifo_in_spinlocked(&hisi_ptt->filter_update_kfifo, info, 1, > >> + &hisi_ptt->filter_update_lock)) > >> + schedule_delayed_work(&hisi_ptt->work, 0); > >> + else > >> + pci_warn(hisi_ptt->pdev, > >> + "filter update fifo overflow for target %s\n", > >> + pci_name(info->pdev)); > >> +} > >> + > >> +/* > >> + * A PCI bus notifier is used here for dynamically updating the filter > >> + * list. > >> + */ > >> +static int hisi_ptt_notifier_call(struct notifier_block *nb, unsigned long action, > >> + void *data) > >> +{ > >> + struct hisi_ptt *hisi_ptt = container_of(nb, struct hisi_ptt, hisi_ptt_nb); > >> + struct hisi_ptt_filter_update_info info; > >> + struct device *dev = data; > >> + struct pci_dev *pdev = to_pci_dev(dev); > >> + > >> + info.pdev = pdev; > >> + > >> + switch (action) { > >> + case BUS_NOTIFY_ADD_DEVICE: > >> + info.is_add = true; > >> + break; > >> + case BUS_NOTIFY_DEL_DEVICE: > >> + info.is_add = false; > >> + break; > >> + default: > >> + return 0; > >> + } > >> + > >> + hisi_ptt_update_fifo_in(hisi_ptt, &info); > >> + > >> + return 0; > >> +} > >> + > >> +static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) > >> +{ > >> + struct hisi_ptt_filter_update_info info = { > >> + .pdev = pdev, > >> + .is_add = true, > >> + }; > >> + struct hisi_ptt *hisi_ptt = data; > >> + > >> + hisi_ptt_update_fifo_in(hisi_ptt, &info); > >> + > >> + return 0; > >> +} > >> + > >> +static void hisi_ptt_release_filters(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct hisi_ptt_filter_desc *filter, *tfilter; > >> + > >> + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->req_filters, list) { > >> + list_del(&filter->list); > >> + kfree(filter); > >> + } > >> + > >> + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->port_filters, list) { > >> + list_del(&filter->list); > >> + kfree(filter); > >> + } > >> +} > >> + > >> +static void hisi_ptt_init_ctrls(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct pci_dev *pdev = hisi_ptt->pdev; > >> + struct pci_bus *bus; > >> + u32 reg; > >> + > >> + INIT_DELAYED_WORK(&hisi_ptt->work, hisi_ptt_update_filters); > >> + spin_lock_init(&hisi_ptt->filter_update_lock); > >> + INIT_KFIFO(hisi_ptt->filter_update_kfifo); > >> + INIT_LIST_HEAD(&hisi_ptt->port_filters); > >> + INIT_LIST_HEAD(&hisi_ptt->req_filters); > >> + > >> + /* > >> + * The device range register provides the information about the > >> + * root ports which the RCiEP can control and trace. The RCiEP > >> + * and the root ports it support are on the same PCIe core, with > >> + * same domain number but maybe different bus number. The device > >> + * range register will tell us which root ports we can support, > >> + * Bit[31:16] indicates the upper BDF numbers of the root port, > >> + * while Bit[15:0] indicates the lower. > >> + */ > >> + reg = readl(hisi_ptt->iobase + HISI_PTT_DEVICE_RANGE); > >> + hisi_ptt->upper = reg >> 16; > >> + hisi_ptt->lower = reg & 0xffff; > >> + hisi_ptt->busnr = PCI_BUS_NUM(hisi_ptt->upper); > >> + > >> + reg = readl(hisi_ptt->iobase + HISI_PTT_LOCATION); > >> + hisi_ptt->core_id = FIELD_GET(HISI_PTT_CORE_ID, reg); > >> + hisi_ptt->sicl_id = FIELD_GET(HISI_PTT_SICL_ID, reg); > >> + > >> + bus = pci_find_bus(pci_domain_nr(pdev->bus), hisi_ptt->busnr); > >> + if (bus) > >> + pci_walk_bus(bus, hisi_ptt_init_filters, hisi_ptt); > > > > What happens if bus is NULL? Should this be reported to the caller and cause > > hisi_ptt_probe() to fail? Please add a comment that describes the scenario. > > > > It's ok if the list is NULL in the probe process, > as the device maybe hotplugged after the PTT driver probe, in which case > we can detect the event and update the list as we register a bus notifier. > Please add the above as a comment in the code. > >> + > >> + /* Initialize trace controls */ > >> + INIT_LIST_HEAD(&hisi_ptt->trace_ctrl.trace_buf); > >> + hisi_ptt->trace_ctrl.buflet_size = HISI_PTT_TRACE_BUFLET_SIZE; > >> + hisi_ptt->trace_ctrl.default_cpu = cpumask_first(cpumask_of_node(dev_to_node(&pdev->dev))); > >> +} > >> + > >> +#define HISI_PTT_PMU_FILTER_IS_PORT BIT(19) > >> +#define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0) > >> +#define HISI_PTT_PMU_DIRECTION_MASK GENMASK(23, 20) > >> +#define HISI_PTT_PMU_TYPE_MASK GENMASK(31, 24) > >> +#define HISI_PTT_PMU_FORMAT_MASK GENMASK(35, 32) > >> + > >> +static ssize_t available_filters_show(struct device *dev, > >> + struct device_attribute *attr, > >> + char *buf) > >> +{ > >> + struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev)); > >> + struct hisi_ptt_filter_desc *filter; > >> + int pos = 0; > >> + > >> + if (list_empty(&hisi_ptt->port_filters)) > >> + return sysfs_emit(buf, "#### No available filter ####\n"); > >> + > >> + mutex_lock(&hisi_ptt->mutex); > >> + pos += sysfs_emit_at(buf, pos, "#### Root Ports ####\n"); > >> + list_for_each_entry(filter, &hisi_ptt->port_filters, list) > >> + pos += sysfs_emit_at(buf, pos, "%s 0x%05lx\n", > >> + pci_name(filter->pdev), > >> + hisi_ptt_get_filter_val(filter->pdev) | > >> + HISI_PTT_PMU_FILTER_IS_PORT); > >> + > >> + pos += sysfs_emit_at(buf, pos, "#### Requesters ####\n"); > >> + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > >> + pos += sysfs_emit_at(buf, pos, "%s 0x%05x\n", > >> + pci_name(filter->pdev), > >> + hisi_ptt_get_filter_val(filter->pdev)); > >> + > >> + mutex_unlock(&hisi_ptt->mutex); > >> + return pos; > >> +} > >> +static DEVICE_ATTR_ADMIN_RO(available_filters); > >> + > >> +PMU_FORMAT_ATTR(filter, "config:0-19"); > >> +PMU_FORMAT_ATTR(direction, "config:20-23"); > >> +PMU_FORMAT_ATTR(type, "config:24-31"); > >> +PMU_FORMAT_ATTR(format, "config:32-35"); > >> + > >> +static struct attribute *hisi_ptt_pmu_format_attrs[] = { > >> + &format_attr_filter.attr, > >> + &format_attr_direction.attr, > >> + &format_attr_type.attr, > >> + &format_attr_format.attr, > >> + NULL > >> +}; > >> + > >> +static struct attribute_group hisi_ptt_pmu_format_group = { > >> + .name = "format", > >> + .attrs = hisi_ptt_pmu_format_attrs, > >> +}; > >> + > >> +static struct attribute *hisi_ptt_pmu_filter_attrs[] = { > >> + &dev_attr_available_filters.attr, > >> + NULL > >> +}; > >> + > >> +static struct attribute_group hisi_ptt_pmu_filter_group = { > >> + .attrs = hisi_ptt_pmu_filter_attrs, > >> +}; > >> + > >> +static const struct attribute_group *hisi_ptt_pmu_groups[] = { > >> + &hisi_ptt_pmu_format_group, > >> + &hisi_ptt_pmu_filter_group, > >> + NULL > >> +}; > >> + > >> +/* > >> + * The supported value of the direction parameter. See hisi_ptt.rst > >> + * documentation for more details. > >> + */ > >> +static u32 hisi_ptt_trace_available_direction[] = { > >> + 0, > >> + 1, > >> + 2, > >> + 3, > >> +}; > >> + > >> +/* Different types can be set simultaneously */ > >> +static u32 hisi_ptt_trace_available_type[] = { > >> + 1, /* posted_request */ > >> + 2, /* non-posted_request */ > >> + 4, /* completion */ > >> +}; > >> + > >> +static u32 hisi_ptt_trace_availble_format[] = { > >> + 0, /* 4DW */ > >> + 1, /* 8DW */ > >> +}; > >> + > >> +/* > >> + * Check whether the config is valid or not. Some configs are multi-selectable > >> + * and can be set simultaneously, while some are single selectable (onehot). > >> + * Use this function to check the non-onehot configs while > >> + * hisi_ptt_trace_valid_config_onehot() for the onehot ones. > >> + */ > >> +static int hisi_ptt_trace_valid_config(u32 val, u32 *available_list, u32 list_size) > >> +{ > >> + int i; > >> + > >> + /* > >> + * The non-onehot configs cannot be 0. Walk the available > >> + * list and clear the valid bits of the config. If there > >> + * is any resident bit after the walk then the config is > >> + * invalid. > >> + */ > >> + for (i = 0; i < list_size; i++) > >> + val &= ~available_list[i]; > >> + > >> + return val ? -EINVAL : 0; > >> +} > >> + > >> +static int hisi_ptt_trace_valid_config_onehot(u32 val, u32 *available_list, u32 list_size) > >> +{ > >> + int i, ret = -EINVAL; > >> + > >> + for (i = 0; i < list_size; i++) > >> + if (val == available_list[i]) { > >> + ret = 0; > >> + break; > >> + } > >> + > >> + return ret; > >> +} > >> + > >> +static int hisi_ptt_trace_init_filter(struct hisi_ptt *hisi_ptt, u64 config) > >> +{ > >> + unsigned long val, port_mask = hisi_ptt->port_mask; > >> + struct hisi_ptt_filter_desc *filter; > >> + int ret = -EINVAL; > >> + > >> + hisi_ptt->trace_ctrl.is_port = FIELD_GET(HISI_PTT_PMU_FILTER_IS_PORT, config); > >> + val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, config); > >> + > >> + /* > >> + * Port filters are defined as bit mask. For port filters, check > >> + * the bits in the @val are within the range of hisi_ptt->port_mask > >> + * and whether it's empty or not, otherwise user has specified > >> + * some unsupported root ports. > >> + * > >> + * For Requester ID filters, walk the available filter list to see > >> + * whether we have one matched. > >> + */ > >> + if (hisi_ptt->trace_ctrl.is_port && > >> + bitmap_subset(&val, &port_mask, BITS_PER_LONG)) { > >> + ret = 0; > >> + } else { > >> + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > >> + if (filter->val == val) { > >> + ret = 0; > >> + break; > >> + } > >> + } > >> + > >> + if (ret) > >> + return ret; > >> + > >> + hisi_ptt->trace_ctrl.filter = val; > >> + return 0; > >> +} > >> + > >> +static int hisi_ptt_pmu_event_init(struct perf_event *event) > >> +{ > >> + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > >> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > >> + int ret; > >> + u32 val; > >> + > >> + if (event->attr.type != hisi_ptt->hisi_ptt_pmu.type) > >> + return -ENOENT; > >> + > >> + mutex_lock(&hisi_ptt->mutex); > >> + > >> + ret = hisi_ptt_trace_init_filter(hisi_ptt, event->attr.config); > >> + if (ret < 0) > >> + goto out; > >> + > >> + val = FIELD_GET(HISI_PTT_PMU_DIRECTION_MASK, event->attr.config); > >> + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_available_direction, > >> + ARRAY_SIZE(hisi_ptt_trace_available_direction)); > >> + if (ret < 0) > >> + goto out; > >> + ctrl->direction = val; > >> + > >> + val = FIELD_GET(HISI_PTT_PMU_TYPE_MASK, event->attr.config); > >> + > >> + ret = hisi_ptt_trace_valid_config(val, hisi_ptt_trace_available_type, > >> + ARRAY_SIZE(hisi_ptt_trace_available_type)); > >> + if (ret < 0) > >> + goto out; > >> + ctrl->type = val; > >> + > >> + val = FIELD_GET(HISI_PTT_PMU_FORMAT_MASK, event->attr.config); > >> + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_availble_format, > >> + ARRAY_SIZE(hisi_ptt_trace_availble_format)); > >> + if (ret < 0) > >> + goto out; > >> + ctrl->format = val; > >> + > >> +out: > >> + mutex_unlock(&hisi_ptt->mutex); > >> + return ret; > >> +} > >> + > >> +static void *hisi_ptt_pmu_setup_aux(struct perf_event *event, void **pages, > >> + int nr_pages, bool overwrite) > >> +{ > >> + struct hisi_ptt_pmu_buf *buf; > >> + struct page **pagelist; > >> + int i; > >> + > >> + if (overwrite) { > >> + dev_warn(event->pmu->dev, "Overwrite mode is not supported\n"); > >> + return NULL; > >> + } > >> + > >> + /* If the pages size less than buflets, we cannot start trace */ > >> + if (nr_pages < HISI_PTT_TRACE_BUFFER_SIZE / PAGE_SIZE) > >> + return NULL; > >> + > >> + buf = kzalloc(sizeof(*buf), GFP_KERNEL); > >> + if (!buf) > >> + return NULL; > >> + > >> + pagelist = kcalloc(nr_pages, sizeof(*pagelist), GFP_KERNEL); > >> + if (!pagelist) { > >> + kfree(buf); > >> + return NULL; > >> + } > >> + > >> + for (i = 0; i < nr_pages; i++) > >> + pagelist[i] = virt_to_page(pages[i]); > >> + > >> + buf->base = vmap(pagelist, nr_pages, VM_MAP, PAGE_KERNEL); > >> + if (!buf->base) { > >> + kfree(pagelist); > >> + kfree(buf); > >> + return NULL; > >> + } > >> + > >> + buf->nr_pages = nr_pages; > >> + buf->length = nr_pages * PAGE_SIZE; > >> + buf->pos = 0; > >> + > >> + kfree(pagelist); > >> + return buf; > >> +} > >> + > >> +static void hisi_ptt_pmu_free_aux(void *aux) > >> +{ > >> + struct hisi_ptt_pmu_buf *buf = aux; > >> + > >> + vunmap(buf->base); > >> + kfree(buf); > >> +} > >> + > >> +static void hisi_ptt_pmu_start(struct perf_event *event, int flags) > >> +{ > >> + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > >> + struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle; > >> + struct hw_perf_event *hwc = &event->hw; > >> + struct hisi_ptt_pmu_buf *buf; > >> + int cpu = event->cpu; > >> + int ret; > >> + > >> + hwc->state = 0; > >> + mutex_lock(&hisi_ptt->mutex); > >> + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) { > >> + pci_dbg(hisi_ptt->pdev, "trace has already started\n"); > >> + goto stop; > >> + } > >> + > >> + if (cpu == -1) > >> + cpu = hisi_ptt->trace_ctrl.default_cpu; > >> + > >> + /* > >> + * Handle the interrupt on the same cpu which starts the trace to avoid > >> + * context mismatch. Otherwise we'll trigger the WARN from the perf > >> + * core in event_function_local(). > >> + */ > >> + WARN_ON(irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ), > >> + cpumask_of(cpu))); > >> + > >> + ret = hisi_ptt_alloc_trace_buf(hisi_ptt); > >> + if (ret) { > >> + pci_dbg(hisi_ptt->pdev, "alloc trace buf failed, ret = %d\n", ret); > >> + goto stop; > >> + } > >> + > >> + buf = perf_aux_output_begin(handle, event); > >> + if (!buf) { > >> + pci_dbg(hisi_ptt->pdev, "aux output begin failed\n"); > >> + goto stop; > >> + } > >> + > >> + buf->pos = handle->head % buf->length; > >> + > >> + ret = hisi_ptt_trace_start(hisi_ptt); > >> + if (ret) { > >> + pci_dbg(hisi_ptt->pdev, "trace start failed, ret = %d\n", ret); > >> + perf_aux_output_end(handle, 0); > >> + goto stop; > >> + } > >> + > >> + mutex_unlock(&hisi_ptt->mutex); > >> + return; > >> +stop: > >> + event->hw.state |= PERF_HES_STOPPED; > >> + mutex_unlock(&hisi_ptt->mutex); > >> +} > >> + > >> +static void hisi_ptt_pmu_stop(struct perf_event *event, int flags) > >> +{ > >> + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > >> + struct hw_perf_event *hwc = &event->hw; > >> + > >> + if (hwc->state & PERF_HES_STOPPED) > >> + return; > >> + > >> + mutex_lock(&hisi_ptt->mutex); > >> + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) { > >> + hisi_ptt_trace_end(hisi_ptt); > >> + WARN(hisi_ptt_wait_trace_hw_idle(hisi_ptt), "Device is still busy"); > >> + hisi_ptt_update_aux(hisi_ptt, hisi_ptt->trace_ctrl.buf_index, true); > >> + } > >> + mutex_unlock(&hisi_ptt->mutex); > >> + > >> + hwc->state |= PERF_HES_STOPPED; > >> + perf_event_update_userpage(event); > >> + hwc->state |= PERF_HES_UPTODATE; > >> +} > >> + > >> +static int hisi_ptt_pmu_add(struct perf_event *event, int flags) > >> +{ > >> + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > >> + struct hw_perf_event *hwc = &event->hw; > >> + int cpu = event->cpu; > >> + > >> + if (cpu == -1 && smp_processor_id() != hisi_ptt->trace_ctrl.default_cpu) > >> + return 0; > >> + > >> + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; > >> + > >> + if (flags & PERF_EF_START) { > >> + hisi_ptt_pmu_start(event, PERF_EF_RELOAD); > >> + if (hwc->state & PERF_HES_STOPPED) > >> + return -EINVAL; > >> + } > >> + > >> + return 0; > >> +} > >> + > >> +static void hisi_ptt_pmu_del(struct perf_event *event, int flags) > >> +{ > >> + hisi_ptt_pmu_stop(event, PERF_EF_UPDATE); > >> +} > >> + > >> +static void hisi_ptt_unregister_pmu(void *priv) > >> +{ > >> + perf_pmu_unregister(priv); > >> +} > >> + > >> +static int hisi_ptt_register_pmu(struct hisi_ptt *hisi_ptt) > >> +{ > >> + char *pmu_name; > >> + int ret; > >> + > >> + hisi_ptt->hisi_ptt_pmu = (struct pmu) { > >> + .module = THIS_MODULE, > >> + .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, > >> + .task_ctx_nr = perf_sw_context, > >> + .attr_groups = hisi_ptt_pmu_groups, > >> + .event_init = hisi_ptt_pmu_event_init, > >> + .setup_aux = hisi_ptt_pmu_setup_aux, > >> + .free_aux = hisi_ptt_pmu_free_aux, > >> + .start = hisi_ptt_pmu_start, > >> + .stop = hisi_ptt_pmu_stop, > >> + .add = hisi_ptt_pmu_add, > >> + .del = hisi_ptt_pmu_del, > >> + }; > >> + > >> + pmu_name = devm_kasprintf(&hisi_ptt->pdev->dev, GFP_KERNEL, "hisi_ptt%u_%u", > >> + hisi_ptt->sicl_id, hisi_ptt->core_id); > >> + if (!pmu_name) > >> + return -ENOMEM; > >> + > >> + ret = perf_pmu_register(&hisi_ptt->hisi_ptt_pmu, pmu_name, -1); > >> + if (ret) > >> + return ret; > >> + > >> + return devm_add_action_or_reset(&hisi_ptt->pdev->dev, > >> + hisi_ptt_unregister_pmu, > >> + &hisi_ptt->hisi_ptt_pmu); > >> +} > >> + > >> +/* > >> + * Get RMR address if provided by the firmware. > >> + * Return 0 if the IOMMU doesn't present or the policy of the > >> + * IOMMU domain is passthrough or we get a usable RMR region. > >> + * Otherwise a negative value is returned. > >> + */ > >> +static int hisi_ptt_get_rmr(struct hisi_ptt *hisi_ptt) > >> +{ > >> + struct pci_dev *pdev = hisi_ptt->pdev; > >> + struct iommu_domain *iommu_domain; > >> + struct iommu_resv_region *region; > >> + LIST_HEAD(list); > >> + > >> + /* > >> + * Use direct DMA if IOMMU does not present or the policy of the > >> + * IOMMU domain is passthrough. > >> + */ > >> + iommu_domain = iommu_get_domain_for_dev(&pdev->dev); > >> + if (!iommu_domain || iommu_domain->type == IOMMU_DOMAIN_IDENTITY) > >> + return 0; > >> + > >> + iommu_get_resv_regions(&pdev->dev, &list); > >> + list_for_each_entry(region, &list, list) > >> + if (region->type == IOMMU_RESV_DIRECT && > >> + region->length >= HISI_PTT_TRACE_BUFFER_SIZE) { > >> + hisi_ptt->trace_ctrl.has_rmr = true; > >> + hisi_ptt->trace_ctrl.rmr_addr = region->start; > >> + hisi_ptt->trace_ctrl.rmr_length = region->length; > >> + break; > >> + } > >> + > >> + iommu_put_resv_regions(&pdev->dev, &list); > >> + return hisi_ptt->trace_ctrl.has_rmr ? 0 : -ENOMEM; > >> +} > >> + > >> +static int hisi_ptt_probe(struct pci_dev *pdev, > >> + const struct pci_device_id *id) > >> +{ > >> + struct hisi_ptt *hisi_ptt; > >> + int ret; > >> + > >> + hisi_ptt = devm_kzalloc(&pdev->dev, sizeof(*hisi_ptt), GFP_KERNEL); > >> + if (!hisi_ptt) > >> + return -ENOMEM; > >> + > >> + mutex_init(&hisi_ptt->mutex); > >> + hisi_ptt->pdev = pdev; > >> + > >> + /* > >> + * Lifetime of pci_dev is longer than hisi_ptt, > >> + * so directly reference to the pci name string. > >> + */ > >> + hisi_ptt->name = pci_name(hisi_ptt->pdev); > >> + pci_set_drvdata(pdev, hisi_ptt); > >> + > >> + ret = pcim_enable_device(pdev); > >> + if (ret) { > >> + pci_err(pdev, "failed to enable device, ret = %d.\n", ret); > >> + return ret; > >> + } > >> + > >> + ret = pcim_iomap_regions(pdev, BIT(2), hisi_ptt->name); > >> + if (ret) { > >> + pci_err(pdev, "failed to remap io memory, ret = %d.\n", ret); > >> + return ret; > >> + } > >> + > >> + hisi_ptt->iobase = pcim_iomap_table(pdev)[2]; > >> + > >> + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); > >> + if (ret) { > >> + pci_err(pdev, "failed to set 64 bit dma mask, ret = %d.\n", ret); > >> + return ret; > >> + } > >> + pci_set_master(pdev); > >> + > >> + ret = hisi_ptt_register_irq(hisi_ptt); > >> + if (ret) > >> + return ret; > >> + > >> + hisi_ptt_init_ctrls(hisi_ptt); > >> + > >> + ret = hisi_ptt_register_pmu(hisi_ptt); > >> + if (ret) { > >> + pci_err(pdev, "failed to register pmu device, ret = %d", ret); > >> + return ret; > >> + } > > > > If this fails the pci_free_irq_vectors() is not called. > > > > It'll be called as we've registered a devm callback when > allocating the irq vector. See hisi_ptt_register_irq(). Ah yes - thanks for pointing that out. > > > I am out of time for today - I will continue tomorrow. > > > > Sure. Thanks! > Yicong > > > Thanks, > > Mathieu > > > >> + > >> + ret = hisi_ptt_get_rmr(hisi_ptt); > >> + if (ret) { > >> + pci_err(pdev, "failed to get RMR region, ret = %d", ret); > >> + return ret; > >> + } > >> + > >> + /* Register the bus notifier for dynamically updating the filter list */ > >> + hisi_ptt->hisi_ptt_nb.notifier_call = hisi_ptt_notifier_call; > >> + ret = bus_register_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb); > >> + if (ret) > >> + pci_warn(pdev, "failed to register filter update notifier, ret = %d", ret); > >> + > >> + return 0; > >> +} > >> + > >> +void hisi_ptt_remove(struct pci_dev *pdev) > >> +{ > >> + struct hisi_ptt *hisi_ptt = pci_get_drvdata(pdev); > >> + > >> + bus_unregister_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb); > >> + > >> + /* Cancel any work that has been queued */ > >> + cancel_delayed_work_sync(&hisi_ptt->work); > >> + > >> + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) > >> + hisi_ptt_trace_end(hisi_ptt); > >> + > >> + hisi_ptt_free_trace_buf(hisi_ptt); > >> + hisi_ptt_release_filters(hisi_ptt); > >> +} > >> + > >> +static const struct pci_device_id hisi_ptt_id_tbl[] = { > >> + { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa12e) }, > >> + { } > >> +}; > >> +MODULE_DEVICE_TABLE(pci, hisi_ptt_id_tbl); > >> + > >> +static struct pci_driver hisi_ptt_driver = { > >> + .name = "hisi_ptt", > >> + .id_table = hisi_ptt_id_tbl, > >> + .probe = hisi_ptt_probe, > >> + .remove = hisi_ptt_remove, > >> +}; > >> +module_pci_driver(hisi_ptt_driver); > >> + > >> +MODULE_LICENSE("GPL v2"); > >> +MODULE_AUTHOR("Yicong Yang <yangyicong(a)hisilicon.com>"); > >> +MODULE_DESCRIPTION("Driver for HiSilicon PCIe tune and trace device"); > >> -- > >> 2.33.0 > >> > > . > >

2 years, 11 months

Re: [PATCH v2 2/6] hwtracing: Add trace function support for HiSilicon PCIe Tune and Trace device

by Mathieu Poirier

Hi Yicong, On Tue, Nov 16, 2021 at 05:06:21PM +0800, Yicong Yang wrote: > HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex > integrated Endpoint(RCiEP) device, providing the capability > to dynamically monitor and tune the PCIe traffic(tune), > and trace the TLP headers(trace). > Is there a reason to put "tune" and "trace" are whithin parentheses? > Add the driver for the device to enable the trace function. The driver > will create PMU device for each PTT device, and users can start trace > through perf command. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > drivers/Makefile | 1 + > drivers/hwtracing/Kconfig | 2 + > drivers/hwtracing/hisilicon/Kconfig | 8 + > drivers/hwtracing/hisilicon/Makefile | 2 + > drivers/hwtracing/hisilicon/hisi_ptt.c | 1146 ++++++++++++++++++++++++ Not sure about the "hisilicon" directory. Right now we have "coresight", "intel_th" and "stm" - they concentrate on the technology rather than the vendor. I think "ptt" would be just fine: drivers/hwtracing/ptt/Kconfig drivers/hwtracing/ptt/Makefile drivers/hwtracing/ptt/hisi_ptt.c That way if other vendors want to introduce support for the same kind of technology we can simply put them under "drivers/hwtracing/ptt/" and things are still accurate. > 5 files changed, 1159 insertions(+) > create mode 100644 drivers/hwtracing/hisilicon/Kconfig > create mode 100644 drivers/hwtracing/hisilicon/Makefile > create mode 100644 drivers/hwtracing/hisilicon/hisi_ptt.c > > diff --git a/drivers/Makefile b/drivers/Makefile > index be5d40ae1488..bb0dc9b55ea2 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -176,6 +176,7 @@ obj-$(CONFIG_USB4) += thunderbolt/ > obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ > obj-y += hwtracing/intel_th/ > obj-$(CONFIG_STM) += hwtracing/stm/ > +obj-$(CONFIG_HISI_PTT) += hwtracing/hisilicon/ > obj-$(CONFIG_ANDROID) += android/ > obj-$(CONFIG_NVMEM) += nvmem/ > obj-$(CONFIG_FPGA) += fpga/ > diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig > index 13085835a636..e3796b17541a 100644 > --- a/drivers/hwtracing/Kconfig > +++ b/drivers/hwtracing/Kconfig > @@ -5,4 +5,6 @@ source "drivers/hwtracing/stm/Kconfig" > > source "drivers/hwtracing/intel_th/Kconfig" > > +source "drivers/hwtracing/hisilicon/Kconfig" > + > endmenu > diff --git a/drivers/hwtracing/hisilicon/Kconfig b/drivers/hwtracing/hisilicon/Kconfig > new file mode 100644 > index 000000000000..9c3ab80d99fe > --- /dev/null > +++ b/drivers/hwtracing/hisilicon/Kconfig > @@ -0,0 +1,8 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config HISI_PTT > + tristate "HiSilicon PCIe Tune and Trace Device" > + depends on PCI && HAS_DMA && HAS_IOMEM What Arm architecture are you aiming this for? Can it be found on both armv7 and armv8? > + help > + HiSilicon PCIe Tune and Trace Device exist as a PCIe RCiEP > + device, provides support for PCIe traffic tuning and > + tracing TLP headers to the memory. Please indicate what the name of the driver will be when compiled as a module. > diff --git a/drivers/hwtracing/hisilicon/Makefile b/drivers/hwtracing/hisilicon/Makefile > new file mode 100644 > index 000000000000..908c09a98161 > --- /dev/null > +++ b/drivers/hwtracing/hisilicon/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +obj-$(CONFIG_HISI_PTT) += hisi_ptt.o > diff --git a/drivers/hwtracing/hisilicon/hisi_ptt.c b/drivers/hwtracing/hisilicon/hisi_ptt.c > new file mode 100644 > index 000000000000..e11e9b6cc2a8 > --- /dev/null > +++ b/drivers/hwtracing/hisilicon/hisi_ptt.c > @@ -0,0 +1,1146 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Driver for HiSilicon PCIe tune and trace device > + * > + * Copyright (c) 2021 HiSilicon Limited. > + */ > + > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/delay.h> > +#include <linux/dma-iommu.h> > +#include <linux/dma-mapping.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/iommu.h> > +#include <linux/iopoll.h> > +#include <linux/kfifo.h> > +#include <linux/module.h> > +#include <linux/notifier.h> > +#include <linux/pci.h> > +#include <linux/perf_event.h> > +#include <linux/sizes.h> > +#include <linux/sysfs.h> > +#include <linux/vmalloc.h> > +#include <linux/workqueue.h> > + > +#define HISI_PTT_TRACE_ADDR_SIZE 0x0800 > +#define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810 > +#define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814 > +#define HISI_PTT_TRACE_ADDR_STRIDE 0x8 > +#define HISI_PTT_TRACE_CTRL 0x0850 > +#define HISI_PTT_TRACE_CTRL_EN BIT(0) > +#define HISI_PTT_TRACE_CTRL_RST BIT(1) > +#define HISI_PTT_TRACE_CTRL_RXTX_SEL GENMASK(3, 2) > +#define HISI_PTT_TRACE_CTRL_TYPE_SEL GENMASK(7, 4) > +#define HISI_PTT_TRACE_CTRL_DATA_FORMAT BIT(14) > +#define HISI_PTT_TRACE_CTRL_FILTER_MODE BIT(15) > +#define HISI_PTT_TRACE_CTRL_TARGET_SEL GENMASK(31, 16) > +#define HISI_PTT_TRACE_INT_STAT 0x0890 > +#define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0) > +#define HISI_PTT_TRACE_INT_MASK 0x0894 > +#define HISI_PTT_TRACE_WR_STS 0x08a0 > +#define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0) > +#define HISI_PTT_TRACE_WR_STS_BUFFER GENMASK(29, 28) > +#define HISI_PTT_TRACE_STS 0x08b0 > +#define HISI_PTT_TRACE_IDLE BIT(0) > +#define HISI_PTT_DEVICE_RANGE 0x0fe0 > +#define HISI_PTT_LOCATION 0x0fe8 > +#define HISI_PTT_CORE_ID GENMASK(15, 0) > +#define HISI_PTT_SICL_ID GENMASK(31, 16) Extra spaces between #define and the literals. Please align the values with that of HISI_PTT_TRACE_DMA_IRQ below. > + > +#define HISI_PTT_TRACE_DMA_IRQ 0 > +#define HISI_PTT_TRACE_BUFLETS_CNT 4 > +#define HISI_PTT_TRACE_BUFLET_SIZE SZ_4M > +#define HISI_PTT_TRACE_BUFFER_SIZE (HISI_PTT_TRACE_BUFLET_SIZE * \ > + HISI_PTT_TRACE_BUFLETS_CNT) > +#define HISI_PTT_FILTER_UPDATE_FIFO_SIZE 16 > + > +/* Delay time for filter updating work */ > +#define HISI_PTT_WORK_DELAY_MS 100UL > +/* Wait time for DMA hardware to reset */ > +#define HISI_PTT_RESET_WAIT_MS 1000UL > +/* Poll timeout and interval for waiting hardware work to finish */ > +#define HISI_PTT_WAIT_TIMEOUT_US 1000000UL > +#define HISI_PTT_WAIT_POLL_INTERVAL_US 100UL > + > +#define HISI_PCIE_CORE_PORT_ID(devfn) (PCI_FUNC(devfn) << 1) > + > +enum hisi_ptt_trace_status { > + HISI_PTT_TRACE_STATUS_OFF = 0, > + HISI_PTT_TRACE_STATUS_ON, > +}; > + > +struct hisi_ptt_dma_buflet { I'm not sure what a "buflet" is... Probably best to just call this hisi_ptt_dma_buffer" if it pertains to a buffer. On that note it is hard to know due to the lack of proper structure documentation. Please have a look at how "coresight_device" is documented. The same applies to the rest of the structures declared below. > + struct list_head list; > + unsigned int size; > + dma_addr_t dma; > + > + /* > + * The address of the buflet holding the trace data. > + * See Documentation/trace/hisi-ptt.rst for the details As of this writing, hisi-ptt.rst doesn't exist. > + * of the data format. > + */ > + void *addr; > + int index; > +}; > + > +struct hisi_ptt_trace_ctrl { > + enum hisi_ptt_trace_status status; > + struct perf_output_handle handle; > + struct list_head trace_buf; > + /* > + * The index of the buffer which trace data > + * currently is writing to. > + */ > + u32 buf_index; > + > + int default_cpu; > + u32 buflet_size; > + bool is_port; > + u32 format:1; /* Format of the traced TLP headers */ > + u32 type:4; /* Type of the TLP headers to trace */ > + u32 direction:2; /* Direction of the TLP headers to trace */ > + u32 filter:16; /* Root port or Requester to filter the TLP headers */ > + > + phys_addr_t rmr_addr; > + size_t rmr_length; > + bool has_rmr; > +}; > + > +struct hisi_ptt_filter_desc { > + struct list_head list; > + struct pci_dev *pdev; > + u16 val; > +}; > + > +struct hisi_ptt_pmu_buf { > + size_t length; > + int nr_pages; > + void *base; > + long pos; > +}; > + > +/* Structure containing the information for filter updating */ > +struct hisi_ptt_filter_update_info { > + struct pci_dev *pdev; > + u32 port_devid; > + bool is_port; > + bool is_add; > + u16 val; > +}; > + > +struct hisi_ptt { > + struct hisi_ptt_trace_ctrl trace_ctrl; > + struct notifier_block hisi_ptt_nb; > + struct pmu hisi_ptt_pmu; > + void __iomem *iobase; > + struct pci_dev *pdev; > + /* > + * Use the mutex to protect the filter list and > + * serialize the perf process. > + */ > + struct mutex mutex; > + const char *name; > + u16 core_id; > + u16 sicl_id; > + /* PCI device range managed by the PTT device */ > + u32 upper; > + u32 lower; > + u8 busnr; > + > + /* > + * The trace TLP headers can either be filtered by certain > + * root port, or by the requester ID. Organize the filters > + * by @port_filters and @req_filters here. The mask of all > + * the valid ports is also cached for doing sanity check > + * of user input. > + */ > + struct list_head port_filters; > + struct list_head req_filters; > + u16 port_mask; > + > + /* > + * We use a delayed work here to avoid indefinitely waiting for > + * the hisi_ptt->mutex which protecting the filter list. The > + * work will be delayed only if the mutex can not be held, > + * otherwise no delay will be applied. > + */ > + struct delayed_work work; > + spinlock_t filter_update_lock; > + DECLARE_KFIFO(filter_update_kfifo, struct hisi_ptt_filter_update_info, > + HISI_PTT_FILTER_UPDATE_FIFO_SIZE); > +}; It might be a good idea to spinoff a hisi_ptt.h for the above declarations. > + > +static inline struct hisi_ptt *to_hisi_ptt(struct pmu *pmu) > +{ > + return container_of(pmu, struct hisi_ptt, hisi_ptt_pmu); > +} I'm not sure there is any value to this inline function. I suggest to simply call container_of() whenever it is needed. > + > +static u16 hisi_ptt_get_filter_val(struct pci_dev *pdev) > +{ > + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) > + return BIT(HISI_PCIE_CORE_PORT_ID(PCI_SLOT(pdev->devfn))); > + > + return PCI_DEVID(pdev->bus->number, pdev->devfn); > +} > + > +static int hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt) > +{ > + u32 val; > + > + return readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TRACE_STS, val, > + val & HISI_PTT_TRACE_IDLE, > + HISI_PTT_WAIT_POLL_INTERVAL_US, > + HISI_PTT_WAIT_TIMEOUT_US); > +} > + > +static void hisi_ptt_free_trace_buf(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct device *dev = &hisi_ptt->pdev->dev; > + struct hisi_ptt_dma_buflet *buflet, *tbuflet; > + > + list_for_each_entry_safe(buflet, tbuflet, &ctrl->trace_buf, list) { > + list_del(&buflet->list); > + > + if (ctrl->has_rmr) > + memunmap(buflet->addr); > + else > + dma_free_coherent(dev, buflet->size, buflet->addr, > + buflet->dma); > + > + kfree(buflet); > + } > +} > + > +static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct device *dev = &hisi_ptt->pdev->dev; > + struct hisi_ptt_dma_buflet *buflet; > + int i, ret; > + > + hisi_ptt->trace_ctrl.buf_index = 0; > + > + /* Make sure the trace buffer is empty before allocating */ > + if (!list_empty(&ctrl->trace_buf)) { > + list_for_each_entry(buflet, &ctrl->trace_buf, list) > + memset(buflet->addr, 0, buflet->size); > + return 0; > + } > + > + for (i = 0; i < HISI_PTT_TRACE_BUFLETS_CNT; ++i) { > + buflet = kzalloc(sizeof(*buflet), GFP_KERNEL); > + if (!buflet) { > + ret = -ENOMEM; > + goto err; > + } > + > + if (ctrl->has_rmr) { > + phys_addr_t base = ctrl->rmr_addr + i * ctrl->buflet_size; > + > + buflet->dma = base; > + buflet->addr = memremap(base, ctrl->buflet_size, MEMREMAP_WB); > + } else { > + buflet->addr = dma_alloc_coherent(dev, ctrl->buflet_size, > + &buflet->dma, GFP_KERNEL); > + } > + > + if (!buflet->addr) { > + kfree(buflet); > + ret = -ENOMEM; > + goto err; > + } > + > + memset(buflet->addr, 0, buflet->size); > + > + buflet->index = i; > + buflet->size = ctrl->buflet_size; > + list_add_tail(&buflet->list, &ctrl->trace_buf); > + } > + > + return 0; > +err: > + hisi_ptt_free_trace_buf(hisi_ptt); > + return ret; > +} > + > +static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt) > +{ > + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + hisi_ptt->trace_ctrl.status = HISI_PTT_TRACE_STATUS_OFF; > +} > + > +static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct hisi_ptt_dma_buflet *cur; > + u32 val; > + > + /* Check device idle before start trace */ > + if (hisi_ptt_wait_trace_hw_idle(hisi_ptt)) { > + pci_err(hisi_ptt->pdev, "Failed to start trace, the device is still busy.\n"); > + return -EBUSY; > + } > + > + /* Reset the DMA before start tracing */ > + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + val |= HISI_PTT_TRACE_CTRL_RST; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + /* > + * We'll be in the perf context where preemption is disabled, > + * so use busy loop here. > + */ > + mdelay(HISI_PTT_RESET_WAIT_MS); > + > + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + val &= ~HISI_PTT_TRACE_CTRL_RST; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + /* clear the interrupt status */ > + writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK); > + > + list_for_each_entry(cur, &ctrl->trace_buf, list) { > + writel(lower_32_bits(cur->dma), > + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_LO_0 + > + cur->index * HISI_PTT_TRACE_ADDR_STRIDE); > + writel(upper_32_bits(cur->dma), > + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_HI_0 + > + cur->index * HISI_PTT_TRACE_ADDR_STRIDE); > + } > + writel(ctrl->buflet_size, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE); > + > + /* set the trace control register */ > + val = FIELD_PREP(HISI_PTT_TRACE_CTRL_TYPE_SEL, ctrl->type); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_RXTX_SEL, ctrl->direction); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_DATA_FORMAT, ctrl->format); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter); > + if (!hisi_ptt->trace_ctrl.is_port) > + val |= HISI_PTT_TRACE_CTRL_FILTER_MODE; > + > + val |= HISI_PTT_TRACE_CTRL_EN; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + ctrl->status = HISI_PTT_TRACE_STATUS_ON; > + > + return 0; > +} > + > +static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop) > +{ > + struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle; > + struct perf_event *event = handle->event; > + struct hisi_ptt_dma_buflet *cur; > + struct hisi_ptt_pmu_buf *buf; > + > + buf = perf_get_aux(handle); > + if (!buf || !handle->size) > + return -EINVAL; > + > + list_for_each_entry(cur, &hisi_ptt->trace_ctrl.trace_buf, list) > + if (cur->index == index) > + break; > + > + memcpy(buf->base + buf->pos, cur->addr, cur->size); > + memset(cur->addr, 0, cur->size); > + buf->pos += cur->size; > + > + if (stop) { > + perf_aux_output_end(handle, buf->pos); > + } else if (buf->length - buf->pos < cur->size) { > + perf_aux_output_skip(handle, buf->length - buf->pos); > + perf_aux_output_end(handle, buf->pos); > + > + buf = perf_aux_output_begin(handle, event); > + if (!buf) > + return -EINVAL; > + > + buf->pos = handle->head % buf->length; > + if (buf->length - buf->pos < cur->size) { > + perf_aux_output_end(handle, 0); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +static irqreturn_t hisi_ptt_isr(int irq, void *context) > +{ > + struct hisi_ptt *hisi_ptt = context; > + u32 status, buf_idx; > + > + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + buf_idx = ffs(status) - 1; > + > + /* Clear the interrupt status of buflet @buf_idx */ > + writel(status, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + > + /* > + * Update the AUX buffer and cache the current buflet index, > + * as we need to know this and save the data when the trace > + * is ended out of the interrupt handler. End the trace > + * if the updating fails. > + */ > + if (hisi_ptt_update_aux(hisi_ptt, buf_idx, false)) > + hisi_ptt_trace_end(hisi_ptt); > + else > + hisi_ptt->trace_ctrl.buf_index = (buf_idx + 1) % HISI_PTT_TRACE_BUFLETS_CNT; > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t hisi_ptt_irq(int irq, void *context) > +{ > + struct hisi_ptt *hisi_ptt = context; > + u32 status; > + > + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + if (!(status & HISI_PTT_TRACE_INT_STAT_MASK)) > + return IRQ_NONE; > + > + return IRQ_WAKE_THREAD; > +} > + > +static void hisi_ptt_irq_free_vectors(void *pdev) > +{ > + pci_free_irq_vectors(pdev); > +} > + > +static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt) > +{ > + struct pci_dev *pdev = hisi_ptt->pdev; > + int ret; > + > + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); > + if (ret < 0) { > + pci_err(pdev, "failed to allocate irq vector, ret = %d.\n", ret); > + return ret; > + } > + > + ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_irq_free_vectors, pdev); > + if (ret < 0) > + return ret; > + > + ret = devm_request_threaded_irq(&pdev->dev, > + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), > + hisi_ptt_irq, hisi_ptt_isr, 0, > + "hisi-ptt", hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to request irq %d, ret = %d.\n", > + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret); > + return ret; > + } > + > + return 0; > +} > + > +static void hisi_ptt_update_filters(struct work_struct *work) > +{ > + struct delayed_work *delayed_work = to_delayed_work(work); > + struct hisi_ptt_filter_update_info info; > + struct hisi_ptt_filter_desc *filter; > + struct list_head *target_list; > + struct hisi_ptt *hisi_ptt; > + > + hisi_ptt = container_of(delayed_work, struct hisi_ptt, work); > + > + if (!mutex_trylock(&hisi_ptt->mutex)) { > + schedule_delayed_work(&hisi_ptt->work, HISI_PTT_WORK_DELAY_MS); > + return; > + } > + > + while (kfifo_get(&hisi_ptt->filter_update_kfifo, &info)) { > + target_list = info.is_port ? &hisi_ptt->port_filters : > + &hisi_ptt->req_filters; > + > + if (info.is_add) { > + filter = kzalloc(sizeof(*filter), GFP_KERNEL); > + if (!filter) > + continue; > + > + filter->pdev = info.pdev; > + filter->val = info.val; > + > + list_add_tail(&filter->list, target_list); > + } else { > + list_for_each_entry(filter, target_list, list) > + if (filter->val == info.val) { > + list_del(&filter->list); > + kfree(filter); > + break; > + } > + } > + > + /* Update the available port mask */ > + if (!info.is_port) > + continue; > + > + if (info.is_add) > + hisi_ptt->port_mask |= info.val; > + else > + hisi_ptt->port_mask &= ~info.val; > + } > + > + mutex_unlock(&hisi_ptt->mutex); > +} > + > +static void hisi_ptt_update_fifo_in(struct hisi_ptt *hisi_ptt, > + struct hisi_ptt_filter_update_info *info) > +{ > + struct pci_dev *root_port = pcie_find_root_port(info->pdev); > + > + if (!root_port) > + return; > + > + info->port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn); > + if (info->port_devid < hisi_ptt->lower || > + info->port_devid > hisi_ptt->upper) > + return; > + > + info->is_port = pci_pcie_type(info->pdev) == PCI_EXP_TYPE_ROOT_PORT; > + info->val = hisi_ptt_get_filter_val(info->pdev); > + > + if (kfifo_in_spinlocked(&hisi_ptt->filter_update_kfifo, info, 1, > + &hisi_ptt->filter_update_lock)) > + schedule_delayed_work(&hisi_ptt->work, 0); > + else > + pci_warn(hisi_ptt->pdev, > + "filter update fifo overflow for target %s\n", > + pci_name(info->pdev)); > +} > + > +/* > + * A PCI bus notifier is used here for dynamically updating the filter > + * list. > + */ > +static int hisi_ptt_notifier_call(struct notifier_block *nb, unsigned long action, > + void *data) > +{ > + struct hisi_ptt *hisi_ptt = container_of(nb, struct hisi_ptt, hisi_ptt_nb); > + struct hisi_ptt_filter_update_info info; > + struct device *dev = data; > + struct pci_dev *pdev = to_pci_dev(dev); > + > + info.pdev = pdev; > + > + switch (action) { > + case BUS_NOTIFY_ADD_DEVICE: > + info.is_add = true; > + break; > + case BUS_NOTIFY_DEL_DEVICE: > + info.is_add = false; > + break; > + default: > + return 0; > + } > + > + hisi_ptt_update_fifo_in(hisi_ptt, &info); > + > + return 0; > +} > + > +static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) > +{ > + struct hisi_ptt_filter_update_info info = { > + .pdev = pdev, > + .is_add = true, > + }; > + struct hisi_ptt *hisi_ptt = data; > + > + hisi_ptt_update_fifo_in(hisi_ptt, &info); > + > + return 0; > +} > + > +static void hisi_ptt_release_filters(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_filter_desc *filter, *tfilter; > + > + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->req_filters, list) { > + list_del(&filter->list); > + kfree(filter); > + } > + > + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->port_filters, list) { > + list_del(&filter->list); > + kfree(filter); > + } > +} > + > +static void hisi_ptt_init_ctrls(struct hisi_ptt *hisi_ptt) > +{ > + struct pci_dev *pdev = hisi_ptt->pdev; > + struct pci_bus *bus; > + u32 reg; > + > + INIT_DELAYED_WORK(&hisi_ptt->work, hisi_ptt_update_filters); > + spin_lock_init(&hisi_ptt->filter_update_lock); > + INIT_KFIFO(hisi_ptt->filter_update_kfifo); > + INIT_LIST_HEAD(&hisi_ptt->port_filters); > + INIT_LIST_HEAD(&hisi_ptt->req_filters); > + > + /* > + * The device range register provides the information about the > + * root ports which the RCiEP can control and trace. The RCiEP > + * and the root ports it support are on the same PCIe core, with > + * same domain number but maybe different bus number. The device > + * range register will tell us which root ports we can support, > + * Bit[31:16] indicates the upper BDF numbers of the root port, > + * while Bit[15:0] indicates the lower. > + */ > + reg = readl(hisi_ptt->iobase + HISI_PTT_DEVICE_RANGE); > + hisi_ptt->upper = reg >> 16; > + hisi_ptt->lower = reg & 0xffff; > + hisi_ptt->busnr = PCI_BUS_NUM(hisi_ptt->upper); > + > + reg = readl(hisi_ptt->iobase + HISI_PTT_LOCATION); > + hisi_ptt->core_id = FIELD_GET(HISI_PTT_CORE_ID, reg); > + hisi_ptt->sicl_id = FIELD_GET(HISI_PTT_SICL_ID, reg); > + > + bus = pci_find_bus(pci_domain_nr(pdev->bus), hisi_ptt->busnr); > + if (bus) > + pci_walk_bus(bus, hisi_ptt_init_filters, hisi_ptt); What happens if bus is NULL? Should this be reported to the caller and cause hisi_ptt_probe() to fail? Please add a comment that describes the scenario. > + > + /* Initialize trace controls */ > + INIT_LIST_HEAD(&hisi_ptt->trace_ctrl.trace_buf); > + hisi_ptt->trace_ctrl.buflet_size = HISI_PTT_TRACE_BUFLET_SIZE; > + hisi_ptt->trace_ctrl.default_cpu = cpumask_first(cpumask_of_node(dev_to_node(&pdev->dev))); > +} > + > +#define HISI_PTT_PMU_FILTER_IS_PORT BIT(19) > +#define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0) > +#define HISI_PTT_PMU_DIRECTION_MASK GENMASK(23, 20) > +#define HISI_PTT_PMU_TYPE_MASK GENMASK(31, 24) > +#define HISI_PTT_PMU_FORMAT_MASK GENMASK(35, 32) > + > +static ssize_t available_filters_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev)); > + struct hisi_ptt_filter_desc *filter; > + int pos = 0; > + > + if (list_empty(&hisi_ptt->port_filters)) > + return sysfs_emit(buf, "#### No available filter ####\n"); > + > + mutex_lock(&hisi_ptt->mutex); > + pos += sysfs_emit_at(buf, pos, "#### Root Ports ####\n"); > + list_for_each_entry(filter, &hisi_ptt->port_filters, list) > + pos += sysfs_emit_at(buf, pos, "%s 0x%05lx\n", > + pci_name(filter->pdev), > + hisi_ptt_get_filter_val(filter->pdev) | > + HISI_PTT_PMU_FILTER_IS_PORT); > + > + pos += sysfs_emit_at(buf, pos, "#### Requesters ####\n"); > + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > + pos += sysfs_emit_at(buf, pos, "%s 0x%05x\n", > + pci_name(filter->pdev), > + hisi_ptt_get_filter_val(filter->pdev)); > + > + mutex_unlock(&hisi_ptt->mutex); > + return pos; > +} > +static DEVICE_ATTR_ADMIN_RO(available_filters); > + > +PMU_FORMAT_ATTR(filter, "config:0-19"); > +PMU_FORMAT_ATTR(direction, "config:20-23"); > +PMU_FORMAT_ATTR(type, "config:24-31"); > +PMU_FORMAT_ATTR(format, "config:32-35"); > + > +static struct attribute *hisi_ptt_pmu_format_attrs[] = { > + &format_attr_filter.attr, > + &format_attr_direction.attr, > + &format_attr_type.attr, > + &format_attr_format.attr, > + NULL > +}; > + > +static struct attribute_group hisi_ptt_pmu_format_group = { > + .name = "format", > + .attrs = hisi_ptt_pmu_format_attrs, > +}; > + > +static struct attribute *hisi_ptt_pmu_filter_attrs[] = { > + &dev_attr_available_filters.attr, > + NULL > +}; > + > +static struct attribute_group hisi_ptt_pmu_filter_group = { > + .attrs = hisi_ptt_pmu_filter_attrs, > +}; > + > +static const struct attribute_group *hisi_ptt_pmu_groups[] = { > + &hisi_ptt_pmu_format_group, > + &hisi_ptt_pmu_filter_group, > + NULL > +}; > + > +/* > + * The supported value of the direction parameter. See hisi_ptt.rst > + * documentation for more details. > + */ > +static u32 hisi_ptt_trace_available_direction[] = { > + 0, > + 1, > + 2, > + 3, > +}; > + > +/* Different types can be set simultaneously */ > +static u32 hisi_ptt_trace_available_type[] = { > + 1, /* posted_request */ > + 2, /* non-posted_request */ > + 4, /* completion */ > +}; > + > +static u32 hisi_ptt_trace_availble_format[] = { > + 0, /* 4DW */ > + 1, /* 8DW */ > +}; > + > +/* > + * Check whether the config is valid or not. Some configs are multi-selectable > + * and can be set simultaneously, while some are single selectable (onehot). > + * Use this function to check the non-onehot configs while > + * hisi_ptt_trace_valid_config_onehot() for the onehot ones. > + */ > +static int hisi_ptt_trace_valid_config(u32 val, u32 *available_list, u32 list_size) > +{ > + int i; > + > + /* > + * The non-onehot configs cannot be 0. Walk the available > + * list and clear the valid bits of the config. If there > + * is any resident bit after the walk then the config is > + * invalid. > + */ > + for (i = 0; i < list_size; i++) > + val &= ~available_list[i]; > + > + return val ? -EINVAL : 0; > +} > + > +static int hisi_ptt_trace_valid_config_onehot(u32 val, u32 *available_list, u32 list_size) > +{ > + int i, ret = -EINVAL; > + > + for (i = 0; i < list_size; i++) > + if (val == available_list[i]) { > + ret = 0; > + break; > + } > + > + return ret; > +} > + > +static int hisi_ptt_trace_init_filter(struct hisi_ptt *hisi_ptt, u64 config) > +{ > + unsigned long val, port_mask = hisi_ptt->port_mask; > + struct hisi_ptt_filter_desc *filter; > + int ret = -EINVAL; > + > + hisi_ptt->trace_ctrl.is_port = FIELD_GET(HISI_PTT_PMU_FILTER_IS_PORT, config); > + val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, config); > + > + /* > + * Port filters are defined as bit mask. For port filters, check > + * the bits in the @val are within the range of hisi_ptt->port_mask > + * and whether it's empty or not, otherwise user has specified > + * some unsupported root ports. > + * > + * For Requester ID filters, walk the available filter list to see > + * whether we have one matched. > + */ > + if (hisi_ptt->trace_ctrl.is_port && > + bitmap_subset(&val, &port_mask, BITS_PER_LONG)) { > + ret = 0; > + } else { > + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > + if (filter->val == val) { > + ret = 0; > + break; > + } > + } > + > + if (ret) > + return ret; > + > + hisi_ptt->trace_ctrl.filter = val; > + return 0; > +} > + > +static int hisi_ptt_pmu_event_init(struct perf_event *event) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + int ret; > + u32 val; > + > + if (event->attr.type != hisi_ptt->hisi_ptt_pmu.type) > + return -ENOENT; > + > + mutex_lock(&hisi_ptt->mutex); > + > + ret = hisi_ptt_trace_init_filter(hisi_ptt, event->attr.config); > + if (ret < 0) > + goto out; > + > + val = FIELD_GET(HISI_PTT_PMU_DIRECTION_MASK, event->attr.config); > + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_available_direction, > + ARRAY_SIZE(hisi_ptt_trace_available_direction)); > + if (ret < 0) > + goto out; > + ctrl->direction = val; > + > + val = FIELD_GET(HISI_PTT_PMU_TYPE_MASK, event->attr.config); > + > + ret = hisi_ptt_trace_valid_config(val, hisi_ptt_trace_available_type, > + ARRAY_SIZE(hisi_ptt_trace_available_type)); > + if (ret < 0) > + goto out; > + ctrl->type = val; > + > + val = FIELD_GET(HISI_PTT_PMU_FORMAT_MASK, event->attr.config); > + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_availble_format, > + ARRAY_SIZE(hisi_ptt_trace_availble_format)); > + if (ret < 0) > + goto out; > + ctrl->format = val; > + > +out: > + mutex_unlock(&hisi_ptt->mutex); > + return ret; > +} > + > +static void *hisi_ptt_pmu_setup_aux(struct perf_event *event, void **pages, > + int nr_pages, bool overwrite) > +{ > + struct hisi_ptt_pmu_buf *buf; > + struct page **pagelist; > + int i; > + > + if (overwrite) { > + dev_warn(event->pmu->dev, "Overwrite mode is not supported\n"); > + return NULL; > + } > + > + /* If the pages size less than buflets, we cannot start trace */ > + if (nr_pages < HISI_PTT_TRACE_BUFFER_SIZE / PAGE_SIZE) > + return NULL; > + > + buf = kzalloc(sizeof(*buf), GFP_KERNEL); > + if (!buf) > + return NULL; > + > + pagelist = kcalloc(nr_pages, sizeof(*pagelist), GFP_KERNEL); > + if (!pagelist) { > + kfree(buf); > + return NULL; > + } > + > + for (i = 0; i < nr_pages; i++) > + pagelist[i] = virt_to_page(pages[i]); > + > + buf->base = vmap(pagelist, nr_pages, VM_MAP, PAGE_KERNEL); > + if (!buf->base) { > + kfree(pagelist); > + kfree(buf); > + return NULL; > + } > + > + buf->nr_pages = nr_pages; > + buf->length = nr_pages * PAGE_SIZE; > + buf->pos = 0; > + > + kfree(pagelist); > + return buf; > +} > + > +static void hisi_ptt_pmu_free_aux(void *aux) > +{ > + struct hisi_ptt_pmu_buf *buf = aux; > + > + vunmap(buf->base); > + kfree(buf); > +} > + > +static void hisi_ptt_pmu_start(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle; > + struct hw_perf_event *hwc = &event->hw; > + struct hisi_ptt_pmu_buf *buf; > + int cpu = event->cpu; > + int ret; > + > + hwc->state = 0; > + mutex_lock(&hisi_ptt->mutex); > + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) { > + pci_dbg(hisi_ptt->pdev, "trace has already started\n"); > + goto stop; > + } > + > + if (cpu == -1) > + cpu = hisi_ptt->trace_ctrl.default_cpu; > + > + /* > + * Handle the interrupt on the same cpu which starts the trace to avoid > + * context mismatch. Otherwise we'll trigger the WARN from the perf > + * core in event_function_local(). > + */ > + WARN_ON(irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ), > + cpumask_of(cpu))); > + > + ret = hisi_ptt_alloc_trace_buf(hisi_ptt); > + if (ret) { > + pci_dbg(hisi_ptt->pdev, "alloc trace buf failed, ret = %d\n", ret); > + goto stop; > + } > + > + buf = perf_aux_output_begin(handle, event); > + if (!buf) { > + pci_dbg(hisi_ptt->pdev, "aux output begin failed\n"); > + goto stop; > + } > + > + buf->pos = handle->head % buf->length; > + > + ret = hisi_ptt_trace_start(hisi_ptt); > + if (ret) { > + pci_dbg(hisi_ptt->pdev, "trace start failed, ret = %d\n", ret); > + perf_aux_output_end(handle, 0); > + goto stop; > + } > + > + mutex_unlock(&hisi_ptt->mutex); > + return; > +stop: > + event->hw.state |= PERF_HES_STOPPED; > + mutex_unlock(&hisi_ptt->mutex); > +} > + > +static void hisi_ptt_pmu_stop(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hw_perf_event *hwc = &event->hw; > + > + if (hwc->state & PERF_HES_STOPPED) > + return; > + > + mutex_lock(&hisi_ptt->mutex); > + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) { > + hisi_ptt_trace_end(hisi_ptt); > + WARN(hisi_ptt_wait_trace_hw_idle(hisi_ptt), "Device is still busy"); > + hisi_ptt_update_aux(hisi_ptt, hisi_ptt->trace_ctrl.buf_index, true); > + } > + mutex_unlock(&hisi_ptt->mutex); > + > + hwc->state |= PERF_HES_STOPPED; > + perf_event_update_userpage(event); > + hwc->state |= PERF_HES_UPTODATE; > +} > + > +static int hisi_ptt_pmu_add(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hw_perf_event *hwc = &event->hw; > + int cpu = event->cpu; > + > + if (cpu == -1 && smp_processor_id() != hisi_ptt->trace_ctrl.default_cpu) > + return 0; > + > + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; > + > + if (flags & PERF_EF_START) { > + hisi_ptt_pmu_start(event, PERF_EF_RELOAD); > + if (hwc->state & PERF_HES_STOPPED) > + return -EINVAL; > + } > + > + return 0; > +} > + > +static void hisi_ptt_pmu_del(struct perf_event *event, int flags) > +{ > + hisi_ptt_pmu_stop(event, PERF_EF_UPDATE); > +} > + > +static void hisi_ptt_unregister_pmu(void *priv) > +{ > + perf_pmu_unregister(priv); > +} > + > +static int hisi_ptt_register_pmu(struct hisi_ptt *hisi_ptt) > +{ > + char *pmu_name; > + int ret; > + > + hisi_ptt->hisi_ptt_pmu = (struct pmu) { > + .module = THIS_MODULE, > + .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, > + .task_ctx_nr = perf_sw_context, > + .attr_groups = hisi_ptt_pmu_groups, > + .event_init = hisi_ptt_pmu_event_init, > + .setup_aux = hisi_ptt_pmu_setup_aux, > + .free_aux = hisi_ptt_pmu_free_aux, > + .start = hisi_ptt_pmu_start, > + .stop = hisi_ptt_pmu_stop, > + .add = hisi_ptt_pmu_add, > + .del = hisi_ptt_pmu_del, > + }; > + > + pmu_name = devm_kasprintf(&hisi_ptt->pdev->dev, GFP_KERNEL, "hisi_ptt%u_%u", > + hisi_ptt->sicl_id, hisi_ptt->core_id); > + if (!pmu_name) > + return -ENOMEM; > + > + ret = perf_pmu_register(&hisi_ptt->hisi_ptt_pmu, pmu_name, -1); > + if (ret) > + return ret; > + > + return devm_add_action_or_reset(&hisi_ptt->pdev->dev, > + hisi_ptt_unregister_pmu, > + &hisi_ptt->hisi_ptt_pmu); > +} > + > +/* > + * Get RMR address if provided by the firmware. > + * Return 0 if the IOMMU doesn't present or the policy of the > + * IOMMU domain is passthrough or we get a usable RMR region. > + * Otherwise a negative value is returned. > + */ > +static int hisi_ptt_get_rmr(struct hisi_ptt *hisi_ptt) > +{ > + struct pci_dev *pdev = hisi_ptt->pdev; > + struct iommu_domain *iommu_domain; > + struct iommu_resv_region *region; > + LIST_HEAD(list); > + > + /* > + * Use direct DMA if IOMMU does not present or the policy of the > + * IOMMU domain is passthrough. > + */ > + iommu_domain = iommu_get_domain_for_dev(&pdev->dev); > + if (!iommu_domain || iommu_domain->type == IOMMU_DOMAIN_IDENTITY) > + return 0; > + > + iommu_get_resv_regions(&pdev->dev, &list); > + list_for_each_entry(region, &list, list) > + if (region->type == IOMMU_RESV_DIRECT && > + region->length >= HISI_PTT_TRACE_BUFFER_SIZE) { > + hisi_ptt->trace_ctrl.has_rmr = true; > + hisi_ptt->trace_ctrl.rmr_addr = region->start; > + hisi_ptt->trace_ctrl.rmr_length = region->length; > + break; > + } > + > + iommu_put_resv_regions(&pdev->dev, &list); > + return hisi_ptt->trace_ctrl.has_rmr ? 0 : -ENOMEM; > +} > + > +static int hisi_ptt_probe(struct pci_dev *pdev, > + const struct pci_device_id *id) > +{ > + struct hisi_ptt *hisi_ptt; > + int ret; > + > + hisi_ptt = devm_kzalloc(&pdev->dev, sizeof(*hisi_ptt), GFP_KERNEL); > + if (!hisi_ptt) > + return -ENOMEM; > + > + mutex_init(&hisi_ptt->mutex); > + hisi_ptt->pdev = pdev; > + > + /* > + * Lifetime of pci_dev is longer than hisi_ptt, > + * so directly reference to the pci name string. > + */ > + hisi_ptt->name = pci_name(hisi_ptt->pdev); > + pci_set_drvdata(pdev, hisi_ptt); > + > + ret = pcim_enable_device(pdev); > + if (ret) { > + pci_err(pdev, "failed to enable device, ret = %d.\n", ret); > + return ret; > + } > + > + ret = pcim_iomap_regions(pdev, BIT(2), hisi_ptt->name); > + if (ret) { > + pci_err(pdev, "failed to remap io memory, ret = %d.\n", ret); > + return ret; > + } > + > + hisi_ptt->iobase = pcim_iomap_table(pdev)[2]; > + > + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); > + if (ret) { > + pci_err(pdev, "failed to set 64 bit dma mask, ret = %d.\n", ret); > + return ret; > + } > + pci_set_master(pdev); > + > + ret = hisi_ptt_register_irq(hisi_ptt); > + if (ret) > + return ret; > + > + hisi_ptt_init_ctrls(hisi_ptt); > + > + ret = hisi_ptt_register_pmu(hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to register pmu device, ret = %d", ret); > + return ret; > + } If this fails the pci_free_irq_vectors() is not called. I am out of time for today - I will continue tomorrow. Thanks, Mathieu > + > + ret = hisi_ptt_get_rmr(hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to get RMR region, ret = %d", ret); > + return ret; > + } > + > + /* Register the bus notifier for dynamically updating the filter list */ > + hisi_ptt->hisi_ptt_nb.notifier_call = hisi_ptt_notifier_call; > + ret = bus_register_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb); > + if (ret) > + pci_warn(pdev, "failed to register filter update notifier, ret = %d", ret); > + > + return 0; > +} > + > +void hisi_ptt_remove(struct pci_dev *pdev) > +{ > + struct hisi_ptt *hisi_ptt = pci_get_drvdata(pdev); > + > + bus_unregister_notifier(&pci_bus_type, &hisi_ptt->hisi_ptt_nb); > + > + /* Cancel any work that has been queued */ > + cancel_delayed_work_sync(&hisi_ptt->work); > + > + if (hisi_ptt->trace_ctrl.status == HISI_PTT_TRACE_STATUS_ON) > + hisi_ptt_trace_end(hisi_ptt); > + > + hisi_ptt_free_trace_buf(hisi_ptt); > + hisi_ptt_release_filters(hisi_ptt); > +} > + > +static const struct pci_device_id hisi_ptt_id_tbl[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa12e) }, > + { } > +}; > +MODULE_DEVICE_TABLE(pci, hisi_ptt_id_tbl); > + > +static struct pci_driver hisi_ptt_driver = { > + .name = "hisi_ptt", > + .id_table = hisi_ptt_id_tbl, > + .probe = hisi_ptt_probe, > + .remove = hisi_ptt_remove, > +}; > +module_pci_driver(hisi_ptt_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Yicong Yang <yangyicong(a)hisilicon.com>"); > +MODULE_DESCRIPTION("Driver for HiSilicon PCIe tune and trace device"); > -- > 2.33.0 >

2 years, 11 months

Re: [PATCH v2 1/6] iommu: Export iommu_{get,put}_resv_regions()

by Mathieu Poirier

On Tue, Nov 16, 2021 at 05:06:20PM +0800, Yicong Yang wrote: > Export iommu_{get,put}_resv_regions() to the modules so that the driver > can retrieve and use the reserved regions of the device. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > drivers/iommu/iommu.c | 2 ++ > include/linux/iommu.h | 4 ++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c > index dd7863e453a5..e96711eee965 100644 > --- a/drivers/iommu/iommu.c > +++ b/drivers/iommu/iommu.c > @@ -2792,6 +2792,7 @@ void iommu_get_resv_regions(struct device *dev, struct list_head *list) > if (ops && ops->get_resv_regions) > ops->get_resv_regions(dev, list); > } > +EXPORT_SYMBOL_GPL(iommu_get_resv_regions); > > void iommu_put_resv_regions(struct device *dev, struct list_head *list) > { > @@ -2800,6 +2801,7 @@ void iommu_put_resv_regions(struct device *dev, struct list_head *list) > if (ops && ops->put_resv_regions) > ops->put_resv_regions(dev, list); > } > +EXPORT_SYMBOL_GPL(iommu_put_resv_regions); > > /** > * generic_iommu_put_resv_regions - Reserved region driver helper > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index d2f3435e7d17..1b7b0f370e28 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -450,8 +450,8 @@ extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t io > extern void iommu_set_fault_handler(struct iommu_domain *domain, > iommu_fault_handler_t handler, void *token); > > -extern void iommu_get_resv_regions(struct device *dev, struct list_head *list); > -extern void iommu_put_resv_regions(struct device *dev, struct list_head *list); > +void iommu_get_resv_regions(struct device *dev, struct list_head *list); > +void iommu_put_resv_regions(struct device *dev, struct list_head *list); Acked-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > extern void generic_iommu_put_resv_regions(struct device *dev, > struct list_head *list); > extern void iommu_set_default_passthrough(bool cmd_line); > -- > 2.33.0 >

2 years, 11 months

[PATCH v1] perf cs-etm: Pass -1 as pid value for machine__set_current_tid()

by Leo Yan

Currently, cs-etm passes the tid value for both tid and pid parameters when calling machine__set_current_tid(), this can lead to confusion for thread handling. E.g. we arbitrarily pass the same value for pid and tid, perf tool will be misled to consider it is a main thread (see thread__main_thread()). On the other hand, Perf tool only can retrieve tid from Arm CoreSight context packet, and we have no chance to know pid (it maps to kernel's task_struct::tgid) from hardware tracing data. For this reason, this patch passes -1 as pid for function machine__set_current_tid(). Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/util/cs-etm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index f323adb1af85..eed1a5930072 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1118,7 +1118,7 @@ int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, if (cs_etm__get_cpu(trace_chan_id, &cpu) < 0) return err; - err = machine__set_current_tid(etm->machine, cpu, tid, tid); + err = machine__set_current_tid(etm->machine, cpu, -1, tid); if (err) return err; -- 2.25.1

2 years, 11 months

[PATCH] Documentation: coresight: Fix documentation issue

by Mike Leach

Fix the description of the directories and attributes used in cs_etm as used by perf. Drop the references to the 'configurations' sub-directory which had been removed in an earlier version of the patchset. Fixes: f71cd93d5ea4 ("Documentation: coresight: Add documentation for CoreSight config") Reported-by: German Gomex <german.gomez(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- .../trace/coresight/coresight-config.rst | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst index a4e3ef295240..6ed13398ca2c 100644 --- a/Documentation/trace/coresight/coresight-config.rst +++ b/Documentation/trace/coresight/coresight-config.rst @@ -211,19 +211,13 @@ also declared in the perf 'cs_etm' event infrastructure so that they can be selected when running trace under perf:: $ ls /sys/devices/cs_etm - configurations format perf_event_mux_interval_ms sinks type - events nr_addr_filters power + cpu0 cpu2 events nr_addr_filters power subsystem uevent + cpu1 cpu3 format perf_event_mux_interval_ms sinks type -Key directories here are 'configurations' - which lists the loaded -configurations, and 'events' - a generic perf directory which allows -selection on the perf command line.:: +The key directory here is 'events' - a generic perf directory which allows +selection on the perf command line. As with the sinks entries, this provides +a hash of the configuration name. - $ ls configurations/ - autofdo - $ cat configurations/autofdo - 0xa7c3dddd - -As with the sinks entries, this provides a hash of the configuration name. The entry in the 'events' directory uses perfs built in syntax generator to substitute the syntax for the name when evaluating the command:: -- 2.17.1

2 years, 11 months

Re: [PATCH 01/10] coresight: add support to enable more coresight paths

by Mathieu Poirier

On Mon, Nov 22, 2021 at 11:12:03PM +0800, Jinlong Mao wrote: > Hi Mathieu, > > Thanks for the comments. > > I double checked the code. Please see my comments below. > > > On 10/29/2021 2:06 AM, Mathieu Poirier wrote: > > On Thu, Oct 21, 2021 at 03:38:47PM +0800, Tao Zhang wrote: > > > Current coresight implementation only supports enabling source > > > ETMs or STM. This patch adds support to enable more kinds of > > > coresight source to sink paths. We build a path from source to > > > sink when any source is enabled and store it in a list. When the > > > source is disabled, we fetch the corresponding path from the list > > > and decrement the refcount on each device in the path. The device > > > is disabled if the refcount reaches zero. Don't store path to > > > coresight data structure of source to avoid unnecessary change to > > > ABI. > > > Since some targets may have coresight sources other than STM and > > > ETMs, we need to add this change to support these coresight > > > devices. > > > > > > Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> > > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > > > --- > > > drivers/hwtracing/coresight/coresight-core.c | 100 +++++++++++-------- > > > 1 file changed, 56 insertions(+), 44 deletions(-) > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > > > index 8a18c71df37a..1e621d61307a 100644 > > > --- a/drivers/hwtracing/coresight/coresight-core.c > > > +++ b/drivers/hwtracing/coresight/coresight-core.c > > > @@ -37,18 +37,16 @@ struct coresight_node { > > > }; > > > /* > > > - * When operating Coresight drivers from the sysFS interface, only a single > > > - * path can exist from a tracer (associated to a CPU) to a sink. > > > + * struct coresight_path - path from source to sink > > > + * @path: Address of path list. > > > + * @link: hook to the list. > > > */ > > > -static DEFINE_PER_CPU(struct list_head *, tracer_path); > > > +struct coresight_path { > > > + struct list_head *path; > > > + struct list_head link; > > > +}; > > For sources associated with a CPU, like ETMs, having a per-cpu way of storing > > paths is a definite advantage and should be kept that way. > > Hi Mathieu, > > Could you please share what is the advantage to handle the sources > associated with a CPU separatly ? > It is a question of efficiency. There is no point iterating through all the sources if we don't have to. > From the code, cpu id is only used to get the path of the ETM source. > > As there will be many tpdm sources, I think it will be easier to only > maintain one list for all the sources. > So many TPDM and many ETMs... That is definitely a reason to do better than a sequential search. > > > -/* > > > - * As of this writing only a single STM can be found in CS topologies. Since > > > - * there is no way to know if we'll ever see more and what kind of > > > - * configuration they will enact, for the time being only define a single path > > > - * for STM. > > > - */ > > > -static struct list_head *stm_path; > > > +static LIST_HEAD(cs_active_paths); > > Then there are sources that aren't associated with a CPU like STMs and TPDMs. > > Perhaps using an IDR or the hash of the device name as a key to a hashing > > vector would be better than doing a sequential search, especially as the > > list of devices is bound to increase over time. > > Agree with you. I will try to use IDR or the hash of the device name as a > key to a hashing vector. > If an IDR (or some other kind of mechanism) is used then we can use that to store paths associated with ETMs as well. That way everything works the same way and access time is constant for any kind of source. > > > > > /* > > > * When losing synchronisation a new barrier packet needs to be inserted at the > > > @@ -354,6 +352,7 @@ static void coresight_disable_sink(struct coresight_device *csdev) > > > if (ret) > > > return; > > > coresight_control_assoc_ectdev(csdev, false); > > > + csdev->activated = false; > > I don't see why this is needed and without proper documentation there is no way > > for me to guess the logic behind the change. The ->activated flag should be > > manipulated from the command line interface only. > > When source is disabled, but sink is still actived. It will be confused for > end users. > That is how it has been working for years now. It was done this way to give as much flexibility to users and keep kernel intelligence to a minimum. > > > > > csdev->enable = false; > > > } > > > @@ -590,6 +589,20 @@ int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data) > > > goto out; > > > } > > > +static struct coresight_device *coresight_get_source(struct list_head *path) > > > +{ > > > + struct coresight_device *csdev; > > > + > > > + if (!path) > > > + return NULL; > > > + > > > + csdev = list_first_entry(path, struct coresight_node, link)->csdev; > > > + if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) > > > + return NULL; > > > + > > > + return csdev; > > > +} > > > + > > > struct coresight_device *coresight_get_sink(struct list_head *path) > > > { > > > struct coresight_device *csdev; > > > @@ -1086,9 +1099,23 @@ static int coresight_validate_source(struct coresight_device *csdev, > > > return 0; > > > } > > > +static int coresight_store_path(struct list_head *path) > > > +{ > > > + struct coresight_path *node; > > > + > > > + node = kzalloc(sizeof(struct coresight_path), GFP_KERNEL); > > > + if (!node) > > > + return -ENOMEM; > > > + > > > + node->path = path; > > > + list_add(&node->link, &cs_active_paths); > > > + > > > + return 0; > > > +} > > > + > > > int coresight_enable(struct coresight_device *csdev) > > > { > > > - int cpu, ret = 0; > > > + int ret = 0; > > > struct coresight_device *sink; > > > struct list_head *path; > > > enum coresight_dev_subtype_source subtype; > > > @@ -1133,25 +1160,9 @@ int coresight_enable(struct coresight_device *csdev) > > > if (ret) > > > goto err_source; > > > - switch (subtype) { > > > - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: > > > - /* > > > - * When working from sysFS it is important to keep track > > > - * of the paths that were created so that they can be > > > - * undone in 'coresight_disable()'. Since there can only > > > - * be a single session per tracer (when working from sysFS) > > > - * a per-cpu variable will do just fine. > > > - */ > > > - cpu = source_ops(csdev)->cpu_id(csdev); > > > - per_cpu(tracer_path, cpu) = path; > > > - break; > > > - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: > > > - stm_path = path; > > > - break; > > > - default: > > > - /* We can't be here */ > > > - break; > > > - } > > > + ret = coresight_store_path(path); > > > + if (ret) > > > + goto err_source; > > > out: > > > mutex_unlock(&coresight_mutex); > > > @@ -1168,8 +1179,11 @@ EXPORT_SYMBOL_GPL(coresight_enable); > > > void coresight_disable(struct coresight_device *csdev) > > > { > > > - int cpu, ret; > > > + int ret; > > > struct list_head *path = NULL; > > > + struct coresight_path *cspath = NULL; > > > + struct coresight_path *cspath_next = NULL; > > > + struct coresight_device *src_csdev = NULL; > > > mutex_lock(&coresight_mutex); > > > @@ -1180,20 +1194,18 @@ void coresight_disable(struct coresight_device *csdev) > > > if (!csdev->enable || !coresight_disable_source(csdev)) > > > goto out; > > > - switch (csdev->subtype.source_subtype) { > > > - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: > > > - cpu = source_ops(csdev)->cpu_id(csdev); > > > - path = per_cpu(tracer_path, cpu); > > > - per_cpu(tracer_path, cpu) = NULL; > > > - break; > > > - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: > > > - path = stm_path; > > > - stm_path = NULL; > > > - break; > > > - default: > > > - /* We can't be here */ > > > - break; > > > + list_for_each_entry_safe(cspath, cspath_next, &cs_active_paths, link) { > > > + src_csdev = coresight_get_source(cspath->path); > > > + if (!src_csdev) > > > + continue; > > > + if (src_csdev == csdev) { > > > + path = cspath->path; > > > + list_del(&cspath->link); > > > + kfree(cspath); > > See my comment above - I agree that sources _not_ associated with a CPU should > > be handled differently. CPU bound sources should be kept untouched. > > > > That is all the time I had for today, I will continue tomorrow. > > > > Thanks, > > Mathieu > > > > > + } > > > } > > > + if (path == NULL) > > > + goto out; > > > coresight_disable_path(path); > > > coresight_release_path(path); > > > -- > > > 2.17.1 > > >

2 years, 11 months

[PATCH v2] drivers/coresight: ultrasoc: Add System Memory Buffer driver

by Qi Liu

This patch adds driver for Ultrasoc SMB(System Memory Buffer) device. SMB provides a way to buffer messages from ETM, and store these CPU instructions in system memory. SMB is developed by Ultrasoc technology, which is acquired by Siemens, and we still use "Ultrasoc" to name driver. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> Tested-by: JunHao He <hejunhao2(a)hisilicon.com> --- Change since RFC: - Move ultrasoc driver to drivers/hwtracing/coresight. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Change since v1: - Drop the document of Ultrasoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html drivers/hwtracing/coresight/Kconfig | 3 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/ultrasoc/Kconfig | 12 + drivers/hwtracing/coresight/ultrasoc/Makefile | 6 + .../coresight/ultrasoc/ultrasoc-smb.c | 610 ++++++++++++++++++ .../coresight/ultrasoc/ultrasoc-smb.h | 116 ++++ 6 files changed, 749 insertions(+) create mode 100644 drivers/hwtracing/coresight/ultrasoc/Kconfig create mode 100644 drivers/hwtracing/coresight/ultrasoc/Makefile create mode 100644 drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 514a9b8086e3..603430664729 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,7 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +source "drivers/hwtracing/coresight/ultrasoc/Kconfig" + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..50491d57c500 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -27,3 +27,5 @@ obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o + +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc/ diff --git a/drivers/hwtracing/coresight/ultrasoc/Kconfig b/drivers/hwtracing/coresight/ultrasoc/Kconfig new file mode 100644 index 000000000000..c18c25bf9df3 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: MIT +# +# ultrasoc configuration +# +config ULTRASOC_SMB + tristate "Ultrasoc system memory buffer drivers" + depends on ARM64 && CORESIGHT + help + This enables support for the Ultrasoc system memory buffer + driver that is responsible for receiving the trace data from + Coresight ETM devices and storing them to a system buffer + respectively. diff --git a/drivers/hwtracing/coresight/ultrasoc/Makefile b/drivers/hwtracing/coresight/ultrasoc/Makefile new file mode 100644 index 000000000000..8469be50fc6a --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for ultrasoc drivers. +# + +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.c new file mode 100644 index 000000000000..f8a4ae705293 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.c @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#include <linux/acpi.h> +#include <linux/circ_buf.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include "ultrasoc-smb.h" + +DEFINE_CORESIGHT_DEVLIST(sink_devs, "sink_smb"); + +static bool smb_buffer_is_empty(struct smb_drv_data *drvdata) +{ + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS); + + return buf_status & BIT(0) ? false : true; +} + +static bool smb_buffer_cmp_pointer(struct smb_drv_data *drvdata) +{ + u32 wr_offset, rd_offset; + + wr_offset = readl(drvdata->base + SMB_LB_WR_ADDR); + rd_offset = readl(drvdata->base + SMB_LB_RD_ADDR); + return wr_offset == rd_offset; +} + +static void smb_reset_buffer_status(struct smb_drv_data *drvdata) +{ + writel(0xf, drvdata->base + SMB_LB_INT_STS); +} + +/* Purge data remaining in hardware path to SMB. */ +static void smb_purge_data(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_LB_PURGE); +} + +static void smb_update_data_size(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 write_offset; + + smb_purge_data(drvdata); + if (smb_buffer_cmp_pointer(drvdata)) { + if (smb_buffer_is_empty(drvdata)) + sdb->data_size = 0; + else + sdb->data_size = sdb->buf_size; + return; + } + + write_offset = readl(drvdata->base + SMB_LB_WR_ADDR) - sdb->start_addr; + sdb->data_size = CIRC_CNT(write_offset, sdb->rd_offset, sdb->buf_size); +} + +static int smb_open(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + + if (local_cmpxchg(&drvdata->reading, 0, 1)) + return -EBUSY; + + return 0; +} + +static ssize_t smb_read(struct file *file, char __user *data, size_t len, loff_t *ppos) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct device *dev = &drvdata->csdev->dev; + unsigned long flags; + int to_copy = 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (!sdb->data_size) { + smb_update_data_size(drvdata); + if (!sdb->data_size) + goto out; + } + + if (atomic_read(drvdata->csdev->refcnt)) { + to_copy = -EBUSY; + goto out; + } + + to_copy = min(sdb->data_size, len); + + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + + if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, to_copy)) { + dev_dbg(dev, "Failed to copy data to user.\n"); + to_copy = -EFAULT; + goto out; + } + + *ppos += to_copy; + sdb->data_size -= to_copy; + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + dev_dbg(dev, "%d bytes copied.\n", to_copy); +out: + if (!sdb->data_size) + smb_reset_buffer_status(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return to_copy; +} + +static int smb_release(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + local_set(&drvdata->reading, 0); + return 0; +} + +static const struct file_operations smb_fops = { + .owner = THIS_MODULE, + .open = smb_open, + .read = smb_read, + .release = smb_release, + .llseek = no_llseek, +}; + +smb_simple_func(struct smb_drv_data, read_pos, SMB_LB_RD_ADDR); +smb_simple_func(struct smb_drv_data, write_pos, SMB_LB_WR_ADDR); +smb_simple_func(struct smb_drv_data, buf_status, SMB_LB_INT_STS); + +static ssize_t buf_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); +} +static DEVICE_ATTR_RO(buf_size); + +static struct attribute *smb_sink_attrs[] = { + &dev_attr_read_pos.attr, + &dev_attr_write_pos.attr, + &dev_attr_buf_status.attr, + &dev_attr_buf_size.attr, + NULL, +}; + +static const struct attribute_group smb_sink_group = { + .attrs = smb_sink_attrs, + .name = "status", +}; + +static const struct attribute_group *smb_sink_groups[] = { + &smb_sink_group, + NULL, +}; + +static int smb_set_perf_buffer(struct perf_output_handle *handle) +{ + struct cs_buffers *buf = etm_perf_sink_config(handle); + u32 head; + + if (!buf) + return -EINVAL; + + /* Wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* Find the page to write to and offset within that page */ + buf->cur = head / PAGE_SIZE; + buf->offset = head % PAGE_SIZE; + + local_set(&buf->data_size, 0); + + return 0; +} + +static void smb_enable_hw(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_GLOBAL_EN); +} + +static void smb_disable_hw(struct smb_drv_data *drvdata) +{ + writel(0x0, drvdata->base + SMB_GLOBAL_EN); +} + +static int smb_enable_sysfs(struct smb_drv_data *drvdata) +{ + if (drvdata->mode == CS_MODE_PERF) + return -EBUSY; + + if (drvdata->mode == CS_MODE_SYSFS) + return 0; + + smb_enable_hw(drvdata); + drvdata->mode = CS_MODE_SYSFS; + return 0; +} + +static int smb_enable_perf(struct smb_drv_data *drvdata, void *data) +{ + struct device *dev = &drvdata->csdev->dev; + struct perf_output_handle *handle = data; + pid_t pid; + + if (drvdata->mode == CS_MODE_SYSFS) { + dev_err(dev, "Device is already in used by sysfs.\n"); + return -EBUSY; + } + + /* Get a handle on the pid of the target process*/ + pid = task_pid_nr(handle->event->owner); + if (drvdata->pid != -1 && drvdata->pid != pid) { + dev_err(dev, "Device is already in used by other session.\n"); + return -EBUSY; + } + /* The sink is already enabled by this session. */ + if (drvdata->pid == pid) + return 0; + + if (smb_set_perf_buffer(handle)) + return -EINVAL; + + smb_enable_hw(drvdata); + drvdata->pid = pid; + drvdata->mode = CS_MODE_PERF; + + return 0; +} + +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int ret = -EINVAL; + + /* Do nothing if trace data is reading by other interface now. */ + if (local_read(&drvdata->reading)) + return -EBUSY; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (mode == CS_MODE_SYSFS) + ret = smb_enable_sysfs(drvdata); + + if (mode == CS_MODE_PERF) + ret = smb_enable_perf(drvdata, data); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (ret) + return ret; + + atomic_inc(csdev->refcnt); + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled.\n"); + + return 0; +} + +static int smb_disable(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + smb_disable_hw(drvdata); + + /* + * Data remaining in hardware path will be sent to SMB after purge, so needs to + * synchronize the read pointer to write pointer in perf mode. + */ + smb_purge_data(drvdata); + if (drvdata->mode == CS_MODE_PERF) + writel(readl(drvdata->base + SMB_LB_WR_ADDR), + drvdata->base + SMB_LB_RD_ADDR); + + /* Dissociate from the target process. */ + drvdata->pid = -1; + drvdata->mode = CS_MODE_DISABLED; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled.\n"); + return 0; +} + +static void *smb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) +{ + struct cs_buffers *buf; + int node; + + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + buf->data_pages = pages; + + return buf; +} + +static void smb_free_buffer(void *config) +{ + struct cs_buffers *buf = config; + + kfree(buf); +} + +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, + struct cs_buffers *buf, unsigned long data_size) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + char **dst_pages = (char **)buf->data_pages; + unsigned long buf_offset = buf->offset; + unsigned int cur = buf->cur; + unsigned long to_copy; + + while (data_size) { + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + PAGE_SIZE - buf_offset > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + else + to_copy = min(data_size, PAGE_SIZE - buf_offset); + + memcpy_fromio(dst_pages[cur] + buf_offset, sdb->buf_base + sdb->rd_offset, to_copy); + + buf_offset += to_copy; + if (buf_offset >= PAGE_SIZE) { + buf_offset = 0; + cur++; + cur %= buf->nr_pages; + } + data_size -= to_copy; + /* ensure memcpy finished before update the read pointer */ + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + } + + sdb->data_size = 0; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + smb_reset_buffer_status(drvdata); +} + +static unsigned long smb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct cs_buffers *buf = sink_config; + unsigned long data_size = 0; + unsigned long flags; + bool lost = false; + + if (!buf) + return 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink. */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + + smb_update_data_size(drvdata); + data_size = sdb->data_size; + if (data_size > handle->size) { + sdb->rd_offset += data_size - handle->size; + sdb->rd_offset %= sdb->buf_size; + data_size = handle->size; + lost = true; + } + + smb_sync_perf_buffer(drvdata, buf, data_size); + if (!buf->snapshot && lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return data_size; +} + +static const struct coresight_ops_sink smb_cs_ops = { + .enable = smb_enable, + .disable = smb_disable, + .alloc_buffer = smb_alloc_buffer, + .free_buffer = smb_free_buffer, + .update_buffer = smb_update_buffer, +}; + +static const struct coresight_ops cs_ops = { + .sink_ops = &smb_cs_ops, +}; + +static int smb_init_data_buffer(struct platform_device *pdev, struct smb_data_buffer *sdb) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "SMB device without data buffer.\n"); + return -EINVAL; + } + + sdb->start_addr = res->start & SMB_BASE_LOW_MASK; + sdb->buf_size = resource_size(res); + if (sdb->buf_size == 0) + return -EINVAL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + sdb->buf_base = base; + + return 0; +} + +static void smb_init_hw(struct smb_drv_data *drvdata) +{ + u32 value; + + /* First disable smb and clear the status of SMB buffer */ + smb_reset_buffer_status(drvdata); + smb_disable_hw(drvdata); + smb_purge_data(drvdata); + + /* Using smb in single-end mode, and set other configures default */ + value = SMB_BUF_CFG_STREAMING | SMB_BUF_SINGLE_END | SMB_BUF_EN; + writel(value, drvdata->base + SMB_LB_CFG_LO); + value = SMB_MSG_FILTER(0x0, 0xff); + writel(value, drvdata->base + SMB_LB_CFG_HI); + + writel(SMB_GLOBAL_CFG, drvdata->base + SMB_CFG_REG); + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLOBAL_INT); + writel(SMB_BUF_INT_CFG, drvdata->base + SMB_LB_INT_CTRL); +} + +static int smb_register_sink(struct platform_device *pdev, + struct smb_drv_data *drvdata) +{ + struct coresight_platform_data *pdata = NULL; + struct coresight_desc desc = { 0 }; + int ret; + + pdata = coresight_get_platform_data(&pdev->dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc.ops = &cs_ops; + desc.pdata = pdata; + desc.dev = &pdev->dev; + desc.groups = smb_sink_groups; + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); + if (!desc.name) { + dev_err(&pdev->dev, "Failed to alloc coresight device name."); + return -ENOMEM; + } + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &smb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) { + coresight_unregister(drvdata->csdev); + dev_err(&pdev->dev, "Failed to register misc, ret=%d.\n", ret); + } + + return ret; +} + +static void smb_unregister_sink(struct smb_drv_data *drvdata) +{ + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); +} + +/* + * Send ultrasoc messge to control hardwares on the tracing path, + * using DSM calls to avoid exposing ultrasoc message format. + */ +static int smb_config_inport(struct device *dev, bool enable) +{ + u32 flag = enable ? 1 : 0; + union acpi_object *obj; + guid_t guid; + + if (guid_parse("82ae1283-7f6a-4cbe-aa06-53e8fb24db18", &guid)) { + dev_err(dev, "Get GUID failed.\n"); + return -EINVAL; + } + + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, flag, NULL); + if (!obj) + dev_err(dev, "ACPI handle failed!\n"); + + ACPI_FREE(obj); + + return 0; +} + +static int smb_probe(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata; + int ret; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) { + dev_err(&pdev->dev, "Failed to ioremap resource.\n"); + return PTR_ERR(drvdata->base); + } + + ret = smb_init_data_buffer(pdev, &drvdata->sdb); + if (ret) { + dev_err(&pdev->dev, "Failed to init buffer, ret = %d.\n", ret); + return ret; + } + + smb_init_hw(drvdata); + spin_lock_init(&drvdata->spinlock); + drvdata->pid = -1; + + ret = smb_register_sink(pdev, drvdata); + if (ret) { + dev_err(&pdev->dev, "Failed to register smb sink.\n"); + return ret; + } + + ret = smb_config_inport(&pdev->dev, true); + if (ret) { + smb_unregister_sink(drvdata); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + return 0; +} + +static int smb_remove(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); + int ret; + + ret = smb_config_inport(&pdev->dev, false); + if (ret) + return ret; + + smb_unregister_sink(drvdata); + return 0; +} + +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { + {"HISI03A1", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); + +static struct platform_driver smb_driver = { + .driver = { + .name = "ultrasoc,smb", + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), + .suppress_bind_attrs = true, + }, + .probe = smb_probe, + .remove = smb_remove, +}; +module_platform_driver(smb_driver); + +MODULE_DESCRIPTION("Ultrasoc smb driver"); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen(a)huawei.com>"); +MODULE_AUTHOR("Qi Liu <liuqi115(a)huawei.com>"); diff --git a/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.h new file mode 100644 index 000000000000..01cb846aeedc --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc/ultrasoc-smb.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#ifndef _ULTRASOC_SMB_H +#define _ULTRASOC_SMB_H + +#include <linux/coresight.h> +#include <linux/list.h> +#include <linux/miscdevice.h> + +#include "../coresight-etm-perf.h" +#include "../coresight-priv.h" + +/* Offset of SMB logical buffer registers */ +#define SMB_CFG_REG 0X0 +#define SMB_GLOBAL_EN 0X4 +#define SMB_GLOBAL_INT 0X8 +#define SMB_LB_CFG_LO 0X40 +#define SMB_LB_CFG_HI 0X44 +#define SMB_LB_INT_CTRL 0X48 +#define SMB_LB_INT_STS 0X4C +#define SMB_LB_LIMIT 0X58 +#define SMB_LB_RD_ADDR 0X5C +#define SMB_LB_WR_ADDR 0X60 +#define SMB_LB_PURGE 0X64 + +/* Set SMB_CFG_REG register */ +#define SMB_IDLE_PRD(period) (((period - 216) & 0xf) << 12) +#define SMB_MEM_WR(credit, rate) (((credit) << 16) | ((rate) << 18)) +#define SMB_MEM_RD(credit, rate) (((credit) << 22) | ((rate) << 24)) +#define SMB_BURST_LEN(len) ((len - 1) << 4) +#define SMB_GLOBAL_CFG (SMB_IDLE_PRD(231) | SMB_MEM_WR(0x3, 0x0) | \ + SMB_MEM_RD(0x3, 0x6) | SMB_BURST_LEN(16)) + +/* Set SMB_GLOBAL_INT register */ +#define SMB_INT_EN BIT(0) +#define SMB_INT_TYPE_PULSE BIT(1) +#define SMB_INT_POLARITY_HIGH BIT(2) +#define SMB_GLB_INT_CFG (SMB_INT_EN | SMB_INT_TYPE_PULSE | SMB_INT_POLARITY_HIGH) + +/* Set SMB_LB_CFG_LO register */ +#define SMB_BUF_EN BIT(0) +#define SMB_BUF_SINGLE_END BIT(1) +#define SMB_BUF_INIT BIT(8) +#define SMB_BUF_CONTINUOUS BIT(11) +#define SMB_FLOW_MASK GENMASK(19, 16) +#define SMB_BUF_CFG_STREAMING (SMB_BUF_INIT | SMB_BUF_CONTINUOUS | SMB_FLOW_MASK) +#define SMB_BASE_LOW_MASK GENMASK(31, 0) + +/* Set SMB_LB_CFG_HI register */ +#define SMB_MSG_FILTER(lower, upper) ((lower & 0xff) | ((upper & 0xff) << 8)) +#define SMB_BUF_INT_EN BIT(0) +#define SMB_BUF_NOTE_MASK GENMASK(11, 8) +#define SMB_BUF_INT_CFG (SMB_BUF_INT_EN | SMB_BUF_NOTE_MASK) + +/** + * struct smb_data_buffer - Details of the buffer used by SMB + * @buf_base : Memory mapped base address of SMB. + * @start_addr : SMB buffer start Physical address. + * @buf_size : Size of the buffer. + * @data_size : Size of Trace data copy to userspace. + * @rd_offset : Offset of the read pointer in the buffer. + */ +struct smb_data_buffer { + void __iomem *buf_base; + u32 start_addr; + unsigned long buf_size; + unsigned long data_size; + unsigned long rd_offset; +}; + +/** + * struct smb_drv_data - specifics associated to an SMB component + * @base: Memory mapped base address for SMB component. + * @csdev: Component vitals needed by the framework. + * @sdb: Data buffer for SMB. + * @miscdev: Specifics to handle "/dev/xyz.tmc" entry. + * @spinlock: Only one at a time pls. + * @reading: Synchronise user space access to SMB buffer. + * @pid: Process ID of the process being monitored by the session + * that is using this component. + * @mode: how this SMB is being used, perf mode or sysfs mode. + */ +struct smb_drv_data { + void __iomem *base; + struct coresight_device *csdev; + struct smb_data_buffer sdb; + struct miscdevice miscdev; + spinlock_t spinlock; + local_t reading; + pid_t pid; + u32 mode; +}; + +#define smb_simple_func(type, name, offset) \ +static ssize_t name##_show(struct device *_dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + type *drvdata = dev_get_drvdata(_dev->parent); \ + u32 val = readl(drvdata->base + offset); \ + \ + return sysfs_emit(buf, "0x%x\n", val); \ +} \ +static DEVICE_ATTR_RO(name) + +#endif -- 2.33.0

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CoreSight November 2021