CoreSight April 2019

coresight@lists.linaro.org

8 participants
11 discussions

[RFC] Trace-based execution time profiling (timestamp in perf-script?)

by Wojciech Żmuda

Hello, I'm trying to design a solution to use CoreSight for measuring application execution time, with granularity of specific ranges of instructions. I have some idea how this may be achieved and I'd like to know your opinion. Great inspiration comes from this patch set by Leo Yan, especially from the disassembly script: https://lists.linaro.org/pipermail/coresight/2018-May/001325.html Analyzing this, I learned that perf-script is capable of understanding perf.data AUXTRACE section and parsing some of the trace elements to branch samples, which illustrate how the IP moved around. These pieces of information are available for the built-in python interpreter, so we can script it to get assembly from the program image. If I understand perf-script in its current shape correctly, it ignores all the non-branching events (so everything that's not an ATOM, EXCEPTION or TRACE_ON packet) - specifically, timestamping is lost during the process. I'd like to modify perf-script to generate samples on such timing events, so later I can have them in between assembly instructions to calculate deltas and be able to tell either: - how much time and/or CPU cycles have been spent between two arbitrary instructions (ideally), or - what instructions have been executed between timestamp T and T+1 (this seems to be more in-line with how timestamping in CS works, I think) Brief analysis of tools/perf/util.cs-etm.c and cs-etm-decoder/cs-etm-decoder.c suggests that timestamp events are not turned into packets, but merely recorded as a packet queue parameter (I'm not sure why this is needed, though). The cycacc event is not processed further at all, beside being later decoded to plaintext by OpenCSD. I think it may be worth to give them both a dedicated `enum cs_etm_sample_type` value and packet generator functions. Then, I think, it should be possible to generate samples (not sure what type though, perhaps not 'branch' this time) for timestamp/cycacc packets, analogically to what has been done for TRACE_ON https://lists.linaro.org/pipermail/coresight/2018-May/001327.html and then expose it in the python interface. I'd be grateful for any opinion about this idea, especially about usefulness of such feature for the general audience, as well as any possible compatibility issues. If you are aware of another approach to achieve timestamp correlation with branch samples, it would also be very welcome. I hope the idea is not completely pointless. I'm still making my way through the perf subsystem, so I might have missed some crucial details. Thank you for your time, Wojciech

5 years, 6 months

[PATCH v2 00/36] coresight: Support for ACPI bindings

by Suzuki K Poulose

This series adds the support for CoreSight devices on ACPI based platforms. The device connections are encoded as _DSD graph property[0], with CoreSight specific extensions to indicate the direction of data flow as described in [1]. Components attached to CPUs are listed as child devices of the corresponding CPU, removing explicit links to the CPU like we do in the DT. The majority of the series cleans up the driver and prepares the subsystem for platform agnostic firwmare probing, naming scheme, searching etc. We introduce platform independent helpers to parse the platform supplied information. Thus we rename the platform handling code from: of_coresight.c => coresight-platform.c The CoreSight driver creates shadow devices that appear on the Coresight bus, in addition to the real devices (e.g, AMBA bus devices). The name of these devices match the real device. This makes the device name a bit cryptic for ACPI platform. So this series also introduces a generic platform agnostic device naming scheme for the shadow Coresight devices. Towards this we also make changes to the way we lookup devices to resolve the connections, as we can't use the names to identify the devices. So, we use the "fwnode_handle" of the real device for the device lookups. Towards that we clean up the drivers to keep track of the "CoreSight" device rather than the "real" device. However, all real operations, like DMA allocation, Power management etc. must be performed on the real device which is the parent of the shadow device. Finally we add the support for parsing the ACPI platform data. The power management support is missing in the ACPI (and this is not specific to CoreSight). The firmware must ensure that the respective power domains are turned on. The last 3 patches in the series also exposes the device connections via sysfs by symlinks to indicate the trace data paths. Patches 01 - 05 : General cleanups and a fix. Patches 06 - 13 : Cleanup the drivers for tracking the CoreSight device instead of the parent device. Patches 14 - 20 : Introduce platform agnostic APIs for firmware data probing. Patches 21 - 26 : Prepare for reusing and freeing up the platform data description for device connections and references. Patches 27 - 30 : Use fwnode handles and introduce generic naming scheme. Patches 31 - 33 : Introduce ACPI bindings support Patches 34 - 36 : RFC - expose device connections via sysfs Applies on Mathieu's coresight/next tree. Tested on a Juno-r0 board with ACPI bindings patch (Patch 37/36) added on top of [2]. You would need to make sure that the debug power domain is turned on before the Linux kernel boots. (e.g, connect the DS-5 to the Juno board while at UEFI). arm32 code is only compile tested. [0] ACPI Device Graphs using _DSD (Not available online yet, approved but awaiting publish and eventually should be linked at). https://uefi.org/sites/default/files/resources/_DSD-implementation-guide-to… [1] https://developer.arm.com/docs/den0067/latest/acpi-for-coresighttm-10-platf… [2] https://github.com/tianocore/edk2-platforms.git Changes since v1: [ http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/639963.html ] - Dropped the replicator driver merge changes as they were pulled already. - Cleanups for Power management in the drivers. - Reuse platform description for connection information. Also introduce routines to clean up the platform description to make sure we drop the references (fwnode_handle). - Add RFC patches for exposing the device-links via sysfs. - Drop tracking the device in favour of coresight_device. - Name etb10 as "etb" - Fix other comments in v1. - Use a generic helper for searching with fwnode_handle rather than adding one for CoreSight. Suzuki K Poulose (36): coresight: Fix freeing up the coresight connections coresight: etb10: Cleanup power management coresight: tpiu: Cleanup power management coresight: catu: Cleanup power management coresight: tmc: Cleanup power management coresight: funnel: Clean up device book keeping coresight: replicator: Cleanup device tracking coresight: tmc: Clean up device specific data coresight: catu: Cleanup device specific data coresight: tpiu: Clean up device specific data coresight: stm: Cleanup device specific data coresight: etm: Clean up device specific data coresight: etb10: Clean up device specific data coresight: Rename of_coresight to coresight-platform coresight: etm3x: Rearrange cp14 access detection coresight: stm: Rearrange probing the stimulus area coresight: tmc-etr: Rearrange probing default buffer size coresight: platform: Make memory allocation helper generic coresight: Introduce generic platform data helper coresight: Make device to CPU mapping generic coresight: Remove cpu field from platform data coresight: Remove name from platform description coresight: Cleanup coresight_remove_conns coresight: Reuse platform data structure for connection tracking coresight: Rearrange platform data probing coresight: Add support for releasing platform specific data drivers: Add a generic helper to match device by fwnode handle coresight: platform: Use fwnode handle for device search coresight: Use fwnode handle instead of device names coresight: Use platform agnostic names coresight: stm: ACPI support for parsing stimulus base coresight: Support for ACPI bindings coresight: acpi: Support for components [RFC] coresight: Pass coresight_device for coresight_release_platform_data [RFC] coresight: add return value for fixup connections [RFC] coresight: Expose device connections via sysfs drivers/acpi/acpi_amba.c | 9 + drivers/base/devcon.c | 5 - drivers/base/property.c | 6 + drivers/hwtracing/coresight/Makefile | 3 +- drivers/hwtracing/coresight/coresight-catu.c | 43 +- drivers/hwtracing/coresight/coresight-catu.h | 1 - drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +- drivers/hwtracing/coresight/coresight-etb10.c | 65 +- drivers/hwtracing/coresight/coresight-etm.h | 6 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 12 +- drivers/hwtracing/coresight/coresight-etm3x.c | 45 +- drivers/hwtracing/coresight/coresight-etm4x.c | 36 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 - drivers/hwtracing/coresight/coresight-funnel.c | 27 +- drivers/hwtracing/coresight/coresight-platform.c | 740 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 3 + drivers/hwtracing/coresight/coresight-replicator.c | 37 +- drivers/hwtracing/coresight/coresight-stm.c | 110 ++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 44 +- drivers/hwtracing/coresight/coresight-tmc.c | 100 +-- drivers/hwtracing/coresight/coresight-tmc.h | 1 - drivers/hwtracing/coresight/coresight-tpiu.c | 30 +- drivers/hwtracing/coresight/coresight.c | 291 ++++++-- drivers/hwtracing/coresight/of_coresight.c | 297 --------- include/linux/coresight.h | 65 +- include/linux/property.h | 1 + 27 files changed, 1378 insertions(+), 613 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-platform.c delete mode 100644 drivers/hwtracing/coresight/of_coresight.c ACPI bindings for Juno-r0 (applies on [2] above) Suzuki K Poulose (1): edk2-platform: juno: Update ACPI CoreSight Bindings Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl | 241 +++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) -- 2.7.4

5 years, 6 months

Crash when processing CoreSight trace

by Robert Walker

Hi, I've noticed that recent versions of perf will crash when processing CoreSight trace with some combinations of decoding options. The crash occurs when neither the 'b' (branch events), or 'l' flag (last branch entries) options to --itrace are specified for the perf report/script/inject commands - e.g. 'perf report --itrace=i1000i'. The default flags includes 'b', so the crash doesn't occur if no '--itrace' option is given. The crash appears to be due to the prev_packet field of cs_etm_queue (tools/perf/util/cs-etm.c) not being initialised unless either 'b' or 'l' is included in the trace flags. There seems to have been a number of uses of this field added without checking whether it's valid - these have been added in 5.0 (e.g. commits 7100b12: perf cs-etm: Generate branch sample for exception packet, 24fff5e: perf cs-etm: Avoid stale branch samples when flush packet) and there have been more added for 5.1-rc1: (06220bf: perf cs-etm: Set sample flags for instruction range packet and related commits) As this field is used more widely now and it's already hard to follow which functions have been called in a context where the validity of prev_packet has been checked (i.e. "if (etm->synth_opts.last_branch || etm->sample_branches) { ... }", I think it would be better to create prev_packet in all cases. Regards Rob

5 years, 6 months

[RFC PATCH v1] perf test: Introduce script for Arm CoreSight testing

by Leo Yan

We need a simple method to test Perf with Arm CoreSight drivers, this could be used for smoke testing when new patch is coming for perf or CoreSight drivers, and we also can use the test to confirm if the CoreSight has been enabled successfully on new platforms. This patch introduces the shell script record+script_arm_cs_etm.sh, it's under the 'pert test' framework. The testing rationale is firstly to search ETR devices under the folder '/sys/bus/coresight/devices/', then traverse for every ETR device to verify trace data recording and decoding. If any ETR device fails for the testing, the test will report failure with directly exiting. This test will be only applied on the platform with PMU event 'cs_etm//', otherwise will skip this testing. Below is detailed usage for it: # cd $linux/tools/perf -> This is important so can use shell script # perf test list [...] 61: Check open filename arg using perf trace + vfs_getname 62: Check Arm CoreSight trace data recording and branch samples 63: Add vfs_getname probe to get syscall args filenames 64: Use vfs_getname probe to get syscall args filenames # perf test 62 62: Check Arm CoreSight trace data recording and branch samples: Ok Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- .../tests/shell/record+script_arm_cs_etm.sh | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100755 tools/perf/tests/shell/record+script_arm_cs_etm.sh diff --git a/tools/perf/tests/shell/record+script_arm_cs_etm.sh b/tools/perf/tests/shell/record+script_arm_cs_etm.sh new file mode 100755 index 000000000000..5f1940f57e1f --- /dev/null +++ b/tools/perf/tests/shell/record+script_arm_cs_etm.sh @@ -0,0 +1,47 @@ +#!/bin/sh +# Check Arm CoreSight trace data recording and branch samples + +# Uses the 'perf record' to record trace data with Arm CoreSight ETR as the +# output, then checks if there have any branch samples are generated by +# CoreSight with 'perf script' command. + +# Leo Yan <leo.yan(a)linaro.org>, 2019 + +perfdata=$(mktemp /tmp/__perf_test.perf.data.XXXXX) +file=$(mktemp /tmp/temporary_file.XXXXX) + +skip_if_no_cs_etm_event() { + perf list | grep -q 'cs_etm//' && return 0 + + # cs_etm event doesn't exist + return 2 +} + +skip_if_no_cs_etm_event || exit 2 + +record_touch_file() { + echo "Recording open file: $1" + perf record -o ${perfdata} -e cs_etm/@$1/ --per-thread touch $file +} + +perf_script_filenames() { + echo "Looking at perf.data file for branch samples:" + perf script -F,-time -i ${perfdata} | \ + egrep " +touch +[0-9]+ .* +branches: +" +} + +arm_cs_etr_test() { + for i in /sys/bus/coresight/devices/*.etr; do + record_touch_file `basename $i` && perf_script_filenames + err=$? + + rm -f ${perfdata} + rm -f ${file} + + # Exit when find failure + [ $err != 0 ] && exit $err + done +} + +arm_cs_etr_test +exit 0 -- 2.17.1

5 years, 6 months

Re: [RFC PATCH v1] perf test: Introduce script for Arm CoreSight testing

by Wojciech Żmuda

Hi Leo, I ran your script on a Zynq Ultrascale+ devboard with 'perf test ...' and it succeeded. After examining the source code, I came up with the following questions: 1) What about other sinks? For now I see it is hardcoded to look for sysfs devices with *.etr only. For example, Zynq US+ has one TMC-ETR and two TMC-ETFs - shouldn't ETFs be tested as well? 2) Is there any sink naming convention? AFAIR sysfs file names depend on what's in DTS. I can imagine a situation where I have two ETRs with nodes names etr1@88f00f00, etr2@88f00f80 - the script will not discover them. I took a brief look at the bindings document and I don't see any obvious remarks on how should we name DTS nodes. Sorry if I confused something here, but perhaps this is the right moment to establish such convention? Best regards, Wojciech

5 years, 6 months

[PATCH v2 00/16] coresight: Add support for CPU-wide trace scenarios

by Mathieu Poirier

This is the second revision of a patchset that adds support for CPU-wide trace scenarios and as such, it is now possible to issue the following commands: # perf record -e cs_etm/(a)20070000.etr/ -C 2,3 $COMMAND # perf record -e cs_etm/(a)20070000.etr/ -a $COMMAND The solution is designed to work for both 1:1 and N:1 source/sink topologies, though the former hasn't been tested for lack of access to HW. Most of the changes revolve around allowing more than one event to use a sink when operated from perf. More specifically the first event to use a sink switches it on while the last one is tasked to aggregate traces and switching off the device. This is the kernel part of the solution, with the user space portion to be released in a later set. All patches (user and kernel) have been rebased on v5.1-rc2 and are hosted here[1]. Everything has been tested on Juno and 410c dragonboard platforms. Regards, Mathieu [1]. https://git.linaro.org/people/mathieu.poirier/coresight.git (5.1-rc2-cpu-wide-v2) == Changes for V2 == * Using define ETM4_CFG_BIT_CTXTID rather than hard coded value (Suzuki). * Moved pid out of struct etr_buf and into struct etr_perf_buffer (Suzuki). * Removed code related to forcing double buffering (Suzuki). * Fixed function reallocarray() for older distributions (Mike). * Fixed counter configuration when dealing with errors(Leo). * Automatically selecting PID_IN_CONTEXTIDR with ETMv4 driver. * Rebased to v5.1-rc2. Mathieu Poirier (16): coresight: pmu: Adding ITRACE property to cs_etm PMU coresight: etm4x: Add kernel configuration for CONTEXTID coresight: etm4x: Configure tracers to emit timestamps coresight: Adding return code to sink::disable() operation coresight: Move reference counting inside sink drivers coresight: Properly address errors in sink::disable() functions coresight: Properly address concurrency in sink::update() functions coresight: perf: Clean up function etm_setup_aux() coresight: perf: Refactor function free_event_data() coresight: Communicate perf event to sink buffer allocation function coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() coresight: tmc-etr: Introduce the notion of process ID to ETR devices coresight: tmc-etr: Allow events to use the same ETR buffer coresight: tmc-etr: Add support for CPU-wide trace scenarios coresight: tmc-etf: Add support for CPU-wide trace scenarios coresight: etb10: Add support for CPU-wide trace scenarios drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 83 +++++-- .../hwtracing/coresight/coresight-etm-perf.c | 37 +++- drivers/hwtracing/coresight/coresight-etm4x.c | 120 ++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 82 +++++-- .../hwtracing/coresight/coresight-tmc-etr.c | 204 +++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.c | 2 + drivers/hwtracing/coresight/coresight-tmc.h | 6 + drivers/hwtracing/coresight/coresight-tpiu.c | 9 +- drivers/hwtracing/coresight/coresight.c | 28 +-- include/linux/coresight-pmu.h | 2 + include/linux/coresight.h | 7 +- tools/include/linux/coresight-pmu.h | 2 + 13 files changed, 482 insertions(+), 101 deletions(-) -- 2.17.1

5 years, 6 months

Changing build-id cache a.k.a ~/.debug directory

by Wojciech Żmuda

Hello, The OpenCSD manual HOWTO.md mentions the ~/.debug directory with the following comment: Perf is expecting files related to the trace capture (perf.data) to be located under ~/.debug [3]. (...) [3]: Get in touch with us if you know a way to change this. Source: https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md I've just discovered how to control this, so I'm sharing. I'm not sure about your pull request policy on OpenCSD contribution, so I decided to use mailing list for that. This setting can be adjusted with the `perf config` command as follows: root@zynq:~# ls -l my_buildid ls: cannot access 'my_buildid': No such file or directory root@zynq:~# perf config --system buildid.dir=/root/my_buildid root@zynq:~# perf record -e cs_etm/(a)fe950000.etf2/u --per-thread ./testprogram Couldn't synthesize bpf events. ^C[ perf record: Woken up 4 times to write data ] Warning: AUX data lost 3 times out of 3! [ perf record: Captured and wrote 0.029 MB perf.data ] root@zynq:~# ls -l my_buildid total 16 drwxr-xr-x 3 root root 4096 Apr 18 16:06 '[kernel.kallsyms]' drwxr-xr-x 3 root root 4096 Apr 18 16:06 '[vdso]' drwxr-xr-x 3 root root 4096 Apr 18 16:06 lib drwxr-xr-x 3 root root 4096 Apr 18 16:06 root More examples on perf-config: http://man7.org/linux/man-pages/man1/perf-config.1.html Best regards, Wojciech

5 years, 6 months

[RFC 00/17] perf tools: Add support for coresight CPU wide trace scenarios

by Mathieu Poirier

This patchset complements the kernel portion of the solution by adding the capability to decode and render traces based on the time they were executed. Most of the changes are related to decoding traces with multiple traceIDs, something that is mandatory when dealing with N:1 source/sink topologies. Both kernel and user space patches have been rebased on yesterday's linux-next and are available here[1]. Note that compiling the perf tools on both target and host platforms in the 5.1 cycle requires the addition of "CORESIGHT=1", i.e: $ make -C tools/perf CORESIGHT=1 VF=1 Moreover this set uses a new decoder callback that was introduced in version 0.11.0 of the openCSD library. Testing with a different version of the library than the one installed on a system can be done by using the CSINCLUDES and CSLIBS environment variables, as described in the library's documentation[2]. As with the kernel portion, I'm only sending to the coresight mailing list because of the merge window. Review and comments would be most appreciated. Thanks, Mathieu [1]. https://git.linaro.org/people/mathieu.poirier/coresight.git/log/?h=next-201… [2]. https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md Mathieu Poirier (17): perf tools: Configure contextID tracing in CPU-wide mode perf tools: Configure timestsamp generation in CPU-wide mode perf tools: Configure SWITCH_EVENTS in CPU-wide mode perf tools: Add handling of itrace start events perf tools: Add handling of switch-CPU-wide events perf tools: Refactor error path in cs_etm_decoder__new() perf tools: Move packet queue out of decoder structure perf tools: Introduce the concept of trace ID queues perf tools: Get rid of unused cpu in struct cs_etm_queue perf tools: Move thread to traceid_queue perf tools: Move tid/pid to traceid_queue perf tools: Mandate using openCSD v0.11.0 perf tools: Use traceID aware memory callback API perf tools: Add support for multiple traceID queues perf tools: Linking PE contextID with perf thread mechanic perf tools: Add notion of time to decoding code perf tools: Add support for CPU-wide trace scenarios tools/build/feature/test-libopencsd.c | 4 +- tools/perf/arch/arm/util/cs-etm.c | 186 +++- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 270 +++-- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 39 +- tools/perf/util/cs-etm.c | 939 ++++++++++++++---- tools/perf/util/cs-etm.h | 104 ++ 6 files changed, 1208 insertions(+), 334 deletions(-) -- 2.17.1

5 years, 7 months

Re: Replicator and funnel binding names

by Leo Yan

On Thu, Apr 04, 2019 at 09:47:53AM +0100, Suzuki K Poulose wrote: > Hi > > On 04/04/2019 05:47, Mathieu Poirier wrote: > > Good day to all, > > > > Suzuki and Leo have recently posted patches to unify the way funnel > > and replicators are supported. Those patches prompted me to have a > > closer look at the bindings we currently use. At this time we have: > > > > Non configurable replicator: "coresight-replicator" > > Configurable replicator: "coresight-dynamic-replicator" > > > > Non Configurable funnel: "coresight-static-funnel" (public but not merged yet) > > Configurable funnel: "coresight-funnel" > > > > This is quite confusing to me and I suggest the following: > > > > Non configurable replicator: "coresight-static-replicator" > > Configurable replicator: "coresight-dynamic-replicator" > > > > Non Configurable funnel: "coresight-static-funnel" > > Configurable funnel: "coresight-dynamic-funnel" > > > > Current bindings would be kept around for backward compatibility but > > marked as obsolete in the coresight DT bindings document. Leo has > > stepped forward to do the work and Rob Herring (DT maintainer) is on > > board with the idea. All we need is to settle on a naming convention, > > hence this email. > > I thought about it when I posted the original suggestion. But didn't want > to disturb the existing compatibles. But given that changing the > "coresight-funnel" doesn't really matter, as long as "primecell" appears > in the list of compatibles. And it is good to have it unified across all > components. So I am happy with the proposal. Cool! Thanks for confirmation, Suzuki. This looks good to me as well, will send patch set soon. Thanks, Leo Yan

5 years, 7 months

[PATCH v3 00/20] coresight: Add support for CPU-wide trace scenarios

by Mathieu Poirier

This is the third revision of a patchset that adds support for CPU-wide trace scenarios and as such, it is now possible to issue the following commands: # perf record -e cs_etm/(a)20070000.etr/ -C 2,3 $COMMAND # perf record -e cs_etm/(a)20070000.etr/ -a $COMMAND The solution is designed to work for both 1:1 and N:1 source/sink topologies, though the former hasn't been tested for lack of access to HW. Most of the changes revolve around allowing more than one event to use a sink when operated from perf. More specifically the first event to use a sink switches it on while the last one is tasked to aggregate traces and switching off the device. This is the kernel part of the solution, with the user space portion to be released in a later set. All patches (user and kernel) have been rebased on v5.1-rc3 and are hosted here[1]. Everything has been tested on Juno, the 410c dragonboard, and hikey620 platforms. Regards, Mathieu [1]. https://git.linaro.org/people/mathieu.poirier/coresight.git (5.1-rc3-cpu-wide-v3) == Changes for v3 == * Added review-by tags (some were dropped due to patch refactoring). * Split IDR and reference counting patches. * Moved IDR to struct tmc_drvdata to support 1:1 source/sink topologies. * Enhanced code comments related to design choices. * Renamed ETR buffer allocation functions to have a stronger perf semantic. * Rebased to v5.1-rc3. == Changes for V2 == * Using define ETM4_CFG_BIT_CTXTID rather than hard coded value (Suzuki). * Moved pid out of struct etr_buf and into struct etr_perf_buffer (Suzuki). * Removed code related to forcing double buffering (Suzuki). * Fixed function reallocarray() for older distributions (Mike). * Fixed counter configuration when dealing with errors(Leo). * Automatically selecting PID_IN_CONTEXTIDR with ETMv4 driver. * Rebased to v5.1-rc2. Mathieu Poirier (20): coresight: pmu: Adding ITRACE property to cs_etm PMU coresight: etm4x: Add kernel configuration for CONTEXTID coresight: etm4x: Skip selector pair 0 coresight: etm4x: Configure tracers to emit timestamps coresight: Adding return code to sink::disable() operation coresight: Move reference counting inside sink drivers coresight: Properly address errors in sink::disable() functions coresight: Properly address concurrency in sink::update() functions coresight: perf: Clean up function etm_setup_aux() coresight: perf: Refactor function free_event_data() coresight: Communicate perf event to sink buffer allocation functions coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() coresight: tmc-etr: Create per-thread buffer allocation function coresight: tmc-etr: Introduce the notion of process ID to ETR devices coresight: tmc-etr: Introduce the notion of reference counting to ETR devices coresight: tmc-etr: Introduce the notion of IDR to ETR devices coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios coresight: tmc-etr: Add support for CPU-wide trace scenarios coresight: tmc-etf: Add support for CPU-wide trace scenarios coresight: etb10: Add support for CPU-wide trace scenarios drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 83 ++++-- .../hwtracing/coresight/coresight-etm-perf.c | 37 ++- drivers/hwtracing/coresight/coresight-etm4x.c | 113 +++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 82 ++++-- .../hwtracing/coresight/coresight-tmc-etr.c | 261 ++++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc.c | 6 + drivers/hwtracing/coresight/coresight-tmc.h | 12 + drivers/hwtracing/coresight/coresight-tpiu.c | 9 +- drivers/hwtracing/coresight/coresight.c | 28 +- include/linux/coresight-pmu.h | 2 + include/linux/coresight.h | 7 +- tools/include/linux/coresight-pmu.h | 2 + 13 files changed, 546 insertions(+), 97 deletions(-) -- 2.17.1

5 years, 7 months

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CoreSight April 2019