On Mon, May 10, 2021 at 10:37 AM Atish Patra atish.patra@wdc.com wrote:
This patch adds all the required content to make RISC-V EBBR compatible. The additional content is not a lot given that we just need to update the architecture specific sections for RISC-V. Rest of the document is ISA agnostic anyways.
Signed-off-by: Atish Patra atish.patra@wdc.com
source/chapter1-about.rst | 86 +++++++++++++++++++++++------ source/chapter2-uefi.rst | 41 +++++++++++++- source/chapter3-secureworld.rst | 12 ++++ source/images/riscv-sbi-intro1.png | Bin 0 -> 11926 bytes source/images/riscv-sbi-intro2.png | Bin 0 -> 23280 bytes source/index.rst | 3 + source/references.rst | 6 ++ 7 files changed, 130 insertions(+), 18 deletions(-) create mode 100644 source/images/riscv-sbi-intro1.png create mode 100644 source/images/riscv-sbi-intro2.png
diff --git a/source/chapter1-about.rst b/source/chapter1-about.rst index 52e61e80b7f9..5097e85ea648 100644 --- a/source/chapter1-about.rst +++ b/source/chapter1-about.rst @@ -158,6 +158,8 @@ easily meet the stricter BBR requirements. By definition, all BBR compliant systems are also EBBR compliant, but the converse is not true.
+This specification is also referenced by RISC-V platform specification [RVPLTSPEC]_.
Conventions Used in this Document
@@ -181,14 +183,12 @@ This document uses the following terms and abbreviations.
.. glossary::
+AARCH64 +------- A64 The 64-bit Arm instruction set used in AArch64 state. All A64 instructions are 32 bits.
- AArch32
Arm 32-bit architectures. AArch32 is a roll up term referring to all
32-bit versions of the Arm architecture starting at ARMv4.
- AArch64 state The Arm 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), Stack Pointer (SP), and
@@ -197,10 +197,6 @@ This document uses the following terms and abbreviations. AArch64 Execution state provides a single instruction set, A64.
- EFI Loaded Image
An executable image to be run under the UEFI environment,
and which uses boot time services.
- EL0 The lowest Exception level on AArch64. The Exception level that is used to execute user applications, in Non-secure state.
@@ -218,17 +214,59 @@ This document uses the following terms and abbreviations. execute Secure Monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.
- Logical Unit (LU)
A logical unit (LU) is an externally addressable, independent entity
within a device. In the context of storage, a single device may use
logical units to provide multiple independent storage areas.
+ARM +---
- AArch32
Arm 32-bit architectures. AArch32 is a roll up term referring to all
32-bit versions of the Arm architecture starting at ARMv4.
- OEM
Original Equipment Manufacturer. In this document, the final device
manufacturer.
+RISC-V +------
- HART
Hardware thread in RISC-V. This is the hardware execution context that contains
all the state mandated by the ISA.
- SiP
Silicon Partner. In this document, the silicon manufacturer.
- HSM
Hart State Management (HSM) is an SBI extension that enables the supervisor
mode software to implement ordered booting.
- HS Mode
Hypervisor-extended-supervisor mode which virtualizes the supervisor mode.
- M Mode
Machine mode is the most secure and privileged mode in RISC-V.
- RISC-V
An open standard Instruction Set Architecture (ISA) based on
Reduced Instruction Set Architecture (RISC).
- RV32
32 bit execution mode in RISC-V.
- RV64
64 bit execution mode in RISC-V.
- RISC-V Supervisor Binary Interface (SBI)
Supervisor Binary Interface. This is an interface between SEE and supervisor
mode in RISC-V.
- SEE
Supervisor Execution Environment in RISC-V. This can be M mode or HS mode.
- S Mode
Supervisor mode is the next privilege mode after M mode where virtual memory is enabled.
- U Mode
User mode is the least privilege mode where user-space application is expected to run.
- VS Mode
Virtulized supervisor mode where the guest OS is expected run when hypervisor is enabled.
+UEFI +----
EFI Loaded Image
An executable image to be run under the UEFI environment,
and which uses boot time services.
UEFI Unified Extensible Firmware Interface.
@@ -240,3 +278,17 @@ This document uses the following terms and abbreviations. UEFI Runtime Services Functionality that is provided to an Operating System after the ExitBootServices() call.
+Miscellaneous +-------------
- Logical Unit (LU)
A logical unit (LU) is an externally addressable, independent entity
within a device. In the context of storage, a single device may use
logical units to provide multiple independent storage areas.
- OEM
Original Equipment Manufacturer. In this document, the final device
manufacturer.
- SiP
Silicon Partner. In this document, the silicon manufacturer.
diff --git a/source/chapter2-uefi.rst b/source/chapter2-uefi.rst index 53c962ab5c25..18a9b5404cba 100644 --- a/source/chapter2-uefi.rst +++ b/source/chapter2-uefi.rst @@ -209,7 +209,7 @@ Resident UEFI firmware might target a specific privilege level. In contrast, UEFI Loaded Images, such as third-party drivers and boot applications, must not contain any built-in assumptions that they are to be loaded at a given privilege level during boot time since they can, for example, -legitimately be loaded into either EL1 or EL2 on AArch64. +legitimately be loaded into either EL1 or EL2 on AArch64 and HS/VS/S mode on RISC-V.
AArch64 Exception Levels
@@ -232,6 +232,45 @@ UEFI-compliant Operating System. In this instance, the UEFI boot-time environment can be provided, as a virtualized service, by the hypervisor and not as part of the host firmware.
+RISC-V Privilege Levels +-----------------------
+Unlike AARCH64, RISC-V doesn't define dedicated privilege levels for hypervisor +enabled platforms. The supervisor mode becomes HS mode where a hypervisor or a hosting-capable +operating system runs while the guest OS runs in virtual S mode (VS mode) as shown in below figures. +Resident UEFI firmware can be executed in M mode or S/HS mode during POST. However, +the UEFI images must be loaded in HS or VS mode if virtualization is available at OS load time.
+.. image:: images/riscv-sbi-intro1.png
- :align: center
+Figure1. RISC-V System without H-extension
+.. image:: images/riscv-sbi-intro2.png
- :align: center
+Figure2. RISC-V System with H-extension
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
+UEFI Boot at VS mode +^^^^^^^^^^^^^^^^^^^^^^
+Booting of UEFI at VS mode is employed within a hypervisor hosted Guest Operating System environment, +to allow the subsequent booting of a UEFI-compliant Operating System. +In this instance, the UEFI boot-time environment can be provided, as a +virtualized service, by the hypervisor and not as part of the host firmware.
UEFI Boot Services
diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 9c51bca24f33..d6bfbd322837 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -27,3 +27,15 @@ Platforms without EL3 must implement one of: However, the spin table protocol is strongly discouraged. Future versions of this specification will only allow PSCI, and PSCI should be implemented in all new designs.
+RISC-V Multiprocessor Startup Protocol +====================================== +The resident firmware in M mode or hypervisor running in HS mode must implement +and conform to at least SBI [RVSBISPEC]_ v0.2 with HART +State Management(HSM) extension for both RV32 and RV64. In addition to that, the +firmware must ensure the following condition before jumping to the UEFI +application.
+The device tree must contain a property named **boot-hartid** under the */chosen* +node. This property must indicate the id of the booting hart. The corresponding entry +in the ACPI tables has not been defined yet as ACPI support in RISC-V is under progress. diff --git a/source/images/riscv-sbi-intro1.png b/source/images/riscv-sbi-intro1.png new file mode 100644 index 0000000000000000000000000000000000000000..953e6529912af2e5b774ec6033abd856262651fe GIT binary patch literal 11926 zcmeI2bySq?*Y8IqRYE`{1e6#+N@@@!q$P$%q!r1bBnPAvL68t(2<h&WE<q$DMH+^Z zk_Kspe6R8OJ<t0*=l7no&imhc);cT}_nMpgy61|0?fu=KYrj=fkte!La~T4G5Gg#A z(SSfMnm`~IE)!e?cf>u4Xdw`8Lj@U0EjOd}#4B!ELp29F(3p->sjHT^5VvL+rQYMQ zU#RI|uLv^XoMK~GY0|TeDt`2!;QBSSLB`8b`W!KuMZUPWmnxDT-wt}RPRL4dD$~+8 z`jYe}0gf-B=VqMH*qE-zzWE}IKNfSIbdItpM1DGsOFU>CNlKJ40G)umB$Oh;UQ>ui znZf0W;wN|#KK4HTAD=JVkbzHkabbku^5J4U4!9`4f@24e^%;5rTr{7cz~7hbB?{p3 znc{zXGkrgnOt2sXt{R$}L)$mDKSOOLbyPbgxF3+>;8x`f*Gz5%1qF3>cIM^ft*js_ zXx`A5DCmEN-X^$=t6u0-V_;@xwy>~Z8a*G05WFh(1XcMGE=5XlIZaPTL&NdM=U4sx z8jgx_nt4NacVEKM7h!~wYHWcBLv?j^2M1nZmL7I1soY1+-!H+eu8cC{NT%M(bHT;M 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diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021 SPDX-License-Identifier: CC-BY-SA-4.0
#################################################### @@ -8,6 +9,8 @@ Embedded Base Boot Requirements (EBBR) Specification
Copyright © 2017-2019 Arm Limited and Contributors.
+Copyright © 2021 Western Digital Corporation or its affiliates.
This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to diff --git a/source/references.rst b/source/references.rst index 6d09d3c0aaa7..5b777a4d032f 100644 --- a/source/references.rst +++ b/source/references.rst @@ -29,3 +29,9 @@ .. [UEFI] `Unified Extensable Firmware Interface Specification v2.8 Errata A https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_A_Feb14.pdf`_, February 2020, `UEFI Forum http://www.uefi.org`_
+.. [RVPLTSPEC] `RISC-V Platform specification https://github.com/riscv/riscv-platform-specs`_
+.. [RVSBISPEC] `RISC-V Supervisor Binary Interface specification https://github.com/riscv/riscv-sbi-doc`_
+.. [RVHYPSPEC] `RISC-V ISA Hypervisor extension https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex`_
2.30.1
boot-architecture mailing list boot-architecture@lists.linaro.org https://lists.linaro.org/mailman/listinfo/boot-architecture
Any comments ?